CN100452394C - Piled double-face electrode package and multi-chip assembly - Google Patents
Piled double-face electrode package and multi-chip assembly Download PDFInfo
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- CN100452394C CN100452394C CNB2004100726240A CN200410072624A CN100452394C CN 100452394 C CN100452394 C CN 100452394C CN B2004100726240 A CNB2004100726240 A CN B2004100726240A CN 200410072624 A CN200410072624 A CN 200410072624A CN 100452394 C CN100452394 C CN 100452394C
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- electrode
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- end surface
- encapsulation
- bridging
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Abstract
The present invention relates to technology of integrated circuit chip encapsulation and microelectronic device assembly. The stacked type double-surface electrode encapsulation and the stacked type multi-chip assembly can be realized by that the upper end surface and the lower end surface of an encapsulation chip can be respectively led out electrodes; the side surface of the encapsulation chip leaves a bridging electrode in advance; the bridging electrode can be used for connecting multiple chips and space bridging chips. In order to realize the stacked type multi-chip assembly, the upper end surface and the lower end surface of the encapsulation chip are respectively provided with plane bridging connecting lines, and a middle transferring layer is formed. The upper end surface and the lower end surface of the middle transferring layer is likewise provided with electrodes and different bridging connecting lines, and the optionally bridging of each electrode of two adjacent stacked type double-surface electrode encapsulation integrated circuit chips can be realized by the middle transferring layer. The forms of the electrodes of the upper end surface and the lower end surface are not limited, the electrode of the upper end surface is a microsphere electrode, and the electrode of the lower end surface is a welding disk electrode. The significance of the present invention is to make a miniature electronic system without PCB possible by a new encapsulation mode and a stacked type circuit assembly mode, and the miniaturization integration of the electronic system can be realized.
Description
Technical field
The present invention relates to integrated circuit (IC) chip encapsulation and microelectronic component packaging technology.
Technical background
All concentrate on many silicon chip encapsulation of silicon chip level at present in the state-of-the-art technology of the involved stacked package in electronic circuit package field, be about in a plurality of silicon chip stacked package to traditional packaged chip, see with the encapsulation of common integrated circuit (IC) chip as broad as long from profile.Such integrated circuit still needs traditional printed circuit board (PCB) (PCB-Printed Circuit Board) that it is formed applicable electronic system.The present invention becomes circuit package two-sided extraction electrode form, by interposer integrated circuit stacking is assembled into together, realizes that the circuit of no traditional PCB connects, the electronic system of no PCB.The reliability that makes electronic system more become microminiaturized, integrated, higher.
Summary of the invention
The technology that the purpose of this invention is to provide a kind of stack double-face electrode encapsulation and stacked multi-chip assembling.
The present invention is by following technical method be achieved (with reference to accompanying drawing 1～3).The stack double-face electrode encapsulates the technology of assembling with stacked multi-chip, draws top electrode 3 from the upper surface 2 of packaged chip 1, and 6 draw bottom electrode 5 in the lower surface, reserves cross-over electrode 4 in packaged chip 1 side and is used for many chip chambers connections and strides the chip connection at interval.Above-mentioned method for packing has constituted stack double-face electrode packaged chip.In order to realize stacked multi-chip assembling, be respectively equipped with plane cross-over connection line 8 at the upper and lower end face 2 and 6 of packaged chip 1, constitute intermediate transit layer 7.Upper surface at the intermediate transit layer is provided with top electrode 3 equally, and the lower surface is provided with bottom electrode 5.And, be designed to different cross-over connection lines 8 at the upper and lower end face of intermediate transit layer 7 according to the needs of circuit design, can realize any cross-over connection of adjacent two each electrodes of stack double-face electrode encapsulated integrated circuit chip by intermediate transit layer 7.Cross-over electrode 4 is also reserved in side in interposer 7, connects in order to chip span chip.The form of upper and lower end face electrode is not limit, and can be designed to variously, reaches reliable connection and gets final product.Top electrode 3 of the present invention is designed to the microballoon electrode, and bottom electrode 5 is designed to pad electrode.At this is example in BGA (Ball GridArray-ball grid array) mode only.Stack double-face electrode packaged chip 1 is assembled into the connection (as Fig. 3) that realizes circuit together by intermediate transit layer 7 stack polyphone in actual applications.
Beneficial effect of the present invention is to make the electronic system of no PCB become possibility by a kind of new double-face electrode packaged type and stack circuit assembling mode.
Description of drawings
Fig. 1 is stack double-face electrode packaged chip structure figure.
Fig. 2 is stacked multi-chip assembling intermediate transit layer structure chart.
Fig. 3 is a stack double-face electrode packaged chip polyphone discharging assembling schematic diagram.
Each chip among the figure is positive and negative layout, to clearly demonstrate the structure of upper and lower end face.
Among the figure: packaged chip-1; Packaged chip upper surface-2; Top electrode-3; Side cross-over electrode-4; Bottom electrode-5; Packaged chip lower surface-6; Intermediate transit layer-7; Bridging wiring-8.
Embodiment
Below the present invention is described further by embodiment.The present invention is that double-faced packaging chip 1 or intermediate transit layer 7 all can be cylinder or cuboid.With accompanying drawing 3 is example, constitutes the electronic system that stacked multi-chip is assembled by three double-faced packaging chips 1 and an intermediate transit layer 7.Middle double-faced packaging chip is the processor with 8031 kernels, and its volume is Φ 5 * 4mm, and the electrode of upper and lower end face is one to one, is 16 programmable I/O mouths, one road reset terminal, one road counting and timing end, and power supply V and power supply ground GND.(volume of interposer is that Φ 5 * 0.5mm) is incorporated into external power source and ground wire in each stack double-faced packaging chip to utilize three side cross-over electrodes 4 and intermediate transit layer 7.In three stack double-faced packaging chips two other is respectively that (its volume is that (its volume is Φ 5 * 10mm) for the control module of Φ 5 * 6mm) and rear end for the data acquisition module of front end.Packaged chip and packaged chip, packaged chip and interposer 7 are all welded together by BGA technology.Constituted a volume has 8 A/D acquisition channels and data processing and controlled function less than Φ 5 * 22mm no PCB miniature electronic system by above-mentioned three stack double-faced packaging chip modules and intermediate transit layer.
Claims (3)
1. encapsulation of stack double-face electrode and stacked multi-chip assembling, top electrode (3) is drawn in the upper surface (2) that it is characterized in that packaged chip (1), (6) draw bottom electrode (5) in the lower surface, and packaged chip (1) side is reserved cross-over electrode (4) and is used for many chip chambers connections and strides chip at interval connecting.
2. according to described stack double-face electrode encapsulation of claim 1 and stacked multi-chip assembling, the upper and lower end face (2) and (6) that it is characterized in that described packaged chip (1) are respectively equipped with plane cross-over connection line (8), constitute intermediate transit layer (7), be provided with top electrode (3) in the upper surface of intermediate transit layer, the lower surface is provided with bottom electrode (5), realizes any cross-over connection of adjacent two each electrodes of stack double-face electrode encapsulated integrated circuit chip by intermediate transit layer (7).
3. according to claim 1 or 2 described stack double-face electrode encapsulation and stacked multi-chip assembling, it is characterized in that described packaged chip (1) and described intermediate transit layer (7) are cylinder or cuboid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100726240A CN100452394C (en) | 2004-11-04 | 2004-11-04 | Piled double-face electrode package and multi-chip assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100726240A CN100452394C (en) | 2004-11-04 | 2004-11-04 | Piled double-face electrode package and multi-chip assembly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1614780A CN1614780A (en) | 2005-05-11 |
| CN100452394C true CN100452394C (en) | 2009-01-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100726240A Expired - Fee Related CN100452394C (en) | 2004-11-04 | 2004-11-04 | Piled double-face electrode package and multi-chip assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100452394C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1239831A (en) * | 1998-06-24 | 1999-12-29 | 日本电气株式会社 | Semiconductor device and method for fabricating the same |
| JP2001085600A (en) * | 1999-09-16 | 2001-03-30 | Seiko Epson Corp | Semiconductor chip, multichip package, semiconductor device, and electronic apparatus |
| US6566232B1 (en) * | 1999-10-22 | 2003-05-20 | Seiko Epson Corporation | Method of fabricating semiconductor device |
-
2004
- 2004-11-04 CN CNB2004100726240A patent/CN100452394C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1239831A (en) * | 1998-06-24 | 1999-12-29 | 日本电气株式会社 | Semiconductor device and method for fabricating the same |
| JP2001085600A (en) * | 1999-09-16 | 2001-03-30 | Seiko Epson Corp | Semiconductor chip, multichip package, semiconductor device, and electronic apparatus |
| US6566232B1 (en) * | 1999-10-22 | 2003-05-20 | Seiko Epson Corporation | Method of fabricating semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1614780A (en) | 2005-05-11 |
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| C06 | Publication | ||
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090114 Termination date: 20111104 |