CN100466219C - 用于低电容布线的可调节自对准空气间隙介质 - Google Patents

用于低电容布线的可调节自对准空气间隙介质 Download PDF

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CN100466219C
CN100466219C CNB2004800274275A CN200480027427A CN100466219C CN 100466219 C CN100466219 C CN 100466219C CN B2004800274275 A CNB2004800274275 A CN B2004800274275A CN 200480027427 A CN200480027427 A CN 200480027427A CN 100466219 C CN100466219 C CN 100466219C
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insulating barrier
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semiconductor device
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R·M·格夫肯
W·T·莫特西夫
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GlobalFoundries Inc
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Abstract

一种可调节自对准低电容集成电路空气间隙结构，包括第一互连(64a)，与互连级上的第二互连(64b)相邻；隔离物(60b、60c)，沿所述第一和第二互连的相邻侧面形成；以及空气间隙(68)，在所述第一和第二互连之间形成。所述空气间隙延伸到所述第一和第二互连的至少一个的上表面(74a、74b)之上以及所述第一和第二互连的至少一个的下表面(76a、76b)之下，以及所述隔离物之间的距离限定所述空气间隙的宽度。所述空气间隙与所述第一和第二互连的相邻侧面自对准。

Description

用于低电容布线的可调节自对准空气间隙介质
技术领域
本发明涉及半导体器件，具体涉及半导体器件中用于低电容布线的可调节自对准空气间隙介质
背景技术
由于半导体芯片中的电路部件的尺寸持续减小，具有在下几个技术代中该技术领域面临的一些互连布线挑战。在这些挑战中，一个问题是在电路布线之间的介质材料中的不希望的电容。一种正在进行以降低互连电容的方法是使用多孔介质。然而，因为这些材料通常具有降低的机械强度和热导率，很难制造芯片并在芯片运行期间散热。在下几个技术代中的其它挑战是预期在布线宽度开始接近其电子平均自由路径时铜布线的电阻率将开始上升。该电阻率上升由于铜的表面和界面粗糙度加剧。双镶嵌沟槽和过孔侧壁贯穿相邻多孔介质区域中的空隙，并使铜电阻率上升。
65nm线宽代面临的另一挑战是物理气相沉积(PVD)或溅射阻挡层将需要替代为化学气相沉积(CVD)或原子气相沉积(ALD)阻挡层，以满足正在进行的厚度减小和一致性改善的需求。如果使用的多孔低k介质材料是开放单元型，如具有连接孔，那么CVD或ALD前体可以扩散进入介质，并降低它的低k特性。同样，依赖于多孔低k介质材料的最大孔尺寸，较薄衬里不能提供连续覆盖来阻止铜扩散进入临近的介质材料。例如，当阻挡层在65nm技术节点需要约50
Figure C200480027427D0005131356QIETU
时，一些现有的多孔低k材料仍然具有200
Figure C200480027427D0005131356QIETU
的最大孔尺寸。
发明内容
考虑到现有技术的问题和缺陷，因此，本发明的一个目的是提供用于半导体器件中具有低电容的介质。
本发明的另一目的是提供当在半导体电路中铜线宽度减小时不具有多孔性问题的低电容介质。
本发明进一步的目的是提供当在半导体电路中铜线宽度减小时不引起铜电阻率增加的低电容介质。
本发明的另一个目的是提供与导线沉积工艺兼容的低电容介质。
在本发明中实现了对于本领域的技术人员将是显而易见的上述和其它目的，本发明旨在可调节自对准低电容集成电路空气间隙结构。一方面，本发明提供了一种半导体器件，包括:第一互连，与互连级上的第二互连相邻；隔离物，沿所述第一和第二互连的相邻侧面形成；以及空气间隙，在所述第一和第二互连之间形成。所述空气间隙延伸到所述第一和第二互连的至少一个的上表面之上以及所述第一和第二互连的至少一个的下表面之下，所述隔离物之间的距离限定所述空气间隙的宽度。所述空气间隙与所述第一和第二互连的相邻侧面自对准。
所述半导体器件优选进一步包括，在所述第一和第二互连的至少一个之下的蚀刻停止层，所述蚀刻停止层位于下面的过孔绝缘层上，从而所述空气间隙延伸到所述第一和第二互连的至少一个的下表面之下相应于所述蚀刻停止层厚度的距离。
优选，与所述第一和第二互连的侧面相邻的所述隔离物包括二氧化硅或氮化硅，所述蚀刻停止层包括碳化硅，以及所述下面的过孔绝缘层包括二氧化硅或氟化二氧化硅。
所述半导体器件优选包括，在所述互连级和所述空气间隙之上的至少一个绝缘层，从而所述空气间隙延伸到所述绝缘层中。在所述互连级和所述空气间隙之上的所述至少一个绝缘层包括氮化硅或氮化硅碳作为覆层，用于所述互连和二氧化硅或氟化二氧化硅作为所述覆层上的绝缘层。
所述半导体器件进一步包括二氧化硅或氮化硅硬掩模隔离物，与所述空气间隙的上部的任一侧自对准，以及所述互连级、所述空气间隙和所述硬掩模隔离物上的绝缘层。所述空气间隙在所述硬掩模隔离物之间延伸并向上延伸到所述绝缘层中。
所述第一和第二互连通过镶嵌工艺或双镶嵌工艺形成，以及包括铜、铝、钨或金。在每个第一和第二互连上，具有可选金属沉积层，包括可选钨层或可选磷化钴钨层。
所述半导体器件进一步包括，在所述第一和第二互连的一个之下的蚀刻停止层，所述蚀刻停止层位于下面的过孔绝缘层上，以及在所述下面的过孔绝缘层之下的第二互连级。在至少一个下面的过孔绝缘层和所述第二互连级之间，设置可选金属沉积层，所述可选金属沉积层包括可选钨层或可选磷化钴钨层。
另一方面，本发明提供了一种用于在半导体器件的互连级上的一对互连之间形成空气间隙的方法，包括以下步骤:沉积半导体器件的多个绝缘层；在所述多个绝缘层上沉积第一硬掩模绝缘层；以及除去部分所述第一硬掩模绝缘层，以暴露所述多个绝缘层的最上层的在其上将要形成互连的区域，所述在其上将要形成互连的区域被隔开。该方法还包括在所述第一硬掩模层和所述多个绝缘层的最上层的暴露区域上沉积第二硬掩模绝缘层，以及除去所述第一硬掩模绝缘层上的部分所述第二硬掩模绝缘层，以暴露所述多个绝缘层的最上层的在其上将要形成互连的区域。这保留与所述多个绝缘层的最上层的在其上将要形成互连的区域相邻的第二硬掩模隔离物。该方法进一步包括利用所述第一硬掩模绝缘层和第二硬掩模隔离物，蚀刻所述下面的多个绝缘层的至少一个以形成互连开口，沉积保形绝缘层以在所述互连开口的侧壁上形成隔离物，以及沉积与所述保形绝缘层隔离物相邻的导电金属，以在所述互连开口中形成互连。然后，该方法蚀刻所述互连和保形绝缘层隔离物之间的部分所述第一硬掩模绝缘层和下面的多个绝缘层，并保留与所述互连和保形绝缘层隔离物相邻的第二硬掩模隔离物，以形成延伸到至少一个所述互连之下的空气间隙，然后，在所述空气间隙上和在所述互连和保形绝缘层隔离物上沉积至少一个绝缘层，以密封所述空气间隙。优选，所述空气间隙延伸到所述互连之上，并延伸到所述至少一个绝缘层中。
所述沉积半导体器件的多个绝缘层的步骤包括以下步骤:沉积半导体器件的第一绝缘覆层；在所述第一绝缘覆层上沉积第二绝缘层；在所述第二绝缘覆层上沉积第三绝缘覆层蚀刻停止层；以及在所述第三绝缘蚀刻停止层上沉积第四绝缘层。在此情况下，除去部分所述第一硬掩模绝缘层的所述步骤暴露所述第四绝缘层的在其上将要形成互连的区域。这也导致在所述互连和保形绝缘层隔离物之间具有所述第一硬掩模绝缘层、第四绝缘层和第三绝缘蚀刻停止层的蚀刻部分，以保留与所述互连和保形绝缘层隔离物相邻的所述第二硬掩模隔离物，并以形成延伸到至少一个所述互连之下的所述空气间隙。
在所述互连之上的所述至少一个绝缘层包括用于所述互连的第五绝缘覆层，和所述覆层之上的第六绝缘层，从而所述空气间隙延伸完全通过所述第五覆层并延伸到部分所述第六绝缘层中。
附图说明
在所附权利要求中具体描述了相信是新颖的本发明的特征以及本发明的元素特性。附图仅是为了说明目的并没有按比例绘制。然而，通过参考下面结合附图的详细描述可以最好地理解本发明本身的组织和操作方法，其中:
图1-11是截面正视图，示出了采用以进行在半导体器件中的本发明的空气间隙介质的一个实施例的工艺步骤。
图12是截面正视图，示出了本发明的空气间隙介质的最终结构的可选实施例，其中用自对准、选择性金属沉积覆层替代下覆层。
具体实施方式
在描述本发明的优选实施例的过程中，这里将参考附图的图1-12，其中相同的标号表示本发明的相同特征。在第一个实施例中，图1描述在先前现有的铜互连布线级上沉积的介质叠层。现有布线级具有衬底介质层20，衬底介质层20包括钨栓塞22、24、26，在衬底介质层20上是沉积的介质层28，介质层28包括在TaN/Ta阻挡层31中的铜线30、32。介质层可以由或不由相同成分构成；例如，介质层20是磷硅玻璃(PSG)而介质层28是未掺杂硅玻璃(USG)或含有硅、碳、氧和氢的玻璃(如甲醇化SiOx、SiCOH)。介质叠层从底部顺序包括覆层34如氮化硅Si3N4，具有良好机械特性和热导率的绝缘层36如USG或氟硅玻璃(FSG)，蚀刻停止层38如SiC，具有良好机械特性和热导率的介质(低k)材料层40如SiCOH，以及第一硬掩模层42如碳化硅SiC。蚀刻停止层38与下面的绝缘层36相比具有高蚀刻速率，以及绝缘层40与蚀刻停止层38相比具有高蚀刻速率。然后，施加抗反射涂层(ARC)44和抗蚀剂层46，并如图2所示进行构图用于沟槽图形开口，随后通过ARC和抗蚀剂开口蚀刻硬掩模层42。下一步，如图3所示，沉积第二硬掩模层48如二氧化硅SiO2或Si3N4。然后，施加并构图过孔抗蚀剂层50以形成过孔抗蚀剂图形开口，如图4所示。然后，通过图形开口蚀刻第二硬掩模层48和过孔开口52，54，下至覆层34，然后剥离过孔抗蚀剂50，如图5所示。
图6示出了仅在第一硬掩模层42的上表面上的第二硬掩模层48的覆盖方向性去除蚀刻，该蚀刻保留与第一硬掩模层42边缘的除了通过过孔光暴露的区域的所有区域相邻的第二硬掩模层隔离物48a、48b、48c，即没有隔离物在过孔52的侧壁上形成。结果，隔离物48a和48b自对准并与沟槽/布线/过孔开口56相邻设置，以及隔离物48c与过孔开口54相邻。隔离物的尺寸由第一和第二硬掩模层的每层的厚度决定。然后蚀刻连接过孔开口52和54的沟槽58，下至蚀刻停止层38。
下一步，在曝露层上和现有结构的过孔开口52、54和沟槽56、58中施加保形沉积的第二绝缘层60如SiO2或Si3N4，如图7所示。然后，进行另一蚀刻，用于覆盖方向性去除硬掩模层42、48和蚀刻停止层38之上的绝缘层60的部分，并用于去除过孔开口52、54和沟槽56的底部的绝缘层60的部分，以及过孔开口52和58之下的覆层34的部分。这保留第二隔离物60加衬过孔开口52、54和沟槽56、56。应该注意的是，因为这些第二隔离物减小沟槽开口56、58和过孔开口52、54的尺寸，当最初形成时，沟槽和过孔光需要被暴露和蚀刻加大隔离物宽度的约两倍。
使用常规阻挡-籽晶层和铜沉积工艺以填充双镶嵌结构，因此首先用阻挡层(如TaN/Ta)和籽晶层62给沟槽和过孔完全加衬，然后用铜64填充，然后用化学机械抛光(CMP)去除剩余材料，如图9所述。代替铜，可采用其它的导电材料如铝、钨或金。图10示出了抗蚀剂阻挡掩模66，用于仅暴露将接收空气间隙介质的区域。通过暴露于氧等离子体、氧反应离子蚀刻(RIE)或氧注入，接着进行稀HF蚀刻，侵蚀层42、40和38的暴露部分SiC、SiCOH、SiC，其如图产生了在未掩蔽的最小空间衬里64a、64b之间具有悬垂物48b、48c的空间68。例如，超临界CO2提供用于稀释HF的载体媒介，以去除氧-侵蚀膜。然后施加各向同性沉积的绝缘氮化物覆层70，如氮化硅、氮化硅碳和二氧化硅或FSG绝缘层72，其关闭了空气间隙层68，而没有将其完全填充，如图11所示。因此，空气间隙68延伸完全通过覆层70，并部分通过绝缘层72，延伸到互连级上。可以通过减小悬垂物48b和48c之间的开口，降低空气间隙68的外来填充。可选地，也可以施加由于其表面张力特性而选择的旋涂介质层，以使空气间隙68不被填充。
在图11中描述的半导体器件的结构中，互连布线64a(填充前是沟槽开口56)与在相同互连级上的互连布线64b(填充前是沟槽58和过孔开口52、54)隔开并相邻。隔离物60b和60c沿布线64a、64b之间的相邻侧面形成，并且降低空气间隙68的宽度，所以实际空气间隙介质的宽度比隔开布线64a、64b的印刷距离小。在互连64a、64b之间形成的空气间隙介质68也延伸到布线的上表面74a、74b之上以及布线的下表面76a、76b之下。形成的空气间隙68与互连布线64a、64b的相邻侧面自对准。
在图12中完全示出的另一个实施例使用与上述类似的工艺顺序，除了在铜布线30、32、64a、64b上用自对准金属覆层34′和70′替代氮化硅Si3N4覆层34和70。这可以通过选择性金属沉积工艺施加，以及金属覆层包括选择性钨或选择性磷化钴钨层。在采用自对准金属覆层70′的情况下，绝缘层72仅关闭空气间隙68的顶部。
因而，本发明提供自对准和可调整空气间隙介质，以减小相邻、相近间隔的导线或过孔之间的电容。相邻铜线之上和之下的空气间隙的高度可以选择，以切断边缘电容和增加结构的有效电阻(k)。采用的优选过孔介质是具有相对良好机械特性和热导率的氧化物如USG或FSG。牺牲沟槽介质和蚀刻停止层可用于产生空气间隙，以及它们可以由较高热导率和机械强度的材料构成。可以使用阻挡掩模，以使具有最小间隔并需要低电容的芯片上的区域接收空气间隙。这增加了芯片的热导率和机械稳定性。因为沟槽和过孔由氧化物或氮化物隔离物限定，从而消除了与进入多孔、低k介质的衬里/阻挡层前体相关的问题，如引起介质的Cu污染的阻挡层完整性的问题以及引起Cu电阻率增加的侧壁粗糙的问题。
尽管结合特定优选实施例具体描述了本发明，但是根据上述描述，许多替换、修改和变化对于本领域的技术人员来说是显而易见的。因此，期望所附权利要求将包括落入本发明的真实范围和精神内的任何所述替换、修改和变化。

Claims (19)

1.一种半导体器件，包括：
第一互连，与互连级上的第二互连相邻；
在所述第一和第二互连的至少一个之下的蚀刻停止层，所述蚀刻停止层位于下面的过孔绝缘层上；
隔离物，沿所述第一和第二互连的相邻侧面形成；以及
空气间隙，在所述第一和第二互连之间形成，所述空气间隙延伸到所述第一和第二互连的至少一个的上表面之上，以及所述空气间隙延伸到具有所述蚀刻停止层的所述第一和第二互连的至少一个的下表面之下与所述蚀刻停止层厚度相等的距离，所述隔离物之间的距离限定所述空气间隙的宽度。
2.根据权利要求1的半导体器件，其中所述空气间隙与所述第一和第二互连的相邻侧面自对准。
3.根据权利要求1的半导体器件，其中与所述第一和第二互连的侧面相邻的所述隔离物包括二氧化硅或氮化硅。
4.根据权利要求1的半导体器件，其中所述蚀刻停止层包括碳化硅。
5.根据权利要求1的半导体器件，其中所述下面的过孔绝缘层包括二氧化硅或氟化二氧化硅。
6.根据权利要求1的半导体器件，进一步包括硬掩模隔离物，与所述空气间隙的上部的任一侧自对准。
7.根据权利要求6的半导体器件，其中所述硬掩模隔离物包括二氧化硅或氮化硅。
8.根据权利要求1的半导体器件，进一步包括在所述互连级和所述空气间隙之上的至少一个绝缘层，其中所述空气间隙延伸到所述绝缘层中。
9.根据权利要求8的半导体器件，其中在所述互连级和所述空气间隙之上的所述至少一个绝缘层包括：氮化硅或氮化硅碳作为用于所述第一和第二互连的覆层，和二氧化硅或氟化二氧化硅作为所述覆层上的绝缘层。
10.根据权利要求1的半导体器件，进一步包括硬掩模隔离物，与所述空气间隙的上部的任一侧自对准，以及所述互连级、所述空气间隙和所述硬掩模隔离物上的绝缘层，其中所述空气间隙在所述硬掩模隔离物之间延伸并向上延伸到所述绝缘层中。
11.根据权利要求1的半导体器件，其中所述第一和第二互连通过镶嵌工艺形成。
12.根据权利要求1的半导体器件，其中所述第一和第二互连包括铜、铝、钨或金。
13根据权利要求1的半导体器件，进一步包括在所述第一和第二互连的一个之下的蚀刻停止层，所述蚀刻停止层位于下面的过孔绝缘层上，以及在所述下面的过孔绝缘层之下的第二互连级。
14.根据权利要求13的半导体器件，进一步包括所述至少一个下面的过孔绝缘层和所述第二互连级之间的选择性金属沉积层，所述选择性金属沉积层包括选择性钨层或选择性磷化钴钨层。
15.根据权利要求1的半导体器件，进一步包括在每个所述第一和第二互连之上的选择性金属沉积层，所述选择性金属沉积层包括选择性钨层或选择性磷化钴钨层。
16.根据权利要求11的半导体器件，其中所述镶嵌工艺包括双镶嵌工艺。
17.一种用于在半导体器件的互连级上的一对互连之间形成空气间隙的方法，包括以下步骤：
沉积半导体器件的多个绝缘层；
在所述多个绝缘层上沉积第一硬掩模绝缘层；
除去部分所述第一硬掩模绝缘层，以暴露所述多个绝缘层的最上层的在其上将要形成互连的区域，所述在其上将要形成互连的区域被隔开；
在所述第一硬掩模绝缘层和所述多个绝缘层的最上层的暴露区域上沉积第二硬掩模绝缘层；
除去所述第一硬掩模绝缘层上的部分所述第二硬掩模绝缘层，以暴露所述多个绝缘层的最上层的在其上将要形成所述互连的区域，保留与所述多个绝缘层的最上层的在其上将要形成互连的区域相邻的所述第二硬掩模绝缘层作为第二硬掩模隔离物；
利用所述第一硬掩模绝缘层和第二硬掩模隔离物，蚀刻下面的多个绝缘层的至少一个，以形成互连开口；
沉积保形绝缘层，以在所述互连开口的侧壁上形成隔离物；
沉积与所述保形绝缘层隔离物相邻的导电金属，以在所述互连开口中形成互连；
蚀刻所述互连和保形绝缘层隔离物之间的部分所述第一硬掩模绝缘层和下面的多个绝缘层，并保留与所述互连和保形绝缘层隔离物相邻的第二硬掩模隔离物，以形成延伸到至少一个所述互连之下的空气间隙；
在所述空气间隙上和在所述互连和保形绝缘层隔离物上沉积至少一个绝缘层，以密封所述空气间隙。
18.根据权利要求17的方法，其中所述空气间隙延伸到所述互连之上，并延伸到所述至少一个绝缘层中。
19.根据权利要求17的方法，其中沉积半导体器件的多个绝缘层的所述步骤包括以下步骤：沉积半导体器件的第一绝缘覆层；在所述第一绝缘覆层上沉积第二绝缘覆层；在所述第二绝缘覆层上沉积第三绝缘蚀刻停止层；以及在所述第三绝缘蚀刻停止层上沉积第四绝缘层；
其中除去部分所述第一硬掩模绝缘层的所述步骤暴露所述第四绝缘层的在其上将要形成互连的区域；以及
其中在所述互连和保形绝缘层隔离物之间具有所述第一硬掩模绝缘层、第四绝缘层和第三绝缘蚀刻停止层的蚀刻部分，以保留与所述互连和保形绝缘层隔离物相邻的所述第二硬掩模隔离物，并以形成延伸到至少一个所述互连之下的所述空气间隙。
20.根据权利要求19的方法，其中在所述互连之上的所述至少一个绝缘层包括用于所述互连的第五绝缘覆层，和所述第五绝缘覆层之上的第六绝缘层，其中所述空气间隙延伸完全通过所述第五绝缘覆层并延伸到部分所述第六绝缘层中。
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