CN100472810C - 双栅极及三栅极金属氧化物半导体场效应晶体管装置及其制造方法 - Google Patents

双栅极及三栅极金属氧化物半导体场效应晶体管装置及其制造方法 Download PDF

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CN100472810C
CN100472810C CNB200380101958XA CN200380101958A CN100472810C CN 100472810 C CN100472810 C CN 100472810C CN B200380101958X A CNB200380101958X A CN B200380101958XA CN 200380101958 A CN200380101958 A CN 200380101958A CN 100472810 C CN100472810 C CN 100472810C
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fin
electrode layer
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silicon
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CN1708858A (zh
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M·R·林
J·X·安
Z·克里沃卡皮克
C·E·塔贝里
H·王
B·俞
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Advanced Micro Devices Inc
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Abstract

一种双栅极金属氧化物半导体场效应晶体管(MOSFET)包括鳍部(220)、第一栅极(240)和第二栅极(420)。该第一栅极(240)形成于鳍部(220)的上端，第二栅极(420)则围绕该鳍部(220)和第一栅极(240)。在另一实施例中，一三栅极MOSFET包括鳍部(220)、第一栅极(710)、第二栅极(720)和第三栅极(730)，该第一栅极(710)形成于鳍部(220)的上端，第二栅极(720)紧邻着鳍部(220)形成，第三栅极(730)紧邻着鳍部(220)并相对于第二栅极而形成(720)。

Description

双栅极及三栅极金属氧化物半导体场效应晶体管装置及其制造方法
技术领域
本发明大体上涉及半导体的制造，尤其涉及一种双栅极及三栅极金属氧化物半导体场效应晶体管(MOSFET)组件及其制造方法。
背景技术
组件尺寸的缩小已成为集成电路性能改进和集成电路成本降低的主要因素。由于栅极氧化物厚度和源极/漏极(S/D)结深的限制，将现有的MOSFET组件块体缩小至0.1μ以下的生产制程，即使可能的话，也是很困难的。因此，需要有新的组件结构和新的材料来改进场效应晶体管(FET)的性能。
而双栅极MOSFET为可被选用作取代替现有平面MOSFET的新组件，在双栅极MOSFET中，使用两个栅极来控制沟道显著地抑制了短沟道效应。“鳍式”场效应晶体管(FinFET)是一种最近新研发出来的双栅极构造，该双栅极包括形成于由自行对准双栅极所控制的垂直鳍部(fin)的沟道。鳍部的形成得薄至使两个栅极能一起控制整个完全耗尽的沟道。虽然有双栅极结构，但FinFET在布线和制造技术上仍类似于现有的平面MOSFET。对比其它双栅极结构，FinFET也提供一定范围的沟道长度、CMOS兼容性、及较大的填装密度。
发明内容
根据本发明的实施例所提供的是一种双栅极和三栅极FinFET组件。不像现有的设计，在该FinFET中的每一栅极均能够独立地控制FinFET的沟道。
如实施例中所示和在说明书中展开说明的，根据本发明的目的，披露了在MOSFET中形成栅极的方法，包括形成一鳍部结构，在该鳍部结构上端形成包含栅极电极层的第一栅极结构，和形成围绕着该鳍部结构和该第一栅极结构的第二栅极结构，其中该第二栅极结构包含第二栅极电极层，而该第二栅极电极层和该第一栅极结构的该栅极电极层分开。
根据本发明的另一实施例，披露了一种在MOSFET中形成栅极的方法，包括形成一鳍部，在该鳍部的上端形成第一栅极，形成围绕着该鳍部及第一栅极的第二栅极，以及移除该第二栅极的一部分以暴露出该第一栅极，该移除会造成第二栅极被分成分离的栅极结构。
根据本发明的又一实施例，提供一种双栅极MOSFET，该双栅极MOSFET包括一鳍部、第一栅极结构和第二栅极结构，该第一栅极结构形成于该鳍部的上端，而该第二栅极结构则围绕着该鳍部和第一栅极结构。
根据本发明的再一实施例，提供一种三栅极MOSFET，该三栅极MOSFET包括鳍部，形成于该鳍部上端的第一栅极结构，邻近该鳍部形成的第二栅极结构，以及邻近该鳍部并相对于该第二栅极结构所形成的第三栅极结构。
附图说明
并入且构成本说明书的一部分的附图，连同说明部分而用来说明本发明的实施例，用来解释本发明。在附图中：
图1示出了根据本发明制造一种双栅极MOSFET的示范性制程；
图2至图4示出了根据图1中所述制程制造出的双栅极MOSFET的示范性剖面图；
图5示出了根据本发明的一个实施例，制造一种三栅极MOSFET的示范性制程；
图6至图8示出了根据图5中所述制程制造出的三栅极MOSFET的示范性剖面图；
图9示出了根据本发明的一个实施例，增加鳍部迁移率的示范性结构；以及
图10至图12示出了制造包括薄鳍部体结构的MOSFET的示范性剖面图。
具体实施方式
以下将参照附图详细说明本发明的实施例。在不同的图式中相同的符号表示相同或相似的组件。同时，下列的详细说明并非用来限制本发明，而是，本发明的范围由所附权利要求及其等效内容所界定。
根据本发明的实施例提供的是双栅极和三栅极FinFET组件。不同于传统的设计，该FinFET中的每个栅极能够独立地控制鳍部沟道。
图1示出了根据本发明的具体实施例，制造一种双栅极MOSFET的示范性制程。图2至图4显示根据图1中所述制程制造出的MOSFET的剖面图。
现在参照图1和图2，制程可从绝缘体上硅(SOI)结构开始，该结构包括一硅基板200、埋入式氧化层210及位于埋入式氧化层210上的硅层220(步骤105)，该埋入式氧化层210及硅层220可用公知的方法形成于基板200上，而该埋入式氧化层的厚度范围约可从100埃至2000埃变化，而硅层220的厚度范围约可从200埃至1000埃变化。应了解到硅层220是用来形成鳍部。
第一栅极氧化层230可在硅层220上沉积或热生长(步骤110)，该第一栅极氧化层230形成的厚度范围大约从5埃至50埃。或者，可以使用诸如高K值电介质材料的其它栅极电介质材料。在一实施例中，可以使用氮氧化物作为栅极电介质材料。第一栅极电极层240可以沉积在第一栅极氧化层230上，以形成第一栅极(步骤115)。有许多的材料可用于第一栅极电极层240，例如，第一栅极电极层240可由金属(如：钨、钽、铝、镍、钌、铑、钯、铂、钛、钼等)、含有化合物的金属(如：氮化钛、氮化钽、氧化钌等)、或掺杂的半导体(如：多晶硅、多晶硅锗等)制成。可选择性地在第一栅极电极层240的上端形成覆盖层250(或硬掩膜)以支持图案优化或化学机械抛光(CMP)(步骤120)。覆盖层250可包括例如氮化硅(SiN)材料或能够在制程期间保护栅极电极的一些其它相似类型的材料，覆盖层250可用例如化学气相沉积(CVD)而沉积大约30埃至200埃的厚度范围。
可用公知的光刻技术(例如，电子束(EB)光刻术)来图案化鳍部220和第一栅极230/240(步骤125)。然后可使用已知的蚀刻技术来蚀刻鳍部220和第一栅极230/240(步骤125)。所得的结构300显示于图3中。在结构300中鳍部220和第一栅极230的宽度可约为50埃至500埃。
在形成鳍部220和第一栅极230后，可形成第二栅极。如图4所示，以沉积或热生长的方式形成第二栅极氧化层410(步骤130)。第二栅极氧化层410可以沉积或生长达约5埃至50埃的厚度。或者，可以使用其它的栅极电介质材料，例如，可使用任何高K电介质材料作为栅极电介质材料。第二栅极电极层420可以沉积在第二栅极氧化层410上以形成第二栅极(步骤135)。类似于第一栅极电极240，有许多的材料可用来作为第二栅极电极层420。因而，此结构400可以有两个栅极(即，栅极240和栅极420)独立地控制该鳍部沟道。可以使用公知的MOSFET制程来完成用于双栅极MOSFET的晶体管(例如，形成源极和漏极区)、触点、互联和层间电介质。
图5显示根据本发明的实施例，制造一种三栅极MOSFET的示范性制程。图6至图8显示根据图5中所述制程制造出的三栅极MOSFET的示范性剖面图。可通过施行如上述图1的步骤105至130而开始本制程。沉积第二栅极电极层420后，可在第二栅极电极层420上沉积层间电介质(ILD)610(步骤505)，如图6所示。层间电介质610可以包括，例如，四乙基正硅酸盐(TEOS)或其它类似类型的材料。层间电介质610的厚度使得其可以在第二栅极电极层420的高度上延伸。
然后，如图7所示，可施行化学机械抛光(CMP)或其它相当的技术来平面化晶圆表面，以暴露出第一栅极电极层240(步骤510)。因而，第二栅极电极层420可以分成两个分离的栅极结构，即栅极720和730。根据此架构，可以制成三栅极MOSFET，其中第一栅极电极层240作为第三栅极710。栅极710至730每一个可独立地控制鳍部220。如图8所示，为减少与栅极710的电容耦合，得使用公知技术深蚀刻栅极720和栅极730(步骤515)。公知的MOSFET制程能用来完成用于三栅极MOSFET的晶体管(例如，形成源极和漏极区)、触点、互联和层间电介质。
其它实施例
迁移率是用来改进晶体管性能的一个重要特性。迁移率可受薄膜中的张力(或压力)的状态的影响。例如，张力应变有利于电子迁移率，而压缩应变则有利于空穴迁移率。
图9显示增加鳍部迁移率的结构。如图中所示，该鳍部结构910可通过在半导体基板上形成硅层而形成。根据本发明的一实施例，半导体基板可以是包括一诸如埋入式氧化层的绝缘层的SOI结构，该绝缘层的厚度范围从100埃至2000埃。形成具有埋入式的氧化层的半导体基板的制程在集成电路制造领域是已知技术。
然后可在鳍部结构910的上端形成高压力薄膜(下文中称之为“盖层”)920。在一实施例中，盖层920可以由例如氮化物类材料制成，厚度约在100埃至1000埃范围。也可使用其它的替代材料。蚀刻鳍部910后盖层920予以保留，从而使鳍部910受张力而改进迁移率。
图10至图12显示制造包括薄鳍部体结构的MOSFET的示范性剖面图。如图10所显示，可经由公知的制造技术形成源极区1010、漏极区1020、和鳍部结构1030。例如，SOI结构可包括形成于半导体基板上的绝缘层(例如，埋入式氧化层)，硅薄膜可以形成于SOI结构上。硅薄膜上可沉积出硬掩膜(例如，二氧化硅)。然后经由例如电子束光刻术(e-beam lithography)和蚀刻可形成鳍部结构1030，再用类似的方法形成源极和漏极区1010和1020。
如图11所示，在源极区1010、漏极区1020和鳍部结构1030形成后，可用保护掩膜覆盖该源极区1010、漏极区1020。有许多材料可作为保护掩膜，譬如氮化硅类材料。然后，如图12所示，未受保护的鳍部结构1030的厚度可被减少以形成薄鳍部结构1230。经由蚀刻或一些其它已知的技术可完成此薄鳍部结构1030。
结论
根据本发明所实施的是一种双栅极和三栅极FinFET组件。不像公知的设计，此FinFET的各个栅极均能够独立地控制FinFET沟道。
本发明的上述实施范例提供了示例和说明，但其并不排除其它可能的实施情形，也不是将本发明限制在所揭示的特定形式上。对上述的实施例可作各种的修饰和变化，或可从实作本发明中获得各种的修饰和变化。举例来说，为能够完全了解本发明，在上述说明中阐明了诸如特定材料、结构、化学物质、制程等许多特别的详细说明。然而，并不须凭借在说明书中所特别提出的这些详细说明，也可实施本发明。在其它的例子中，为了避免不必要地模糊了本发明的真实情形，因此并未详细说明公知的制程。在实施本发明时，可以使用公知的沉积、光刻术和蚀刻技术等，因此，在说明书中没有给出这些技术的详细说明。
虽然已详细说明了关于图1和图5的一系列的制程动作，但是在其它实施例中本发明的这些制程的次序是可以改变的。而且，非依赖性动作可并行执行。
除非说明书中已明白说明，否则没有任何在说明书中使用的组件、动作、或指示对本发明而言是关键性或不可或缺的。
本发明的范围将由下列权利要求书及其等效内容所界定。

Claims (10)

1.一种在金属氧化物半导体场效应晶体管中形成栅极的方法，该方法包含以下步骤：
形成硅鳍部结构；
在该硅鳍部结构的上端形成包含栅极电极层的第一栅极结构，该第一栅极结构的宽度与该硅鳍部结构的宽度相同；以及
形成围绕该硅鳍部结构和该第一栅极结构的第二栅极结构，其中该第二栅极结构包含和该第一栅极结构的该栅极电极层分开的第二栅极电极层。
2.如权利要求1所述的方法，其中该形成该硅鳍部结构的步骤包括：
在形成于半导体基板上面的绝缘层上形成硅层。
3.如权利要求2所述的方法，其中该形成第一栅极结构的步骤包括：
在该硅层上形成电介质层；
在该电介质层上面沉积该第一栅极结构的栅极电极层；以及
图案化该栅极电极层。
4.如权利要求1所述的方法，其中该形成第二栅极结构的步骤包括：
在该硅鳍部结构和第一栅极结构的周围形成第二电介质层；
在该第二电介质层上沉积该第二栅极电极层；以及
图案化该第二栅极电极层；其中该第二电介质层分隔该第二栅极结构的该第二栅极电极层和该第一栅极结构的栅极电极层。
5.如权利要求1所述的方法，其中该第一栅极结构和该第二栅极结构邻接于该硅鳍部结构。
6.如权利要求1所述的方法，进一步包括：
用该第一栅极结构和第二栅极结构独立地控制该硅鳍部结构。
7.一种在金属氧化物半导体场效应晶体管中形成栅极的方法，该方法包含以下步骤：
形成鳍部；
在该鳍部的上端形成第一栅极；
形成围绕该鳍部和第一栅极的第二栅极；以及
去除该第二栅极的一部分以暴露出该第一栅极，该去除造成第二栅极被分成分离的栅极结构。
8.如权利要求7所述的方法，其中该形成鳍部的步骤包括：
在形成于半导体基板上面的绝缘层上形成硅层。
9.如权利要求8所述的方法，其中该形成第一栅极的步骤包括：
在该硅层上形成电介质材料；以及
在该电介质材料上面沉积栅极电极层。
10.如权利要求7所述的方法，其中该形成第二栅极的步骤包括：
在该鳍部及该第一栅极的周围形成第二电介质材料；以及
在该第二电介质材料上沉积第二栅极电极层。
CNB200380101958XA 2002-10-22 2003-10-14 双栅极及三栅极金属氧化物半导体场效应晶体管装置及其制造方法 Expired - Lifetime CN100472810C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543753A (zh) * 2010-12-29 2012-07-04 新加坡商格罗方德半导体私人有限公司 改善之鳍式场效晶体管

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8222680B2 (en) 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US7148526B1 (en) 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
WO2004090992A1 (ja) * 2003-04-09 2004-10-21 Nec Corporation 高移動度シリコンチャネルを有する縦型ｍｉｓｆｅｔ半導体装置
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US20040266115A1 (en) * 2003-06-25 2004-12-30 Bor-Wen Chan Method of making a gate electrode on a semiconductor device
US7005330B2 (en) * 2003-06-27 2006-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7196374B1 (en) * 2003-09-03 2007-03-27 Advanced Micro Devices, Inc. Doped structure for FinFET devices
JP4216676B2 (ja) * 2003-09-08 2009-01-28 株式会社東芝 半導体装置
US7888201B2 (en) * 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
KR100552058B1 (ko) * 2004-01-06 2006-02-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
US7056773B2 (en) * 2004-04-28 2006-06-06 International Business Machines Corporation Backgated FinFET having different oxide thicknesses
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7388257B2 (en) * 2004-09-01 2008-06-17 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7170772B1 (en) 2005-07-29 2007-01-30 International Business Machines Corporation Apparatus and method for dynamic control of double gate devices
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7341916B2 (en) * 2005-11-10 2008-03-11 Atmel Corporation Self-aligned nanometer-level transistor defined without lithography
US7326976B2 (en) * 2005-11-15 2008-02-05 International Business Machines Corporation Corner dominated trigate field effect transistor
US20080054361A1 (en) * 2006-08-30 2008-03-06 Infineon Technologies Ag Method and apparatus for reducing flicker noise in a semiconductor device
US8217435B2 (en) 2006-12-22 2012-07-10 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US8173532B2 (en) 2007-07-30 2012-05-08 International Business Machines Corporation Semiconductor transistors having reduced distances between gate electrode regions
JP5285947B2 (ja) * 2008-04-11 2013-09-11 株式会社東芝 半導体装置、およびその製造方法
CN102361011B (zh) * 2008-06-11 2016-06-22 美格纳半导体有限会社 形成半导体器件的栅极的方法
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8796777B2 (en) * 2009-09-02 2014-08-05 Qualcomm Incorporated Fin-type device system and method
KR101056229B1 (ko) 2009-10-12 2011-08-11 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를 구비하는 유기전계발광 표시 장치
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8368146B2 (en) * 2010-06-15 2013-02-05 International Business Machines Corporation FinFET devices
US8021950B1 (en) * 2010-10-26 2011-09-20 International Business Machines Corporation Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation
US9214529B2 (en) * 2011-03-14 2015-12-15 Globalfoundries Inc. Fin Fet device with independent control gate
US9293584B2 (en) * 2011-11-02 2016-03-22 Broadcom Corporation FinFET devices
US8604518B2 (en) 2011-11-30 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Split-channel transistor and methods for forming the same
US8723223B2 (en) 2011-11-30 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Fin field-effect transistors
US8907431B2 (en) * 2011-12-16 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with multiple threshold voltages
WO2013095550A1 (en) 2011-12-22 2013-06-27 Intel Corporation Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
KR101878744B1 (ko) 2012-01-03 2018-07-16 삼성전자주식회사 고 전압 산화물 트랜지스터 및 그 제조방법
US9029863B2 (en) * 2012-04-20 2015-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103383965B (zh) * 2012-05-04 2016-01-20 台湾积体电路制造股份有限公司 混合鳍式场效应晶体管
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
CN103839810B (zh) * 2012-11-21 2017-02-22 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管芯片及其制造方法
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
US8847324B2 (en) 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires
US9634000B2 (en) * 2013-03-14 2017-04-25 International Business Machines Corporation Partially isolated fin-shaped field effect transistors
US9257536B2 (en) 2013-04-22 2016-02-09 Globalfoundries Inc. FinFET with crystalline insulator
KR102066848B1 (ko) 2013-06-24 2020-01-16 삼성전자 주식회사 반도체 소자 및 그 제조 방법
KR20150020848A (ko) * 2013-08-19 2015-02-27 에스케이하이닉스 주식회사 동작 전류가 개선된 수직 채널 pmos 트랜지스터, 이를 포함하는 저항 변화 메모리 장치 및 pmos 트랜지스터의 제조방법
CN105845725B (zh) * 2015-01-12 2019-01-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
KR102251061B1 (ko) 2015-05-04 2021-05-14 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
TWI574402B (zh) 2016-04-28 2017-03-11 國立交通大學 場效電晶體結構
US9953876B1 (en) 2016-09-30 2018-04-24 Globalfoundries Inc. Method of forming a semiconductor device structure and semiconductor device structure
CN106898553A (zh) * 2017-03-16 2017-06-27 北京大学 一种鳍式场效应晶体管及其制备方法
CN106952959B (zh) * 2017-03-16 2020-04-03 北京大学 一种锗硅沟道鳍式场效应晶体管及其制备方法
US10297672B2 (en) 2017-07-13 2019-05-21 Globalfoundries Inc. Triple gate technology for 14 nanometer and onwards
EP3718142A4 (en) * 2017-11-30 2021-09-22 Intel Corporation STRUCTURING RIBS FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
DE102018126911A1 (de) 2017-11-30 2019-06-06 Intel Corporation Gate-Schnitt und Finnentrimmisolation für fortschrittliche Integrierter-Schaltkreis-Struktur-Fertigung

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582794B2 (ja) * 1987-08-10 1997-02-19 株式会社東芝 半導体装置及びその製造方法
JPH03250770A (ja) 1990-02-28 1991-11-08 Sony Corp 半導体装置
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
JP3261306B2 (ja) 1996-04-04 2002-02-25 シャープ株式会社 半導体記憶装置及びその製造方法
US6288431B1 (en) * 1997-04-04 2001-09-11 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
DE10012112C2 (de) * 2000-03-13 2002-01-10 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
WO2001069689A1 (de) 2000-03-16 2001-09-20 Max Roth Energieelement mit fotovoltaïscher schicht
JP4443008B2 (ja) * 2000-06-30 2010-03-31 富士通株式会社 半導体装置及びその製造方法
US6342410B1 (en) * 2000-07-10 2002-01-29 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6359311B1 (en) * 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
KR100431489B1 (ko) * 2001-09-04 2004-05-12 한국과학기술원 플래쉬 메모리 소자 및 제조방법
US6433609B1 (en) 2001-11-19 2002-08-13 International Business Machines Corporation Double-gate low power SOI active clamp network for single power supply and multiple power supply applications
US6800905B2 (en) 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US8222680B2 (en) 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US7148526B1 (en) 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US6812119B1 (en) 2003-07-08 2004-11-02 Advanced Micro Devices, Inc. Narrow fins by oxidation in double-gate finfet
US6876042B1 (en) 2003-09-03 2005-04-05 Advanced Micro Devices, Inc. Additional gate control for a double-gate MOSFET

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543753A (zh) * 2010-12-29 2012-07-04 新加坡商格罗方德半导体私人有限公司 改善之鳍式场效晶体管

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