CN100477207C - 具有三维载体安装集成电路封装阵列的电子模块 - Google Patents

具有三维载体安装集成电路封装阵列的电子模块 Download PDF

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CN100477207C
CN100477207C CNB2006101218061A CN200610121806A CN100477207C CN 100477207 C CN100477207 C CN 100477207C CN B2006101218061 A CNB2006101218061 A CN B2006101218061A CN 200610121806 A CN200610121806 A CN 200610121806A CN 100477207 C CN100477207 C CN 100477207C
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circuit board
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compressing tablet
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CN1941361A (zh
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K·J·克莱德齐克
J·C·恩格尔
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Legacy Electronics Inc
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Abstract

一种用于增加印刷电路板(503)上电路密集度的封装载体(100)。封装载体(100)安装在印刷电路板(503)上，处在第一集成电路封装(507)的顶部，第一集成电路封装(507)也安装在印刷电路板(503)上。载体(100)具有带压片阵列的上主表面(102U)，第二集成电路封装(501)可安装在该压片阵列上。载体(100)具有多根引线，通过该引线将载体(100)表面安装到印刷电路板(503)上。每根载体引线同样与上表面(102U)上压片阵列的单个压片电气连接。载体(100)下方的集成电路封装(507)享有全部或大部分与载体(100)共有的印刷电路板(503)的连接，并随后将集成电路封装(501)安装到载体(100)上。载体(100)还包括散热片或散热结构。

Description

具有三维载体安装集成电路封装阵列的电子模块
本申请是申请日为“2001年3月13日”、申请号为“01809032.X”、题为“具有三维载体安装集成电路封装阵列的电子模块”的分案申请。
技术领域
本发明涉及多芯片电子模块的生产，更确切地说是涉及将多重集成电路封装加入印刷电路板的方法和设备。本发明也涉及具有三维集成电路封装排列的高密集度存储模块。
背景技术
对半导体存储器的需求是高度灵活的。一方面，当这样的存储器与计算机系统的总价格相比相对不是很贵时，则随着计算机的生产倾向于在每个系统中安装的主存储器大大超过普通程序的使用要求量而导致几乎不能满足的需求。另一方面，当它的成本很高时，制造商们通常在每个系统中安装的主存储器量刚好满足普通程序的需求量。虽然计算机的销售价格可能因此被维持在低水平，但最终的用户可能很快会发现，他必须升级他的主存储器。
对大随机存取计算机存储器的不断增长的需求，以及对愈益紧凑型计算机的持续增长的需求，加上对部分半导体制造商们减少每位成本所带来的刺激，已造成不仅大约每三年电路密集度要翻四倍，而且封装和安装电路芯片的技术效率也越来越高。直到20世纪80年代末期，半导体存储芯片通常以双列式管脚封装(DIPP)进行封装。这些DIPP封装的管脚通常直接焊接到主电路板(比如，母板)中的通孔内，或者插入插座内，该插座随后被焊接到主电路板中的通孔内。随着表面安装技术的出现，传统的在印刷电路板上的电镀通孔已被导电安装压片代替。小外形J-引线(SOJ)封装已发展成薄的小外形封装(TSOP)。因为相邻表面安装管脚中心之间的间距或间隔明显少于传统通孔元件的传统0.10英寸的间隔，所以表面安装芯片将显著地小于对应的传统芯片，从而在印刷电路板上占据更少的空间。另外，由于不再需要通孔，所以表面安装技术适用于在印刷电路板两侧上元件的安装。在两侧都利用表面安装封装的存储模块已成为标准。将早期的单列式存储模块(SIMM)和当今使用的双列式存储模块(DIMM)都被插入母板上的插座中。
通过制造这样的模块，即其中的多个诸如存储芯片之类的集成电路(IC)芯片是以三维排列叠加的，可非常显著地增加封装密集度。一般地讲，芯片的三维叠加需要复杂且非标准封装的方法。
在Floyd Eide的美国专利号为4,956,694的题为“集成电路芯片叠加”的专利中，提供了一个IC芯片垂直叠加的例子。多个集成电路在封装载体内封装并在印刷电路板上将一个叠加到另一个之上。除了芯片选择终端，芯片上所有其它类似终端的都平行地连接。
在Fox等的美国专利号为5,128,831的题为“包含通过注入焊料的通路互相电气互连的叠加的子模块的高密集度电子封装”的专利中，给出了另一个芯片叠加的例子。该封装由单独可测试的子模块组装，每个都有与之键合的单个芯片。子模块以框形间隔交错插入。子模块和间隔都有可提供不同子模块之间互连的可对准通路。
同样由Floyd Eide发表题为“具有加入到重叠基片中并与该片线连的芯片的IC芯片封装”是另一个例子。这样的封装包括具有上工作表面的芯片，该芯片与在其上表面有导电轨迹的下基片层的下表面键合，其中，该轨迹在其周边上的导电压片上终止。工作表面上的终端与该轨迹之间的连接通过下基片层中各个孔的线连接制成的。与下基片层键合的上基片层具有与那些下基片层各个孔相一致的孔并提供在其中可进行线连接的空间。在完成线连接之后，孔被注入环氧树脂以形成单独可测试的子模块。多重子模块可叠加并用连接于其边缘的金属条互相连接。
在A.U.Levy等人的美国专利号5,869,353的题为“模块板叠加过程”的专利中披露了芯片叠加模块的最后一个例子。制造多块面板，在该面板中有孔，在该面板的底部有芯片安装压片的阵列，还有对接的导电压片。芯片安装压片和对接的导电压片都用焊料胶涂层。塑料封装的表面安装IC芯片都位于胶覆盖的安装压片上，多个面板以层排列叠加，且加热叠加层以将芯片引线与安装压片和邻近面板的对接压片焊接在一起。随后通过切割和裂开操作将单个的芯片封装叠加层从面板叠加层分离。
从上述的例子可看到，通过对复杂的封装和叠加排列的使用可取得增大的芯片密集度，这当然必定要在每位存储上的较高成本反映出来。
发明内容
本发明使印刷电路板上的电路密集度增加。本发明对增加用于计算机系统的存储模块上存储芯片的密集度特别有用。本发明包括封装载体，它被设计安装在第一集成电路(IC)封装顶部的印刷电路板(PCB)上，其中的第一集成电路(IC)封装也安装在PCB上。载体有上主表面，该表面有在其上可安装第二IC封装的压片阵列。当安装在第一IC封装的顶部时，载体可被认为是顶盖，在其顶部可安装第二IC封装。载体具有多根引线，通过该引线载体可表面安装到PCB上。每根载体引线也与上表面压片阵列的单片电气连接。本发明还包括多芯片模块，该模块用至少一个PCB、至少一个封装载体和至少两个IC封装进行组装。因为在多芯片模块中，载体下方的IC封装共享全部或大部分共同与安装在其上的IC封装相连的连接，所以载体的引线和载体下方封装的单个引线可共享PCB上的安装/连接压片。当必须通过载体上类似的固定引线和载体下方的封装来完成分离连接时，PCB上相应的片可被分开从而使每根引线都具有独一无二的连接。
载体的第一实施例包括具有第一压片阵列的个体，以两平行的线性行压片排列并粘附到它的上主表面。IC封装的引线可导电地与第一压片阵列的压片相键合。个体还具有第二压片阵列，以两平行的线性行压片沿着纵向边缘固定排列并粘附到它的下主表面。第一和第二阵列片用电镀通路或通孔互相连接。载体引线导电地与第二阵列片键合。载体结合了散热片特征。载体第一侧上的端引线都是电源引线。这两根电源引线由第一薄片互相连接，该薄片与这两根引线连续并在这两根引线之间延伸，而且会延伸载体的整个长度。第一薄片的端位置可裸露在载体的每一端从而简化向周围空气的热传送。载体第二侧上的端引线都是地引线。这两根地引线由第二薄片互相连接，该薄片在这两根引线之间连续并延伸，而且会延伸载体的整个长度。第二薄片的端位置可裸露在载体的每一端从而促进向周围空气的热传送。每片薄片互相间隔以防止不要与相同行的引线交错。第一和第二薄片沿着载体的中心互相隔开。每个IC封装包括介电个体、嵌入在个体中的IC芯片、以及多根引线，引线的末端同样嵌入在个体内并与IC芯片上的连接终端导电地连接。对于多重芯片模块的较佳实施例，下IC封装个体的上表面与两片薄片紧密接触，或通过热导复合物与它热耦连，或与它非常接近以促进从封装个体到薄片的热传送。
载体的第二实施例包括改进过的引线，每根引线都作为散热片起作用。每根引线的中心位置与载体个体下表面上第二压片阵列的压片键合。对每根引线的外面部分成形以用于表面安装到PCB上的安装/连接压片。每根引线的里面部分向个体的中心延伸。对于多芯片模块的较佳实施例，下IC封装个体的上表面与每根引线的里面部分紧密接触，或通过热导复合物与它热耦连，或与它非常接近以促进从封装个体到引线的热传送。
根据本发明，提供一种电子模块，包括第一印刷电路板和第二印刷电路板。该第一印刷电路板包括：多根引线；第一安装压片阵列；和第一集成电路封装，具有多个耦连到所述第一安装压片阵列的连接元件。该第二印刷电路板包括：多个连接元件；第二安装压片阵列；第二集成电路电路封装，具有多个耦连到所述第二安装压片阵列的连接元件；和第三安装压片阵列，其中，通过将所述多根引线电连接到所述第三安装压片阵列将所述第一印刷电路板耦连到所述第二印刷电路板，且所述第一印刷电路板位于所述第二集成电路封装顶部的上方。
附图说明
图1是显示第一实施例封装载体顶部的等轴图；
图2是第一实施例封装载体个体显示其下侧的等轴图；
图3是图1封装载体的载体引线的等轴图；
图4是与地引线和电源引线连接的第一和第二散热片的等轴图；
图5是联系第一和第二集成电路封装，显示第一实施例电子模块分解部分的等轴图；
图6是第一实施例电子模块装配部分的等轴图；
图7第二实施例封装载体的等轴图；
图8是第二实施例封装载体个体显示其下侧的等轴图；
图9是图7封装载体的载体引线的等轴图；
图10是第一或第二实施例封装载体的载体个体的俯视平面图；
图11是第二实施例电子模块分解部分的等轴图；以及
图12是第二实施例电子模块装配部分的等轴图。
具体实施方式
从附图可明显地看出，本发明允许制造电路密集度增加的电子模块。本发明可用于多种场合。一种非常明显的用途是存储模块的制造。由于存储模块通常结合有尺寸严格规定的印刷电路板，所以电路板实际面积的更加有效使用将导致具有总存储容量的加大模块。也可利用本发明紧密地连接相关但不相同的IC封装。比如，可以希望在含微处理器芯片的IC封装的顶部安装含高速缓冲存储器的IC封装。现将参考附图对改进后电子模块的不同实施例进行详细描述。
现在参考图1和图2，第一实施例的封装载体100具有介电体101，该介电体具有上平行主平面102U和下平行主平面102L。对于本发明的较佳实施例，介电体是由通常用于制造印刷电路板的纤维玻璃强化的塑料材料制成。介电体101也具有固定于于所述上主平面102U的第一安装压片阵列103。阵列103的多个安装压片104是单独成形共同排列以接收第一集成电路封装的多根引线(该图中未显示)。介电体101还包括固定于所述下主平面102L的第二安装压片阵列105。第二阵列105的每一压片106都通过内部电镀孔与所述的第一阵列103的片104耦连，该电镀孔在上主平面102U和下主平面102L之间延伸。封装载体100还包括一系列载体引线108，每根引线导电地与第二安装压片阵列105的压片106键合。载体引线系列108的单根引线108A被互相隔开并设置，用于在印刷电路板(在该图中未显示)上表面安装。需指出的是，个体101在其每一端都有被挖空的部分109。同样需要指出的是，对于这个载体的实施例，第一阵列103两行压片104当中的间隔要窄于第二阵列两行压片105当中的间隔。这个间隔上不同的原因是，封装载体100可被认为是覆盖并跨接安装在印刷电路板上的第二集成电路封装的覆盖层。因此，载体引线108必须是较宽的间隔以便于它们安装在这样覆盖的封装的引线的外面。封装载体100还包括在其每端上的一对电容安装压片110。设置每对压片的尺寸和间隔以接收表面安装去耦合电容器111。
现在参考图3，第一实施例封装载体100的载体引线系列108包括多根铰接引线301，每根都各自与第二安装压片阵列105的压片106相连。每根引线301的外面部分基本上是C形的。载体引线系列108还包括三根一组的电源引线302，它们通过第一薄片303互相连接，也起到散热层的作用。同样包括在载体引线系列108中的是三根一组的地引线304，它们通过第二薄片305互相连接，也起到散热层的作用。第一和第二薄片303和305分别包括了一对延伸片306，它提高了从薄片的散热。被挖孔的部分109裸露了第一和第二薄片103和105部分，从而有助于向周围空气的散热。
图4显示了去掉铰接引线301的载体引线系列108。三根电源引线302和相关的互连散热层303在左边，而三根地引线304和相关的互连散热层305在右边。延伸片306同样容易看见。
现在参考图5中电子模块500的分解图，示出的具有多根引线502的第一集成电路封装501正对准用以表面安装至第一实施例封装载体100的上主平面102U上的第一安装压片阵列103。印刷电路板503包括第三安装压片阵列504，该阵列具有以两平行行506L和506R排列的单个安装压片505。示出的具有多根引线508的第二集成电路封装507正对准用以表面安装至第三安装压片阵列504。封装载体100同样对准用以表面安装至第三安装压片阵列。设计封装载体100从而使它的组成其载体引线系列108的两行引线108L和108R相隔的距离比第二集成电路封装507上的引线行508更宽。这样的配置允许一根载体引线108和第二根封装引线508共享印刷电路板503上的共有安装压片505。在信号和/或电源输入是共有的情况下，压片505不需要被分离。但是，当信号不同时(比如，芯片选择信号)，则可分离片505从而可以向适当的引线传送不同的信号或电源要求。片505S就是这样的分离片。如果第一和第二封装501和507分别是存储芯片，第一封装501表面安装至载体100，载体100和第二封装表面安装至印刷电路板503，则可通过向适当的半片505S发送信号来单独地选择每个芯片。一种将芯片选择信号传递给两个等效芯片的可替换方法包含利用不使用的引线片(在每个封装上通常有几个)作为一个芯片选择信号并随后在载体的介电体101中重新将信号传递给将与芯片选择引线键合的压片。需要指出的是，印刷电路板包括一对在第三安装压片阵列504对角上的电容安装压片509。设置每对片的尺寸和间隔以接收表面安装去耦合电容器111。去耦合电容器的固定通常不是关键问题，而电容器可早点安装在载体101的同侧上。另外，对于每个芯片可使用超过两个的电容器。很显然，对于一对等效的存储芯片，所有的连接，而不只是芯片选择输入，都将被垂直地叠加。在这样的情况下，将使用内部电镀孔107以便将第一安装压片阵列103的压片104与第二安装压片阵列105的垂直对准的压片106互相连接。当使用不相同的第一和第二集成电路封装时，连接的重新布线是必须的。这可以和用于印刷电路板设计相同的方式来完成。因此，在分别位于载体介电体101上表面102U和下表面102L的第一和第二安装压片阵列之间，在介电材料的个体101中嵌入了一个或更多交错层轨迹。交错层也可与内部电镀孔互相连接。该技术是这样普通，以致在本说明书中不太需要讨论。
参考图6，第二集成电路封装507表面安装至印刷电路板503上的第三安装压片阵列504，第一实施例的封装载体100也表面安装至第三安装压片阵列504，而第一集成电路封装501表面安装至封装载体100的第一安装压片阵列103。装配还包括四个去耦合电容器111，它们被表面安装至载体100上的电容器安装压片110以及印刷电路板503上的电容器安装压片509。
图7、图8和图9显示了以装配形式(图7)和元件形式(图8和图9)的第二实施例封装载体700。第一实施例载体100和第二实施例载体700之间的主要区别是引线701的形状。将指出的是，每根引线都具有起到散热片作用的拉长部分。没有薄片如第一实施例载体100那样与电源引线或地引线耦合。图8显示了介电载体体101的下侧，在该情况下，与第一实施例载体100的等效。
现在参考图10，第一或第二芯片载体700的俯视图示出了用于去耦合电容器安装压片110和509的布线轨迹的一种结构。轨迹1001将压片110A/509A与第一安装压片阵列103的电源安装压片104P耦连，而轨迹1002将片110B与第一安装压片阵列103的地安装压片104G耦连。同样，轨迹1003将压片110C与第一安装压片阵列103的地安装压片104G耦连，而轨迹1004将压片110D/509D与第一安装压片阵列103的电源安装压片104P耦连。
现在参考图11的分解部分，示出的具有多根引线502的第一集成电路封装501正对准用以表面安装至第二实施例封装载体700的上主平面102U上的第一安装压片阵列103。印刷电路板503包括第三安装压片阵列504，该阵列具有以两平行行506L和506R排列的单个安装压片505。示出的具有多根引线508的第二集成电路封装507的排列，用于表面安装至第三安装压片阵列504。第二实施例封装载体700的排列也是用于表面安装至第三安装压片阵列。
现在参考图12，第二集成电路封装507被表面安装至印刷电路板503的第三安装压片阵列504，第二实施例的封装载体700也被表面安装至第三安装压片阵列504，而第一集成电路封装501则被表面安装至封装载体100的第一安装压片阵列103。装配还包括安装至电容器安装压片110和509的四个去耦合电容器111。
虽然上文中只描述了本发明的几个单独的实施例，但对于本技术领域中那些具有一般技术的人士来说，在不脱离由下文中权利要求所定义的本发明的范围和精神的前提下仍可以作出变化和修改。比如，可以对两个基本的实施例作许多变化。例如，可改变表面安装IC封装的引线。另外，载体引线外面部分的形状也可从文中披露的“C”形变化。在当今，通常有两类引线广泛用于表面安装元件。一类引线是“J”形的；另一类是“S”形的。“S”形或鸥翼形的引线变得越来越广泛。其它类型用于表面安装元件的引线也可发展。本发明不应该被认为受到在任何组成元件或芯片载体101上使用的引线类型的限制。也可在组成模块的元件之间组合引线类型。因此，可以有包含几种不同引线组合的装配。在光谱的一端，封装和载体都可以使用“C”形或“J”形的引线。在另一端，所有的元件都使用“S”形的引线。在这两个极端之间，每个元件都可使用现今用于表面安装元件的三种引线中的任一种以及可能发展的引线。另外，元件的表面安装通常包含焊接回流处理，其中引线和/或安装压片用焊料乳胶涂层。随后装配元件，装配在炉子中经过回流步骤完成。引线因此导电地与安装压片键合。用于将引线与安装压片连接还有其它知名的技术。在每个安装压片上放置金属球(通常为金球)，在每个球的顶部设置引线，并使用超声波能量将每个球与其相关的压片和引线熔合是另一种表面安装的选择。

Claims (19)

1.一种电子模块，包括：
第一印刷电路板，包括：
多个导电部件；
第一安装压片阵列；和
第二安装压片阵列，其中所述第二安装压片阵列导电地耦连于所述第一安装压片阵列，并且所述第二安装压片阵列还导电地耦连于所述多个导电部件；
第二印刷电路板，包括第三安装压片阵列，其中通过导电地将所述多个导电部件耦连于所述第三安装压片阵列，将所述第一印刷电路板耦连到所述第二印刷电路板；
第一集成电路封装，具有多个耦连到所述第一安装压片阵列的连接元件；和
第二集成电路封装，具有多个耦连到所述第三安装压片阵列的连接元件，并夹在所述第一印刷电路板和所述第二印刷电路板之间。
2.如权利要求1所述的电子模块，其特征在于，所述第一和第二集成电路封装连接元件包括引线。
3.如权利要求1所述的电子模块，其特征在于，所述多个导电部件包括多根引线。
4.如权利要求3所述的电子模块，其特征在于，所述多根引线选自由鸥翼形引线、铰接引线、“S”形引线、“C”形引线和“J”形引线构成的组。
5.如权利要求1所述的电子模块，其特征在于，所述电子模块还包括散热片。
6.如权利要求1所述的电子模块，其特征在于，所述第一印刷电路板包括一个热沉。
7.如权利要求1所述的电子模块，其特征在于，所述多个导电部件中只有两个导电部件适于在第一集成电路封装的操作中位于地电势或电源电压电势。
8.如权利要求1所述的电子模块，其特征在于，所述第一印刷电路板还包括至少一对电容器安装压片，设置每对压片的尺寸和间隔以接收去耦合电容器。
9.如权利要求8所述的电子模块，其特征在于，所述电子模块还包括与所述第一印刷电路板耦连的去耦合电容器。
10.如权利要求1所述的电子模块，其特征在于，所述第二印刷电路板还包括至少一对电容器安装压片，设置每对压片的尺寸和间隔以接收去耦合电容器。
11.如权利要求10所述的电子模块，其特征在于，所述电子模块还包括与所述第二印刷电路板耦连的去耦合电容器。
12.如权利要求1所述的电子模块，其特征在于，所述第二集成电路封装的顶表面和所述第一印刷电路板的底表面互相接触。
13.如权利要求1所述的电子模块，其特征在于，所述第一印刷电路板由纤维玻璃强化的塑料材料形成。
14.如权利要求1所述的电子模块，其特征在于，所述第二印刷电路板由纤维玻璃强化的塑料材料形成。
15.如权利要求1所述的电子模块，其特征在于，所述多个导电部件中的每一个耦连于所述第一印刷电路板的底表面。
16.如权利要求1所述的电子模块，其特征在于，所述第一和第二印刷电路板具有矩形的形状。
17.如权利要求1所述的电子模块，其特征在于，所述第一和第二印刷电路板具有正方形的形状。
18.如权利要求16所述的电子模块，其特征在于，所述多个导电部件耦连于所述第一印刷电路板的两侧。
19.如权利要求16所述的电子模块，其特征在于，所述多个导电部件耦连于所述第二印刷电路板的两侧。
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WO2001069680A3 (en) 2002-03-21
WO2001069680A2 (en) 2001-09-20
EP1264347B1 (en) 2006-10-11
DE60123762D1 (de) 2006-11-23
CN1428006A (zh) 2003-07-02
US20020181216A1 (en) 2002-12-05
HK1055015A1 (en) 2003-12-19
US6900529B2 (en) 2005-05-31
AU2001249169A1 (en) 2001-09-24
CN1941361A (zh) 2007-04-04
CN1282244C (zh) 2006-10-25
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US6487078B2 (en) 2002-11-26

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