CN100481283C - Inductive element and symmetric inductive component - Google Patents
Inductive element and symmetric inductive component Download PDFInfo
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- CN100481283C CN100481283C CNB2006100994258A CN200610099425A CN100481283C CN 100481283 C CN100481283 C CN 100481283C CN B2006100994258 A CNB2006100994258 A CN B2006100994258A CN 200610099425 A CN200610099425 A CN 200610099425A CN 100481283 C CN100481283 C CN 100481283C
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Abstract
The invention supplies an inductance component and a symmetric inductance component. It includes the first, the second, the third and the forth half-coil conducting wire layers in the insulating layer of the base. The second half-coil conducting wire layer is symmetric with the fist one. The third half-coil conducting wire layer is parallel with the first one and out of it. The fourth half-coil conducting wire layer is symmetric with the third one. Every half-coil conducting wire layer has the first and the second end. The first ends of the first and the second half-coil conducting wire layer are connected. The second ends of the second and the third half-coil conducting wire layer are connected. The second ends of the first and the fourth half-coil conducting wire layer are connected. These half-coil conducting wire layers have the same wire width and the same wire distance and when the wire width is below 6 micron, the wire distance exceeds the wire width. The invention decreases the parasitic capacitance effect in the symmetric inductance component of the differential wave operation to maintain the frequency span of the inductance component.
Description
Technical field
The present invention particularly operates the symmetrical inductance element of (differential operation) relevant for a kind of semiconductor device relevant for a kind of differential-type.
Background technology
Many numerals and analog component and circuit successfully apply to semiconductor integrated circuit.Above-mentioned parts have comprised passive device, for example resistance, electric capacity or inductance etc.Typical semiconductor integrated circuit comprises a silicon base.The above dielectric layer of one deck is arranged in the substrate, and the above metal level of one deck is arranged in the dielectric layer.These metal levels can form the built-in parts of wafer, for example wafer built-in inductor element (on-chip inductor) by existing manufacture of semiconductor technology.
Traditionally, the wafer built-in inductor is formed in the substrate and applies to radio frequency band (radio frequency band) integrated circuit (IC) design.Please refer to Fig. 1, wherein Fig. 1 shows a known wafer built-in inductor element floor map with snail structure.Wafer built-in inductor element is formed in the insulating barrier 104 of a substrate 100 tops, and it comprises a spiral metal layer 103 and an internal connection-wire structure.Spiral metal layer 103 is embedded in the insulating barrier 104.Internal connection-wire structure comprise the conductive plunger 105 that embeds in the layer insulating (not illustrating) down and 109 and metal level 107 be embedded in the insulating barrier 104 metal level 111 spiral metal layers 103 by conductive plunger 105 and 109 and metal level 107 and 111 form a current path, to electrically connect with wafer outside or internal circuit.
The advantage of plane helical inductance element is and can be positioned at the integrated level that circuit element quantity that wafer builds and required complicated intraconnections thereof increase circuit outward by minimizing.Moreover the plane spiral inductance can avoid wafer built in channel and wafer to build the ghost effect that joint sheet between (off-chip) circuit (bond pad) or wiring (bond wire) are produced outward.
Yet the quality factor of above-mentioned plane spiral inductance (quality factor/Qvalue) are low and area is big.For the Q value of further improving inductance and reduce area, the someone proposes the inner ring that increases the thickness of spiral metal layer 103 and dwindle spiral metal layer 103 and the line-spacing S1 between the outer ring.In addition, also the someone proposes the double-layer spiral induction structure.Generally speaking, under identical inductance, the shared chip area of double-layer spiral inductance is 1/2 to 1/4 of the shared chip area of plane spiral inductance.Moreover the required coil of double-layer spiral inductance also is less than the plane spiral inductance, increases the Q value so can further reduce impedance.
Though the double-layer spiral inductance has less impedance and preferable Q value, but increasing wireless telecommunications design uses differential circuit reducing common mode (common mode) noise, and the inductance that applies to above-mentioned differential circuit is required to be symmetrical expression and prevents that common-mode noise from producing.That is inductance is watched from arbitrary end points all has same structure.Plane spiral inductance among Fig. 1 or double-layer spiral inductance are not to be symmetrical expression, if be applied to then effective noise insulation of differential circuit.
Summary of the invention
In view of this, the invention provides a kind of symmetrical inductance element, it is by the live width of coil (coil) and the relation of line-spacing in the change inductance, to improve the inductance quality factor.
According to above-mentioned purpose, the invention provides a kind of symmetrical inductance element, it comprises: an insulating barrier and the first, second, third and the 4th half-turn shape conductor layer.Insulating barrier is arranged in the substrate.The first half-turn shape conductor layer is arranged in the insulating barrier, and it has one first end and one second end.The second half-turn shape conductor layer is arranged in the insulating barrier and is symmetrical in the first half-turn shape conductor layer, and it has one first end and one second end, and first end of first end of the second half-turn shape conductor layer and the first half-turn shape conductor layer electrically connects.The 3rd half-turn shape conductor layer is arranged in the insulating barrier, and it has one first end and one second end outside being parallel to the first half-turn shape conductor layer and being positioned at it, and second end of second end of the 3rd half-turn shape conductor layer and the second half-turn shape conductor layer electrically connects.The 4th half-turn shape conductor layer is arranged in the insulating barrier, is symmetrical in the 3rd half-turn shape conductor layer, and it has second end of one first end and one second end the 4th half-turn shape conductor layer and second end of the first half-turn shape conductor layer electrically connects.These half-turn shape conductor layers have identical live width and identical line-spacing, and when live width during less than 6 microns, line-spacing is greater than live width, and when this live width was roughly 6 microns, this line-spacing was same as this live width substantially, and when this live width during greater than 6 microns, this line-spacing is less than this live width.
Symmetrical inductance element of the present invention, wherein when this live width was not more than 9 microns, this live width and this line-spacing relation were as follows: S=[-W/6+2] * W; Wherein S is a line-spacing, and W is a live width.
Symmetrical inductance element of the present invention, wherein when this live width was not less than 9 microns, this live width and this line-spacing relation were as follows: S=0.5W; Wherein S is a line-spacing, and W is a live width.
Symmetrical inductance element of the present invention, wherein these first and second half-turn shape conductor layers are to constitute to be roughly circular or polygonal profile.
Symmetrical inductance element of the present invention, wherein this polygon comprises rectangle, hexagon and octagon.
According to above-mentioned purpose, the invention provides a kind of inductance element again, be disposed in the insulating barrier of semiconductor wafer, comprising: the first, second, third and the 4th half-turn shape conductor layer.The first half-turn shape conductor layer has one first end and one second end.The second half-turn shape conductor layer is symmetrical in the first half-turn shape conductor layer, has one first end and one second end, and first end of first end of the second half-turn shape conductor layer and the first half-turn shape conductor layer electrically connects.The 3rd half-turn shape conductor layer is parallel to the first half-turn shape conductor layer and is positioned at its outside, have one first end and one second end, and second end of second end of the 3rd half-turn shape conductor layer and the second half-turn shape conductor layer electrically connects.The 4th half-turn shape conductor layer is symmetrical in the 3rd half-turn shape conductor layer, has one first end and one second end, and second end of second end of the 4th half-turn shape conductor layer and the first half-turn shape conductor layer electrically connects.First and second half-turn shape conductor layer has identical live width, and this live width is different from another live width that the 3rd half-turn shape conductor layer and the 4th half-turn shape conductor layer have, and the line-spacing between this first half-turn shape conductor layer and the 3rd half-turn shape conductor layer is same as the line-spacing between this second half-turn shape conductor layer and the 4th half-turn shape conductor layer, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer during less than 6 microns, line-spacing between this first half-turn shape conductor layer and the 3rd half-turn shape conductor layer is greater than this live width, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer is roughly 6 microns, this line-spacing is same as this live width substantially, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer during greater than 6 microns, this line-spacing is less than this live width.
Inductance element of the present invention, wherein when this live width was not more than 9 microns, this live width and this line-spacing relation were as follows: S=[-W/6+2] * W; Wherein S is a line-spacing, and W is a live width.
Inductance element of the present invention, wherein when this live width was not less than 9 microns, this live width and this line-spacing relation were as follows: S=0.5W; Wherein S is a line-spacing, and W is a live width.
Inductance element of the present invention and symmetrical inductance element can be by the particular kind of relationships of live width and line-spacing, make that the parasitic capacitance effect in the symmetrical inductance element of differential wave operation reduces, to keep inductance element available frequencies scope.
Description of drawings
Fig. 1 shows known wafer built-in inductor element floor map with snail structure.
Fig. 2 shows two a circles symmetry inductance element floor map according to the embodiment of the invention.
Fig. 3 shows three a circles symmetry inductance element floor map according to the embodiment of the invention.
Fig. 4 shows four a circles symmetry inductance element floor map according to the embodiment of the invention.
Embodiment
Below cooperate Fig. 2 that the floor map of the symmetrical inductance element of the embodiment of the invention is described.The symmetry inductance element is configurable in an insulating barrier 210 of semiconductor wafer (not illustrating), comprising: the first, second, third and the 4th half-turn shape conductor layer 201,202,203 and 204.Insulating barrier 210 is arranged in the substrate 200.Substrate 200 comprises a silicon base or other known semiconductor substrates.Can comprise various element in the substrate 200, for example transistor, resistance and other semiconductor elements commonly used.Moreover substrate 200 also can comprise other conductive layers (for example, copper, aluminium or its alloy) and insulating barrier (for example, silicon oxide layer, silicon nitride layer or low dielectric material layer).For simplicity of illustration, only represent with a smooth substrate herein.In addition, insulating barrier 210 can be an individual layer low dielectric material layer or a multilayered dielectric structure.In the present embodiment, insulating barrier 210 can comprise silicon oxide layer, silicon nitride layer or low dielectric material layer.
The first half-turn shape conductor layer 201 is arranged in the insulating barrier 210, and is positioned at one first side of dotted line 2.The second half-turn shape conductor layer 202 is arranged in the insulating barrier 210, and is positioned at second side with respect to first side of dotted line 2, and wherein the second half-turn shape conductor layer 202 is that symmetry axis is symmetrical in the first half-turn shape conductor layer 201 with dotted line 2.First and second half-turn shape conductor layer 201 and 202 can constitute and is roughly circle, rectangle, hexagon, octagon or polygonal profile., being simplicity of illustration herein, is to illustrate as example with octagon.Moreover first and second half-turn shape conductor layer 201 and 202 material can comprise copper, aluminium or its alloy.In the present embodiment, first and second half-turn shape conductor layer 201 and 202 has identical live width W.Moreover first and second half-turn shape conductor layer 201 and 202 respectively has one first end 10 and one second end 20, wherein first end 10 of the second half-turn shape conductor layer 202 first end 10 that extends to the first half-turn shape conductor layer 201 with its electric connection.
The 3rd half-turn shape conductor layer 203 is arranged in the insulating barrier 210, and is positioned at first side of dotted line 2.Moreover the 3rd half-turn shape conductor layer 203 is parallel to the first half-turn shape conductor layer 201 and is positioned at its outside.The 4th half-turn shape conductor layer 204 is arranged in the insulating barrier 210, and be positioned at second side of dotted line 2, wherein the 4th half-turn shape conductor layer 204 is that symmetry axis is symmetrical in the 3rd half-turn shape conductor layer 203 with dotted line 2, make the 4th half-turn shape conductor layer 204 be parallel to the second half-turn shape conductor layer 202 and be positioned at its outside.The the 3rd and the 4th half-turn shape conductor layer 203 and 204 formations are roughly octagonal profile.Moreover the 3rd and the 4th half-turn shape conductor layer 203 and 204 material can be same as first and second half-turn shape conductor layer 201 and 202.
In the present embodiment, the 3rd and the 4th half-turn shape conductor layer 203 and 204 has identical live width W, and the line-spacing S between the 3rd and first half-turn shape conductor layer 203 and 201 is same as the line-spacing between the 4th and second half-turn shape conductor layer 204 and 202.In other present embodiments, the 3rd and the 4th half-turn shape conductor layer 203 and 204 has identical live width and is different from the live width W of first and second half-turn shape conductor layer 201 and 202.Moreover the 3rd and the 4th half-turn shape conductor layer 203 and 204 respectively has one first end 10 and one second end 20.In the present embodiment, for second end 20 of keeping inductance element geometrical symmetry (geometric symmetry) the 3rd half-turn shape conductor layer 203 by second end, 20 electric connections of cross-over connection layer (cross-connect) 211 once with the second half-turn shape conductor layer 202.The two ends of following cross-over connection layer 211 are respectively arranged with a conductive plunger (not illustrating) with second end 20 that is electrically connected to the 3rd half-turn shape conductor layer 203 respectively and second end 20 of the second half-turn shape conductor layer.In addition, second end 20 of the 4th half-turn shape conductor layer 204 electrically connects with second end 20 of the first half-turn shape conductor layer 201 by cross-over connection layer 213 on.In other embodiments, second end 20 of the 3rd half-turn shape conductor layer 203 can electrically connect by second end 20 of cross-over connection layer on the second half-turn shape conductor layer 202, and second end 20 of the 4th half-turn shape conductor layer 204 can be by cross-over connection layer once and with second end, 20 electric connections of the first half-turn shape conductor layer 201.The the 3rd and the 4th half-turn shape conductor layer 203 and 204 first end 10 have the portion of extending laterally 30 and 40, in order to input differential wave (not illustrating).That is, identical and have a signal that 180 degree differ in extension 30 and 40 input sizes.
Generally speaking, because adjacent metal wire winding layer (winding) can be by the signal of same phase, so the parasitic capacitance effect between the adjacent metal wire winding layer (parasitic capacitance effect) is lower in the inductance element of single-ended signal operation (single-ended signaloperation).Therefore, the line-spacing between the metal wire winding layer must dwindle as much as possible, to improve the usefulness of inductance element.Among design at present, in order to reach the highest inductance value, the designer can be according to the minimum line that is allowed in manufacture of semiconductor adjacent metal winding structure in the inductance element that designs the single-ended signal operation under the same implant space of lines.
Yet, the inductance element that is different from single-ended signal operation (single-ended signaloperation), wire winding layer adjacent in the inductance element of differential wave operation can be spent the signal that differs by having 180, so the parasitic capacitance effect between the adjacent metal wire winding layer increases because of the signal that is carried differs.In other words, under identical line-spacing design, mean between these adjacent in the inductance element of differential wave operation metal wire winding layers to have bigger parasitic capacitance.When parasitic capacitance increased, peak value quality factor frequency (peak Q-factor frequency) can descend and increase inductance deviation (inductance value deviation), thereby has limited inductance element available frequencies scope.Therefore, in the present embodiment, half-turn shape conductor layer live width W and line-spacing S have specific relation in the symmetrical inductance element.For example, as live width W during less than 6 microns (μ m), line-spacing S is greater than live width W.Moreover when live width W was roughly 6 microns (μ m), line-spacing S was same as live width W substantially.Again, when live width during greater than 6 microns, line-spacing S is less than live width W, to avoid significantly increasing the area of inductance element.Especially, when live width W was not more than 9 microns (μ m), live width W and line-spacing S relation were as follows:
S＝[-W/6+2]×W
In addition, in the present embodiment, when live width W was not less than 9 microns (μ m), live width W and line-spacing S relation were as follows:
S＝0.5W
According to symmetrical inductance element of the present invention, can be by the particular kind of relationship of live width W and line-spacing S, make parasitic capacitance effect reduction in the symmetrical inductance element of differential wave operation, to keep inductance element available frequencies scope.
Below cooperate Fig. 3 and Fig. 4 that the symmetrical inductance element of other embodiments of the invention is described, wherein Fig. 3 shows three circles symmetry inductance element floor map, and Fig. 4 shows four circles symmetry inductance element floor map.Moreover the parts that are same as among Fig. 2 are to use identical label and omit its explanation.In Fig. 3, symmetrical inductance element further comprises the 5th and the 6th half-turn shape conductor layer 205 and 206.The 5th half-turn shape conductor layer 205 is arranged in the insulating barrier 210, and it is parallel to the 3rd half-turn shape conductor layer 203 and is positioned at its outside.The 6th half-turn shape conductor layer 206 is arranged in the insulating barrier 210, and it is symmetrical in the 5th half-turn shape conductor layer 205, make the 6th half-turn shape conductor layer 206 be parallel to the 4th half-turn shape conductor layer 204 and be positioned at its outside.Similarly, the 5th and the 6th half-turn shape conductor layer 205 and 206 has identical live width W and identical line-spacing S.In other embodiments, the 5th and the 6th half-turn shape conductor layer 205 and 206 has identical live width and is different from the live width W of first and second half-turn shape conductor layer 201 and 202.Moreover the 5th and the 6th half-turn shape conductor layer 205 and 206 respectively has one first end 10 and one second end 20.First end 10 of the 5th half-turn shape conductor layer 205 can be by first end, 10 electric connections of cross-over connection layer 217 and the 4th half-turn shape conductor layer 204 once.In addition, first end 10 of the 6th half-turn shape conductor layer 206 can electrically connect with first end 10 of the 3rd half-turn shape conductor layer 203 by cross-over connection layer 215 on.The the 5th and the 6th half-turn shape conductor layer 205 and 206 second end 20 have the portion of extending laterally 30 and 40, in order to input differential wave (not illustrating).In the present embodiment, half-turn shape conductor layer live width W and line-spacing S have above-mentioned relation in the symmetrical inductance element.Moreover the symmetrical inductance element of other odd number circles has the structure that is similar to inductance element among Fig. 3.
In Fig. 4, symmetrical inductance element further comprises the 7th and the 8th half-turn shape conductor layer 207 and 208.The 7th half-turn shape conductor layer 207 is parallel to the 5th half-turn shape conductor layer 205 and is positioned at its outside.The 8th half-turn shape conductor layer 208 is symmetrical in the 7th half-turn shape conductor layer 207.Similarly, the 7th and the 8th half-turn shape conductor layer 207 and 208 has identical live width W and identical line-spacing S.Moreover the 7th and the 8th half-turn shape conductor layer 207 and 208 respectively has one first end 10 and one second end 20.Second end 20 of the 7th half-turn shape conductor layer 207 can be by second end, 20 electric connections of cross-over connection layer 221 and the 6th half-turn shape conductor layer 206 once.In addition, second end 20 of the 8th half-turn shape conductor layer 208 can electrically connect with second end 20 of the 5th half-turn shape conductor layer 205 by cross-over connection layer 219 on.The the 7th and the 8th half-turn shape conductor layer 207 and 208 first end 10 have the portion of extending laterally 30 and 40, in order to input differential wave (not illustrating).In the present embodiment, half-turn shape conductor layer live width W and line-spacing S have above-mentioned relation in the symmetrical inductance element.Moreover the symmetrical inductance element of other even number circles has the structure that is similar to inductance element among Fig. 4.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: substrate
103: the spiral metal layer
104: insulating barrier
105,109: conductive plunger
107,111: metal level
S1: line-spacing
2: dotted line
10: the first ends
20: the second ends
30,40: extend laterally portion
200: substrate
201: the first half-turn shape conductor layers
202: the second half-turn shape conductor layers
203: the three half-turn shape conductor layers
204: the four half-turn shape conductor layers
205: the five half-turn shape conductor layers
206: the six half-turn shape conductor layers
207: the seven half-turn shape conductor layers
208: the eight half-turn shape conductor layers
210: insulating barrier
211,217,221: following cross-over connection layer
213,215,219: go up the cross-over connection layer
S: line-spacing
W: live width
Claims (8)
1. a symmetrical inductance element is characterized in that, described symmetrical inductance element comprises:
One insulating barrier is arranged in the substrate;
One first half-turn shape conductor layer is arranged in this insulating barrier, and it has one first end and one second end;
One second half-turn shape conductor layer is arranged in this insulating barrier and is symmetrical in this first half-turn shape conductor layer, and it has one first end and one second end, this first end electric connection of this first end of this second half-turn shape conductor layer and this first half-turn shape conductor layer;
One the 3rd half-turn shape conductor layer, be arranged in this insulating barrier, be parallel to this first half-turn shape conductor layer and be positioned at its outside, it has one first end and one second end, and this second end of this second end of the 3rd half-turn shape conductor layer and this second half-turn shape conductor layer electrically connects; And
One the 4th half-turn shape conductor layer is arranged in this insulating barrier, is symmetrical in the 3rd half-turn shape conductor layer, and it has one first end and one second end, and this second end of this second end of the 4th half-turn shape conductor layer and this first half-turn shape conductor layer electrically connects;
Wherein the first half-turn shape conductor layer, the second half-turn shape conductor layer, the 3rd half-turn shape conductor layer and the 4th half-turn shape conductor layer have identical live width and identical line-spacing, and when this live width during less than 6 microns, this line-spacing is greater than this live width, when this live width is 6 microns, this line-spacing is same as this live width, when this live width during greater than 6 microns, this line-spacing is less than this live width.
2. symmetrical inductance element according to claim 1 is characterized in that, when this live width was not more than 9 microns, this live width and this line-spacing relation were as follows:
S＝[-W/6+2]×W，
Wherein S is a line-spacing, and W is a live width.
3. symmetrical inductance element according to claim 1 is characterized in that, when this live width was not less than 9 microns, this live width and this line-spacing relation were as follows:
S＝0.5W，
Wherein S is a line-spacing, and W is a live width.
4. symmetrical inductance element according to claim 1 is characterized in that, this first half-turn shape conductor layer and the second half-turn shape conductor layer are to constitute circular or polygonal profile.
5. symmetrical inductance element according to claim 4 is characterized in that this polygon comprises rectangle, hexagon and octagon.
6. an inductance element is disposed in the insulating barrier of semiconductor wafer, it is characterized in that described inductance element comprises:
One first half-turn shape conductor layer, it has one first end and one second end;
One second half-turn shape conductor layer is symmetrical in this first half-turn shape conductor layer, and it has one first end and one second end, and this first end of this first end of this second half-turn shape conductor layer and this first half-turn shape conductor layer electrically connects;
One the 3rd half-turn shape conductor layer is parallel to this first half-turn shape conductor layer and is positioned at its outside, and it has one first end and one second end, and this second end of this second end of the 3rd half-turn shape conductor layer and this second half-turn shape conductor layer electrically connects; And
One the 4th half-turn shape conductor layer is symmetrical in the 3rd half-turn shape conductor layer, and it has one first end and one second end, and this second end of this second end of the 4th half-turn shape conductor layer and this first half-turn shape conductor layer electrically connects;
Wherein this first half-turn shape conductor layer and this second half-turn shape conductor layer have identical live width, and this live width is different from another live width that the 3rd half-turn shape conductor layer and the 4th half-turn shape conductor layer have, and the line-spacing between this first half-turn shape conductor layer and the 3rd half-turn shape conductor layer is same as the line-spacing between this second half-turn shape conductor layer and the 4th half-turn shape conductor layer, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer during less than 6 microns, line-spacing between this first half-turn shape conductor layer and the 3rd half-turn shape conductor layer is greater than this live width, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer is 6 microns, this line-spacing is same as this live width, when this live width of this first half-turn shape conductor layer and this second half-turn shape conductor layer during greater than 6 microns, this line-spacing is less than this live width.
7. inductance element according to claim 6 is characterized in that, when this live width was not more than 9 microns, this live width and this line-spacing relation were as follows:
S＝[-W/6+2]×W，
Wherein S is a line-spacing, and W is a live width.
8. inductance element according to claim 6 is characterized in that, when this live width was not less than 9 microns, this live width and this line-spacing relation were as follows:
S＝0.5W，
Wherein S is a line-spacing, and W is a live width.
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| CNB2006100994258A CN100481283C (en) | 2006-07-18 | 2006-07-18 | Inductive element and symmetric inductive component |
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| CN100481283C true CN100481283C (en) | 2009-04-22 |
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| CN100511640C (en) * | 2007-03-21 | 2009-07-08 | 威盛电子股份有限公司 | Screw inductive element having multiplex conductor structure |
| TWI345243B (en) | 2007-08-14 | 2011-07-11 | Ind Tech Res Inst | Inter-helix inductor devices |
| CN101145435B (en) * | 2007-08-23 | 2010-08-25 | 威盛电子股份有限公司 | Inductance structure |
| CN101206950B (en) * | 2007-11-14 | 2010-08-25 | 威盛电子股份有限公司 | Inductance structure |
| TWI514547B (en) * | 2013-01-30 | 2015-12-21 | Via Tech Inc | Semiconductor device |
| CN103400820B (en) * | 2013-01-30 | 2016-08-10 | 威盛电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| TWI757073B (en) * | 2021-01-28 | 2022-03-01 | 威鋒電子股份有限公司 | Multilayer-type on-chip inductor structure |
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| CN1405801A (en) * | 2002-10-30 | 2003-03-26 | 威盛电子股份有限公司 | Multilayer balanced inductor |
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| CN1649042A (en) * | 2004-01-30 | 2005-08-03 | 联华电子股份有限公司 | Symmetrical type inductance |
| US6972658B1 (en) * | 2003-11-10 | 2005-12-06 | Rf Micro Devices, Inc. | Differential inductor design for high self-resonance frequency |
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| CN1405801A (en) * | 2002-10-30 | 2003-03-26 | 威盛电子股份有限公司 | Multilayer balanced inductor |
| US6972658B1 (en) * | 2003-11-10 | 2005-12-06 | Rf Micro Devices, Inc. | Differential inductor design for high self-resonance frequency |
| CN1649042A (en) * | 2004-01-30 | 2005-08-03 | 联华电子股份有限公司 | Symmetrical type inductance |
| CN1606127A (en) * | 2004-10-28 | 2005-04-13 | 复旦大学 | Method for designing low parasitic capacity differential driving symmetrical inductance through standard integrated circuit process |
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| CN1889205A (en) | 2007-01-03 |
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