CN100499556C - High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor - Google Patents

Abstract

This invention discloses a high speed asynchronous interconnected communication network of an isomeric multi-core processor composed of multiple communication nodes, multiple communication stacks, a comunication ring and an arbitrator, in which, one comunication stack is connected with one node by data line, all the stacks are connected in pairs by the ring and the arbitrator is connected with the stacks by data lines, and the stack is composed of a local decoder, a node configuring part and a channel controller, the arbitrator is composed of a sub-part for testing conflict of devices, a clockwise resource distributing part, a counter clockwise resource distributing part, a register set of clockwise matters, a register set of counter clockwise matters and a resource recovery part, and the ring is a ring line connecting all the communication stacks in pairs and composed of multiple crossed and dual-way channels, a requiring signal line and a confirmation signal line.

Description

High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor

Technical field: the present invention relates to the communication network of integrated circuit fields microprocessor internal, especially the high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor inside.

Background technology: along with the development of integrated circuit technology, a plurality of micro-processor kernels are integrated in the same chip constitute polycaryon processor, become a kind of effective high-performance processor system design approach, more powerful disposal ability and the concurrency of Geng Gao can be provided.According to the kind that includes processor core, multi-core microprocessor can be divided into two kinds of isomorphism multi-core microprocessor and heterogeneous polynuclear microprocessors.Wherein, the heterogeneous polynuclear microprocessor internal comprises different processor cores, and different processor cores is finished different functions in the heterogeneous polynuclear microprocessor.How be integrated in the system-level microprocessor chip dissimilar processor cores is seamless, the design of interlinkage communication network has been proposed challenge.

Bus is present most widely used chip-on communication structure, as AMBA (the AdvancedMicroprocessor Bus Architecture) bus of ARM company.But the broadcast characteristic of bus makes the delay of signal and power consumption along with the scale of microprocessor sharply increases, and poor expandability simultaneously is not suitable for the communication requirement of following more extensive multi-core microprocessor.

Traditional static state connects network, the ring of introducing in " Computer Architecture " chapter 7 of publishing as Higher Education Publishing House in 2000, the communication link by one-way transmission couples together the communication node in the network, to realize the transmission of point-to-point, advantage is simple in structure, realizes easily.But traditional ring communication structure adopts the global synchronization clock to communicate synchronously, the mode that adopts token to distribute is distributed to communication node communication network right to occupation, at the communication node number more for a long time, the efficient that token distributes is lower, and because can only one-way transmission, will be in the communication between distance two communication nodes far away on the communication link through the forwarding one by one of intermediate node, the overhead of communication is very big.

(Globally Asynchronous Locally Synchronous, GALS) interconnection technique is also becoming the focus of research to the Global Asynchronous local synchronization at present.It relatively is fit to solve SOC (system on a chip) (System onChip, problem when having a plurality of clock zone SoC), each IP module and interconnect bus in the system are kept apart, interconnection adopts the mode of asynchronous circuit to realize, realize communication by Handshake Protocol, and can be well and the integration of existing synchronous circuit module.In design, no longer adopt the global synchronization clock and use the mode of asynchronous handshake to control communication, saved the more and more huger power consumption that synchronised clock produced in the Modern microprocessor design.Owing to increased extra communication overhead, and used a large amount of state holding elements in the circuit, made that the realization cost of GALS technology is higher.

Summary of the invention: the technical problem to be solved in the present invention is at the interlinkage communication network of existing multi-core microprocessor or can only supports to have the kernel of same frequency, extensibility is relatively poor, problems such as the efficiency of transmission concurrency is relatively poor, transmission frequency is limited, propose a kind of new heterogeneous polynuclear microprocessor internal and be responsible for the high-speed asynchronous interlinkage communication network of each inter-node communication, for the heterogeneous polynuclear microprocessor provides better transmission concurrency and higher transmission frequency.

High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor of the present invention is formed by connecting by a plurality of communication nodes, a plurality of communication stack, a communication loop and a moderator.Each communication stack is connected by data wire with a communication node, and all communication stacks link together in twos by communication loop, and moderator is connected by data wire with each communication stack.Communication node is sent out access request to the communication stack that is attached thereto, communication stack is deciphered access request, determine whether to send out transactions requests to moderator, it is communication request, to obtain the access right that the equipment of being requested is another communication node, if the equipment that is requested allows visit, the equipment of being requested will send confirmation signal, and the communication node of sending out access request obtains access right.Moderator then is responsible for the affairs arbitration, judges that can the communication node of the request of sending obtain access right, and the control communication stack is cut into different transmission paths with communication loop and makes the communication node that obtains access right finish communication.

Communication node is to send access request or accessed equipment to communication network, each communication node can also can communicate as slave unit as main equipment, when this communication node is called main equipment when other communication node sends access request, when receiving the access request that comes from other communication node, this communication node is called slave unit.Communication node can be different micro-processor kernel, also can be functional unit, storage control module, the peripheral module of simple computation and the interface module that is connected with other system etc., is mainly used in to handle the each task that microprocessor is born.Each communication node all has a unique device id, and promptly device numbering supposes to have in the microprocessor N communication node, is each communication node ID that allocates a device when microprocessor system designs, and for convenience, device id is 0 to N-1.

Communication stack is made up of partial decode device, node configuration parts and channel controller.When communication node during as main equipment, the communication stack that is attached thereto connects corresponding passage according to the channel allocation information of moderator, sends out request signal according to the asynchronous handshake agreement to slave unit simultaneously; When communication node during as slave unit, the communication stack that is attached thereto connects corresponding passage according to the channel allocation information of moderator, sends out confirmation signal according to the asynchronous handshake agreement to main equipment simultaneously; When communication node does not communicate, when the communication stack that is attached thereto is the intermediate path of conduct communication, communication stack connects corresponding passage according to the channel allocation information of moderator, simultaneously also as the transmission path of request signal and confirmation signal, transport communication data and handshake between main equipment and slave unit.

Communication node, moderator that the partial decode device is corresponding with communication stack on the one hand link to each other, and link to each other with node configuration parts, channel controller on the one hand.The access request that partial decode device received communication node is sent is also deciphered access request, determines sources traffic node and destination communication node address (ID) and access type (read/write); Simultaneously, it reads the node configuration information that is stored in the node configuration parts, predefined master/slave arrangement address space in decoding destination communication node address of gained and the node configuration information is compared, if the destination communication node address of decoding gained is not effective reference address, then do not send transactions requests to moderator; If effective reference address, the partial decode device is sent out transactions requests to moderator, and sources traffic node and the destination communication node address and the access type (read/write) of decoding gained are issued moderator, asks the access right of communication network.

The node configuration parts are memories of the node configuration information of a corresponding communication node of record, its size is by the size decision of the configuration information of corresponding communication node, its both corresponding with partial decode device, communication stack communication node links to each other, and links to each other with other node configuration parts in adjacent two communication stacks on the communication loop again.According to the microprocessor internal structure, the configuration parameter of each communication node is set when microprocessor system designs, distribute to fixing node configuration information of each communication node.The configuration information of each communication node is made up of 8 words, the 1st word is sign, and wherein the 0th to the 4th is interrupt number IRQ, and the 5th to the 9th is the VERSION of version number, the the 12nd to the 23rd is device id, and the 24th to the 31st is the Vendor ID of manufacturer; Reference address, access rights and I/O configuration information when 8 words of the 5th word to the write down this communication node as slave unit, the 0th to the 3rd is I/O configuration information TYPE in each word, the 16th and the 17th has indicated two kinds of access rights C (Cacheable respectively, but buffer memory) with P (Prefetchable, can look ahead), the 20th is reference address to the 31st; Remaining 3 words (the 2nd to the 4th word) use for User Defined.The configuration information of each communication node all originates in address space 0 x FFFFF000 with the form of read-only form, wherein the address space of main equipment is 0 x FFFFF000～0 x FFFFF7FF, and the address space of slave unit is 0 x FFFFF800～0 x FFFFFFFC.Because the node configuration parts in the communication network all are to link to each other in twos, so any communication node can both read the node configuration information of other communication node.

Channel controller is the control switch of passage, is made up of first control assembly, second control assembly, first switch block and second switch parts.First switch block is the identical MUX of structure with the second switch parts; First control assembly is the identical controller of structure with second control assembly.The input of first switch block and second switch parts links to each other with each passage, and output all links to each other with the data wire of communication node; The control signal wire of first switch block links to each other with first control assembly, the control signal wire of second switch parts links to each other with second control assembly, accept the channel allocation signal of first control assembly, the generation of second control assembly respectively, the connection of the passage that control links to each other with communication stack or shutoff form the transmission path that signal post needs in communication network.First control assembly and second control assembly all link to each other with request signal line, confirmation signal line and moderator on the communication loop, link to each other with the inside confirmation holding wire by the inside request signals line between first control assembly and second control assembly.A switching circuit is arranged respectively on inside request signals line and the inside confirmation holding wire, and when corresponding communication node was main equipment or slave unit, switching circuit was opened, and inside request signals line and inside confirmation holding wire disconnect respectively; When the communication stack of correspondence during just as the intermediate node on the master-slave equipment communication path, the switching circuit closure, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, and the connection between this moment two control assemblies is only as the transmission path of request signal and confirmation signal between main equipment and the slave unit.

Resource allocation parts, counterclockwise resource allocation parts homogeneous phase connect clockwise in first control assembly, second control assembly and the moderator, channel arrangement signal according to clockwise resource allocation parts or counterclockwise resource allocation parts in the direction reception moderator of communication are sent generates the channel allocation signal according to the channel arrangement signal and issues first switch block and second switch parts respectively.

If present node is as the main equipment of communication, and carry out be clockwise communication the time, communication process is undertaken by second control assembly and second switch parts, the channel arrangement signal that the clockwise resource allocation parts of the second control assembly selective reception are sent; If carry out be anticlockwise communication the time, communication process is undertaken by first control assembly and first switch block, the channel arrangement signal that the counterclockwise resource allocation parts of the first control assembly selective reception are sent.A clockwise process is: second control assembly becomes " 1 " to send out request signal to destination communication node with the level on the request signal line by " 0 ", when second control assembly detects level on the confirmation signal line and becomes " 1 " by " 0 ", show that destination communication node has received request signal and sent the affirmation signal that can communicate.At this moment, the channel arrangement signal that second control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues the second switch parts, the second switch parts passage that communication transmission path is required is opened, close other unwanted passage, communication node communicates along the transmission path that forms, and second control assembly becomes " 0 " with the level on the request signal line by " 1 " simultaneously.When second control assembly detects level on the confirmation signal line and becomes " 0 " by " 1 ", the sign off between the expression communication node.Anticlockwise communication process is undertaken by first control assembly and first switch block, and the channel arrangement signal that first control assembly is sent according to counterclockwise resource allocation parts generates the channel allocation signal and issues first switch block, and other is the same with clockwise communication process.

Current communication node as communication slave unit the time, if carry out clockwise communication, communication process is undertaken by first control assembly and first switch block, the channel arrangement signal that the clockwise resource allocation parts of the first control assembly selective reception are sent; If what carry out is anticlockwise communication, communication process is undertaken by second control assembly and second switch parts, the channel arrangement signal that the counterclockwise resource allocation parts of the second control assembly selective reception are sent.A clockwise communication process is: when first control assembly detects level on the request signal line and becomes " 1 " by " 0 ", first control assembly becomes " 1 " with the level on the confirmation signal line by " 0 ", expression has received request signal, can communicate, and the channel arrangement signal that first control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues first switch block, first switch block passage that communication transmission path is required is opened, and closes other unwanted passage.The level that detects on the request signal line when first control assembly becomes " 0 " by " 1 ", and after communication finished, first control assembly became " 0 " with the level on the confirmation signal line by " 1 ", finishes handshake procedure, the expression sign off.Anticlockwise communication process is undertaken by second control assembly and second switch parts, and the channel arrangement signal that second control assembly is sent according to counterclockwise resource allocation parts generates the channel allocation signal, and other is the same with clockwise communication process.

If current communication node is neither main equipment neither slave unit, and the communication stack that is attached thereto is during just as the intermediate node on the master-slave equipment communication path, if carry out clockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that clockwise resource allocation parts are sent; If carry out anticlockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that counterclockwise resource allocation parts are sent.First control assembly and second control assembly generate the channel allocation signal and issue first switch block and second switch parts respectively, and two switch blocks select the required passage of communication transmission path to open respectively, close other unwanted passage.Simultaneously, the switching circuit closure on inside request signals line and the inside confirmation holding wire, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, request signal and confirmation signal between the transmission master-slave equipment.Can not produce extra communication overhead as the just effect of line that the communication stack of intermediate node on the communication path plays this moment, therefore at the communication delay between the master-slave equipment except the delay of handshake procedure, have only the delay of line.

Because whole communication process is to control by shaking hands between request signal and the confirmation signal, is not to be undertaken synchronously by synchronizing clock signals, thereby does not need to design the global synchronization clock in communication network.Simultaneously, adopt the circuit of synchronised clock, for synchronous needs, the time that its executable operations spent must be the integral multiple of clock cycle, and not having synchronizing clock signals in the asynchronous circuit, the circuit in each parts can carry out work according to the execution speed of self.The for example partial decode device action of sending transactions requests to moderator, the execution speed of ifs circuit is 3ns, is the synchronised clock of 5ns and adopt the clock cycle, the execution of this action need spend a clock cycle so; And not adopting the mode of synchronised clock, it is exactly the execution speed of circuit itself that asynchronous circuit is carried out the time that this action spends, and is 3ns.

After communication process was finished, if carry out clockwise communication, second control assembly in the communication stack that connects as the communication node of main equipment was sent out the transaction retraction signal to moderator; If carry out anticlockwise communication, first control assembly in the communication stack that connects as the communication node of main equipment is sent out the transaction retraction signal to moderator.Control assembly is sent out the transaction retraction signal to moderator, and the request moderator is cancelled current affairs and discharged resource, and whole communication process finishes.

Moderator is made up of slave unit collision detection parts, clockwise resource allocation parts, counterclockwise resource allocation parts, clockwise affairs registers group, counterclockwise affairs registers group and resource recovery part.

Slave unit collision detection parts link to each other with partial decode device in all communication stacks on the communication loop on the one hand, link to each other with clockwise resource allocation parts, counterclockwise resource allocation parts on the one hand.Clockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, clockwise affairs registers group.Counterclockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, counterclockwise affairs registers group.The resource recovery part connects first control assembly and second control assembly in all communication stacks, also links to each other with clockwise affairs registers group, clockwise resource allocation parts, counterclockwise affairs registers group and counterclockwise resource allocation parts.The affairs registers group links to each other with clockwise resource allocation parts with the resource recovery part clockwise, and the affairs registers group links to each other with clockwise resource allocation parts with the resource recovery part counterclockwise.

The transactions requests that the partial decode device is sent in all communication stacks on the slave unit collision detection parts received communication ring.When a plurality of communication nodes communicate simultaneously as main equipment, a plurality of main equipments send situation from access request to same slave unit can appear, slave unit collision detection this moment parts are determined the priority of these transactions requests according to the resolving strategy of circular priority, the priority of each communication node is by the operating system (operating system that refers to the microprocessor operation, the such operating system of for example embedded Liunx/WinCE) specify in advance, but in a single day the communication node of obtaining the communication network control discharges taking of communication network, its priority becomes minimum, priority rises inferior to its communication node priority, so the priority of communication node is to rise successively, moves in circles.Slave unit collision detection parts are selected the transactions requests of the highest communication node of priority, and other will not be accepted to the access request that same slave unit sends.If N communication node arranged in the microprocessor, if main equipment to the communication of slave unit through the number of communication node less than N/2, be clockwise communication, slave unit collision detection parts are issued clockwise resource allocation parts with transactions requests; Otherwise, if main equipment to the communication of slave unit through the number of communication node greater than N/2, be anticlockwise communication, slave unit collision detection parts are issued counterclockwise resource allocation parts with transactions requests.If main equipment equals N/2 to the number of the communication process communication node of slave unit, because main equipment is to the communication of slave unit, no matter adopt clockwise or counterclockwise, the communication node number of process all equates, so this moment, the communication overhead of dual mode was identical, in such cases, both can take clockwise communication, also can take counterclockwise communication.

The resource allocation parts are parts that the channel resource on the clockwise or counterclockwise communication direction is distributed with counterclockwise resource allocation parts clockwise, and their structure is identical.After clockwise the resource allocation parts receive the transactions requests that slave unit collision detection parts send, visit clockwise affairs registers group on the one hand, read the current transaction information that is in active state, i.e. the relevant information of affairs, as the master and slave device address of communicating by letter, state etc.; The access resources recovery part obtains doing/not busy state of each communication node and passage on the one hand, to determine current resource operating position; According to transactions requests, current active transaction information and resource operating position, select the idle channel that can between the master-slave equipment of communication, form transmission path, thereby be that the communication of being asked generates channel configuration information, indicate the numbering of the passage of obtaining access rights, and channel configuration information issued first control assembly and second control assembly in all communication stacks, the transaction information with this road communication is updated to clockwise affairs registers group simultaneously.The resource allocation parts distribute the channel resource on the counterclockwise communication direction counterclockwise, and just its visit and renewal is counterclockwise affairs registers group.

Affairs registers group and affairs register set stores transaction information clockwise counterclockwise, each free N/2 affairs register formed, and N is the number of communication node in the microprocessor.Each affairs register writes down the transaction information of a paths, what transaction information was represented is the relevant information that this paths is once communicated by letter, comprise sources traffic node address, destination communication node address and a significance bit, when significance bit is " 1 ", show this road communication well afoot, be active state; When significance bit was " 0 ", this road communication finished, and is non-active state.When new transactions requests, if be clockwise communication, clockwise the resource allocation parts upgrade the affairs register in the clockwise affairs registers group, sources traffic node address, destination communication node address and significance bit " 1 " when promptly writing this paths and carrying out new communication; If be anticlockwise communication, the resource allocation parts upgrade the affairs register in the counterclockwise affairs registers group counterclockwise.

The resource recovery part writes down the operating position of all communication nodes and passage on the one hand, is divided into " doing ", " spare time " two states; On the other hand according to the transaction retraction signal with clockwise affairs registers group or the counterclockwise affairs register significance bit reset in the affairs registers group.The resource recovery part is connected to first control assembly and second control assembly in all communication stacks, receives the transaction retraction signal that control assembly sends after communication is finished.If clockwise communication, the resource recovery part receives the transaction retraction signal of sending as second control assembly in the communication stack of the communication node connection of main equipment, with the active position of this road affairs register in the clockwise affairs registers group is " 0 ", the communication node that this road office takies in the resource recovery part and the state of passage are changed to " spare time " simultaneously, the expression resource finishes, and takies resource and is released; If be anticlockwise communication, the resource recovery part receives the transaction retraction signal of sending as first control assembly in the communication stack of the communication node connection of main equipment, with the active position of this road affairs register in the counterclockwise affairs registers group is " 0 ", the communication node that this road office takies in the resource recovery part and the state of passage are changed to " spare time " simultaneously, the expression resource finishes, and takies resource and is released.Occupation condition new in the communication network has just been arranged like this, the visit next time of funding source distribution member in the resource recovery part.

Communication loop is the annular line that all communication stacks are connected in twos, is made up of two-way many passages, a request signal line, the confirmation signal line of intersection.First switch block of channel controller links to each other with the second switch parts in passage and the communication stack, and first control assembly of channel controller links to each other with first control assembly in request signal line, confirmation signal line and the communication stack.The number K of passage is relevant with the number N of communication node, and K is that N/4 round numbers and K can only be even number, for example, and 1＜N≤8 o'clock, K=2, and 8＜N≤16 o'clock, K=4.Every paths all is the path of transfer of data, and the transmission direction between adjacent two passages is opposite.The request signal line transmits request signal according to Handshake Protocol between communication stack, the confirmation signal line between communication stack according to Handshake Protocol delivery confirmation signal, transmission by request signal between the communication stack and confirmation signal finish receiving whole handshake procedure.

Finishing the communication process on the clockwise direction among the present invention between the communication node is:

(1) send out access request as the partial decode device of one or more communication nodes in communication stack of main equipment, the request communication network is finished communication for it distributes a transmission paths.

(2) the partial decode device receives the access request row decoding of going forward side by side, and determines the destination communication node address of being asked.Simultaneously the partial decode device reads node configuration information in the node configuration parts with the reference address of obtaining communication node, to decipher in the address of gained and the node configuration information predefined master/slave arrangement address space simultaneously compares, if not effective reference address, then do not send transactions requests to moderator; If effective reference address, just will decipher the sources traffic node of gained and destination communication node address and access type (read/write) and issue moderator, ask the access right of communication network.

(3) the slave unit collision detection parts in the moderator receive transactions requests, at first confirm whether exist a plurality of main equipments to send the situation of access request to same slave unit, if exist, then adopt the resolving strategy of circular priority to determine to send the priority of the communication node of access request, select the transactions requests of the highest communication node of priority, other then is not accepted to the access request that same slave unit sends.According to the direction of communication, slave unit collision detection parts are issued corresponding clockwise resource allocation parts with selected transactions requests.

(4) when clockwise resource allocation parts receive the transactions requests that slave unit collision detection parts send, visit clockwise affairs registers group on the one hand, read the current transaction information that is in active state; Access resources recovery part on the one hand obtains busy/not busy state of each communication node in the microprocessor and passage, determines current resource operating position; According to transactions requests, current active transaction information and resource operating position is that the communication of being asked generates channel configuration information, select the idle channel that can between the master-slave equipment of communication, form transmission path, thereby be that the communication of being asked generates channel configuration information, indicate the numbering of the passage that obtains access rights, and channel configuration information is issued first control assembly and second control assembly in all communication stacks.Transaction information with this road communication is updated to clockwise affairs registers group simultaneously.

(5) if current communication node as communication main equipment, second control assembly will become " 1 " by " 0 " with the level on the request signal line, send out request signal to destination communication node, when second control assembly detects level on the confirmation signal line and becomes " 1 " by " 0 ", show that destination communication node has received request signal and sent the affirmation signal that can communicate.At this moment, the channel arrangement signal that second control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues the second switch parts, select the required passage of communication transmission path to open, close other unwanted passage, communication node can communicate along the transmission path that forms, and second control assembly becomes " 0 " with the level on the request signal line by " 1 " simultaneously.When second control assembly detects level on the confirmation signal line and becomes " 0 " by " 1 ", the sign off between the expression communication node.When first control assembly detects level on the request signal line and becomes " 1 " by " 0 ", first control assembly becomes " 1 " with the level on the confirmation signal line by " 0 ", expression has received request signal, can communicate, and the channel arrangement signal that first control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues first switch block, select the required passage of communication transmission path to open, close other unwanted passage.The level that detects on the confirmation signal line when first control assembly becomes " 0 " by " 1 ", and after communication finished, first control assembly could become " 0 " by " 1 " with the level on the confirmation signal line, finishes handshake procedure, the expression sign off.If current communication node is neither main equipment neither slave unit, and the communication stack that is attached thereto is during just as the intermediate node on the master-slave equipment communication path, if carry out clockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that clockwise resource allocation parts are sent; If carry out anticlockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that counterclockwise resource allocation parts are sent.First control signal and second control signal generate the channel allocation signal and issue first switch block and second switch parts respectively, and two switch blocks select the required passage of communication transmission path to open respectively, close other unwanted passage.Simultaneously, the switching circuit closure on inside request signals line and the inside confirmation holding wire, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, request signal and confirmation signal between the transmission master-slave equipment.

(6) after second control assembly in the communication stack that connects as the communication node of main equipment detected level on the confirmation signal line and becomes " 0 " by " 1 ", second control assembly sent the transaction retraction signal to moderator, and the request moderator is cancelled current affairs.

(7) the resource recovery part receives after the transaction retraction signal that second control assembly in the communication stack that connects as the communication node of main equipment sends, the communication node that this road office is taken and the state of passage are changed to " spare time ", obtain occupation condition new in the communication network.Active position with this road affairs register in the clockwise affairs registers group is " 0 " simultaneously, represents that these road affairs finish, and are in non-active state.

According to the occupation condition in the communication network, at the multichannel communication that can carry out simultaneously on the communication loop on clockwise direction or the counter clockwise direction.

Adopt the present invention can reach following technique effect:

(1) support the parallel transmission of point-to-point between all communication nodes: the passage in the communication loop can be cut into many transmission paths by channel controller, and the communication on every transmission paths can executed in parallel.

(2) adopt handshake to communicate control between the communication node, do not need to design huge global synchronization clock and control communication, can save power consumption greatly.

(3) communication speed is faster: adopt the communication of global clock control, each step action of communication all relies on global clock synchronous, and the time that whole communication is finished is the integral multiple of clock cycle; And adopt asynchronous handshake technology, each step action of communication only to depend on the module self speed of execution, therefore whole communication time of finishing can be less than or equal to the time when adopting global clock synchronous.

(4) do not need global clock to carry out synchronously, thereby can support the communication node of multi-clock zone, enlarged the scope of application of communication network;

(5) node configuration information can be provided with by configuration parameter, and the designer can revise node configuration information easily by configuration parameter is set, with system extension to the communication between the more nodes.

Description of drawings:

Figure 1A MBA bus structures schematic diagram

The ring topological structure schematic diagram of introducing among Fig. 2 " Computer Architecture "

Fig. 3 adopts the interconnection structure schematic diagram of GALS technology

Fig. 4 communication network architecture schematic diagram of the present invention

Fig. 5 communication stack structural representation of the present invention

Fig. 6 moderator structural representation of the present invention

Affairs register-stored content schematic diagram in Fig. 7 moderator of the present invention

Fig. 8 communication node configuration information of the present invention form

Fig. 1 is the AMBA bus structures schematic diagram of ARM company.The AMBA bus generally is made up of the peripheral bus APB (Advanced Peripheral Bus) of high performance system bus AHB (Advanced High Performance Bus) and low-power consumption, is connected by the AHB/APB bridge between AHB and the APB.Ahb bus is mainly used in the module that connects high-performance, high clock frequency, as CPU, ram in slice, dma bus controller, external memory interface etc.; APB is mainly used in the connection that does not need high-performance streamline interface or do not need the ancillary equipment of high bandwidth interface, as URAT, GPIO, timer, interrupt control unit etc.The IP module of CPU and other friction speed can organically combine like this.But the broadcast characteristic of bus makes the delay of signal and power consumption sharply increase along with the scale of microprocessor, because extensibility is relatively poor, is not suitable for the communication requirement of following more massive multi-core microprocessor simultaneously.

Fig. 2 is the topological structure schematic diagram of the ring introduced in " Computer Architecture " chapter 7 of publishing of Higher Education Publishing House in 2000.Ring couples together the communication node in the network by communication link, to realize the transmission of point-to-point, its advantage is simple in structure, be easy to realize, but traditional ring communication structure adopts the global synchronization clock to communicate synchronously, the mode that adopts token to distribute is distributed to communication node communication network right to occupation, at the communication node number more for a long time, the efficient that token distributes is lower, and because can only one-way transmission, will be in the communication between distance two communication nodes far away on the communication link through the forwarding one by one of intermediate node, the overhead of communication is very big.

Fig. 3 (a) is for adopting the interconnection structure schematic diagram of GALS technology, and Fig. 3 (b) is the structural representation of communication node and stack.Adopt the interference networks overall situation of GALS technology to adopt the asynchronous handshake mode, do not have the global synchronization clock, each communication node adopts the module of local synchronization, by oneself independently local synchronization clock control.Stack shown in Fig. 3 (b) is simple cross bar switch, the design of communication node is comparatively complicated, GALS interface and the FIFO that is connected input, output have respectively been comprised in the communication node, also at IP (Intellectual Property, refer to logic module or data module in the integrated circuit (IC) design) designed input, output port control logic between module and the GALS interface, communicating by letter between realization IP module and the GALS interface.This technology relatively be fit to solve the problem when having a plurality of clock zone among the SoC, can effectively realize the integration of asynchronous communication and existing synchronous circuit module.But the design of complicated communication node has increased extra communication overhead, and needs to use a large amount of state holding elements in the GALS interface circuit, makes that the realization cost of GALS technology is higher.

Fig. 4 is a communication network architecture schematic diagram of the present invention.Whole communication network is formed by connecting by a plurality of communication nodes, a plurality of communication stack, a communication loop and a moderator.Each communication stack connects by data wire with a corresponding communication node, and all communication stacks link together in twos by communication loop, and moderator then is connected by data wire with each communication stack.Communication node sends access request to the communication stack of correspondence, and communication stack is deciphered access request, determines whether to send transactions requests to moderator the access right of requesting service to obtain.Moderator then is responsible for the affairs arbitration, and can judgment device obtain access right, and the control communication stack is cut into different transmission paths with communication loop and makes the communication node that obtains access right finish communication.

Fig. 5 is a communication stack structural representation of the present invention, comprises partial decode device, node configuration parts and channel controller.The partial decode device links to each other with communication node, and the access request that the received communication node sends is by deciphering the destination communication node address of determining visit.The partial decode device also is connected with the node configuration parts, reads the reference address of communication node, if the address of decoding gained is an effective address, the partial decode device will send transactions requests to moderator.The node configuration parts are memories, and all node configuration parts all are to link to each other in twos in the communication network, and any communication node can both read the node configuration information of other communication node.Channel controller is the control switch of passage, is made up of first control assembly, second control assembly, first switch block and second switch parts.First switch block is the identical MUX of structure with the second switch parts; First control assembly is the identical controller of structure with second control assembly.The input of first switch block and second switch parts links to each other with each passage, and output all links to each other with the data wire of communication node; The control signal wire of first switch block links to each other with first control assembly, the control signal wire of second switch parts links to each other with second control assembly, accept the channel allocation signal of first control assembly, the generation of second control assembly respectively, the connection of the passage that control links to each other with communication stack or shutoff form the transmission path that signal post needs in communication network.First control assembly and second control assembly all link to each other with request signal line, confirmation signal line and moderator on the communication loop, link to each other with the inside confirmation holding wire by the inside request signals line between first control assembly and second control assembly.The inside request signals line is connected with the confirmation signal line with the request signal line of the outside that is connected to two control assemblies respectively with the inside confirmation holding wire.A switching circuit is arranged respectively on inside request signals line and the inside confirmation holding wire, and when corresponding communication node was main equipment or slave unit, switching circuit was opened, and inside request signals line and inside confirmation holding wire disconnect respectively; When the communication stack of correspondence during just as the intermediate node on the master-slave equipment communication path, the switching circuit closure, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, and the connection between this moment two control assemblies is only as the transmission path of request signal and confirmation signal between main equipment and the slave unit.In first control assembly, second control assembly and the moderator clockwise the resource allocation parts, resource allocation parts homogeneous phase connects counterclockwise, receives in the moderator resource allocation parts clockwise or the channel arrangement signal sent of resource allocation parts counterclockwise according to the direction of communication.First control assembly and second control assembly generate the channel allocation signal according to the channel arrangement signal and issue first switch block and second switch parts respectively.After communication process was finished, if carry out clockwise communication, second control assembly in the communication stack that connects as the communication node of main equipment was sent out the transaction retraction signal to moderator; If carry out anticlockwise communication, first control assembly in the communication stack that connects as the communication node of main equipment is sent out the transaction retraction signal to moderator, and whole communication process finishes.

Fig. 6 is a moderator structural representation of the present invention.Moderator is made up of slave unit collision detection parts, clockwise resource allocation parts, counterclockwise resource allocation parts, clockwise affairs registers group, counterclockwise affairs registers group and resource recovery part.Slave unit collision detection parts link to each other with partial decode device in all communication stacks on the communication loop on the one hand, link to each other with clockwise resource allocation parts, counterclockwise resource allocation parts on the one hand.Clockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, clockwise affairs registers group.Counterclockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, counterclockwise affairs registers group.The resource recovery part connects first control assembly and second control assembly in all communication stacks, also links to each other with clockwise affairs registers group, clockwise resource allocation parts, counterclockwise affairs registers group and counterclockwise resource allocation parts.The affairs registers group links to each other with clockwise resource allocation parts with the resource recovery part clockwise, and the affairs registers group links to each other with clockwise resource allocation parts with the resource recovery part counterclockwise.

Fig. 7 is an affairs register-stored content schematic diagram, each affairs register writes down the transaction information of a paths, what transaction information was represented is the relevant information that this paths is once communicated by letter, comprise sources traffic node address, destination communication node address and a significance bit, when significance bit is " 1 ", show this road communication well afoot, be active state; When significance bit was " 0 ", this road communication finished, and is non-active state.When new transactions requests, if be clockwise communication, clockwise the resource allocation parts upgrade the affairs register in the clockwise affairs registers group, sources traffic node address, destination communication node address and significance bit " 1 " when promptly writing this paths and carrying out new communication; If be anticlockwise communication, the resource allocation parts upgrade the affairs register in the counterclockwise affairs registers group counterclockwise.

Fig. 8 is a communication node configuration information form, the configuration information of each communication node is made up of 8 words, the 1st word is sign, wherein the 0th is interrupt number IRQ to the 4th, the 5th is the VERSION of version number to the 9th, the the 12nd to the 23rd is device id, and the 24th to the 31st is the Vendor ID of manufacturer; Address information, access rights and the I/O configuration information of slave unit have then been write down from 8 words of the 5th word to the, the 0th to the 3rd is I/O configuration information TYPE in each word, the 16th and the 17th has indicated two kinds of access rights C (Cacheable respectively, but buffer memory) with P (Prefetchable, can look ahead), the 20th is reference address to the 31st; Remaining 3 words (the 2nd to the 4th word) use for User Defined.The configuration information of all communication nodes all originates in 0 x FFFFF000 with the form of read-only form, and wherein the form space of main equipment is 0 x FFFFF000～0 x FFFFF7FF, and the form space of slave unit is 0 x FFFFF800～0 x FFFFFFFC.Because the node configuration parts in the communication network all are to link to each other in twos, so any communication node can both read the node configuration information of other communication node.

Claims (12)

1. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor, it is characterized in that it is formed by connecting by a plurality of communication nodes, a plurality of communication stack, a communication loop and a moderator, each communication stack is connected by data wire with a communication node, all communication stacks link together in twos by communication loop, and moderator is connected by data wire with each communication stack; Communication node is to send access request or accessed equipment to communication network, and it is device id that each communication node all has a unique device numbering; Communication stack is made up of partial decode device, node configuration parts and channel controller; Moderator is made up of slave unit collision detection parts, clockwise resource allocation parts, counterclockwise resource allocation parts, clockwise affairs registers group, counterclockwise affairs registers group and resource recovery part; Communication loop is the annular line that all communication stacks are connected in twos, is made up of two-way many passages, a request signal line, the confirmation signal line of intersection; Communication node is sent out access request to the communication stack that is attached thereto, communication stack is deciphered access request, determine whether to send out transactions requests to moderator, it is communication request, to obtain the access right that the equipment of being requested is another communication node, if the equipment that is requested allows visit, the equipment of being requested will send confirmation signal, and the communication node of sending out access request obtains access right; Moderator then is responsible for the affairs arbitration, judges that can the communication node of the request of sending obtain access right, and the control communication stack is cut into clockwise or counterclockwise transmission path with communication loop and makes the communication node that obtains access right finish communication.

2. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 1, it is characterized in that corresponding with communication stack on the one hand communication node, the moderator of partial decode device in the communication stack links to each other, and links to each other with node configuration parts, channel controller on the one hand; The access request that partial decode device received communication node is sent is also deciphered access request, determines sources traffic node and destination communication node address and access type; Simultaneously, it reads the node configuration information that is stored in the node configuration parts, predefined master/slave arrangement address space in decoding destination communication node address of gained and the node configuration information is compared, if the destination communication node address of decoding gained is not effective reference address, then do not send transactions requests to moderator; If effective reference address, the partial decode device is sent out transactions requests to moderator, and sources traffic node and the destination communication node address and the access type of decoding gained are issued moderator, asks the access right of communication network.

3. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 1, it is characterized in that the node configuration parts in the communication stack are memories of the node configuration information of a corresponding communication node of record, its size is by the size decision of the configuration information of corresponding communication node, its both corresponding with partial decode device, communication stack communication node links to each other, and links to each other with other node configuration parts in adjacent two communication stacks on the communication loop again.

4. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 3, the configuration information that it is characterized in that described communication node is made up of 8 words, the 1st word is sign, wherein the 0th is interrupt number IRQ to the 4th, the 5th is the VERSION of version number to the 9th, the the 12nd to the 23rd is device id, and the 24th to the 31st is the Vendor ID of manufacturer; Reference address, access rights and I/O configuration information when 8 words of the 5th word to the write down this communication node as slave unit, the 0th to the 3rd is I/O configuration information TYPE in each word, but the 16th and the 17th has indicated two kinds of cache access authority C respectively, with the access rights P that can look ahead, the 20th is reference address to the 31st; The the 2nd to the 4th word uses for User Defined; The configuration information of each communication node all originates in address space 0xFFFFF000 with the form of read-only form, and wherein the address space of main equipment is 0xFFFFF000～0xFFFFF7FF, and the address space of slave unit is 0xFFFFF800～0xFFFFFFFC.

5. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 1, it is characterized in that the channel controller in the communication stack is the control switch of passage, be made up of first control assembly, second control assembly, first switch block and second switch parts: first switch block is the identical MUX of structure with the second switch parts; First control assembly is the identical controller of structure with second control assembly; The input of first switch block and second switch parts links to each other with each passage, and output all links to each other with the data wire of communication node; The control signal wire of first switch block links to each other with first control assembly, the control signal wire of second switch parts links to each other with second control assembly, accept the channel allocation signal of first control assembly, the generation of second control assembly respectively, the connection of the passage that control links to each other with communication stack or shutoff form the transmission path that signal post needs in communication network; First control assembly and second control assembly all link to each other with request signal line, confirmation signal line and moderator on the communication loop, link to each other with the inside confirmation holding wire by the inside request signals line between first control assembly and second control assembly; A switching circuit is arranged respectively on inside request signals line and the inside confirmation holding wire, and when corresponding communication node was main equipment or slave unit, switching circuit was opened, and inside request signals line and inside confirmation holding wire disconnect respectively; When the communication stack of correspondence during just as the intermediate node on the master-slave equipment communication path, the switching circuit closure, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, and the connection between this moment two control assemblies is only as the transmission path of request signal and confirmation signal between main equipment and the slave unit.

6. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 1, it is characterized in that in the moderator, slave unit collision detection parts link to each other with partial decode device in all communication stacks on the communication loop on the one hand, link to each other with clockwise resource allocation parts, counterclockwise resource allocation parts on the one hand; Clockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, clockwise affairs registers group; Counterclockwise the resource allocation parts link to each other with first control assembly, second control assembly in all communication stacks, also link to each other with slave unit collision detection parts, resource recovery part, counterclockwise affairs registers group; The resource recovery part connects first control assembly and second control assembly in all communication stacks, also links to each other with clockwise affairs registers group, clockwise resource allocation parts, counterclockwise affairs registers group and counterclockwise resource allocation parts; The affairs registers group links to each other with clockwise resource allocation parts with the resource recovery part clockwise, and the affairs registers group links to each other with counterclockwise resource allocation parts with the resource recovery part counterclockwise.

7. as claim 1 or 6 described high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor, it is characterized in that the transactions requests that the partial decode device is sent in all communication stacks on the slave unit collision detection parts received communication ring, determine the priority of the transactions requests that a plurality of main equipments send to same slave unit according to the resolving strategy of circular priority, the priority of each communication node is specified in advance by operating system, but in a single day the communication node of obtaining the communication network control discharges taking of communication network, its priority becomes minimum, and priority rises inferior to its communication node priority; Slave unit collision detection parts are selected the transactions requests of the highest communication node of priority, and other will not be accepted to the access request that same slave unit sends; If N communication node arranged in the microprocessor, if main equipment to the communication of slave unit through the number of communication node smaller or equal to N/2, be clockwise communication, slave unit collision detection parts are issued clockwise resource allocation parts with transactions requests; Otherwise, if main equipment to the communication of slave unit through the number of communication node greater than N/2, be anticlockwise communication, slave unit collision detection parts are issued counterclockwise resource allocation parts with transactions requests.

8. as claim 1 or 6 described high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor, it is characterized in that clockwise resource allocation parts and counterclockwise resource allocation parts are parts that the channel resource on the clockwise or counterclockwise communication direction is distributed, their structure is identical; After clockwise the resource allocation parts receive the transactions requests that slave unit collision detection parts send, visit clockwise affairs registers group on the one hand, read the current transaction information that is in active state, i.e. the relevant information of affairs, as the master and slave device address of communicating by letter, state; The access resources recovery part obtains doing/not busy state of each communication node and passage on the one hand, to determine current resource operating position; According to transactions requests, current active transaction information and resource operating position, select the idle channel that can between the master-slave equipment of communication, form transmission path, thereby be that the communication of being asked generates channel configuration information, indicate the numbering of the passage of obtaining access rights, and channel configuration information issued first control assembly and second control assembly in all communication stacks, the transaction information with this road communication is updated to clockwise affairs registers group simultaneously; The resource allocation parts distribute the channel resource on the counterclockwise communication direction counterclockwise, and just its visit and renewal is counterclockwise affairs registers group.

9. as claim 1 or 6 described high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor, it is characterized in that clockwise affairs registers group and counterclockwise affairs register set stores transaction information, each free N/2 affairs register formed, and N is the number of communication node in the microprocessor; Each affairs register writes down the transaction information of a paths, transaction information is represented the relevant information that this paths is once communicated by letter, comprise sources traffic node address, destination communication node address and a significance bit, when significance bit is " 1 ", show this road communication well afoot, be active state; When significance bit was " 0 ", this road communication finished, and is non-active state; When new transactions requests, if be clockwise communication, clockwise the resource allocation parts upgrade the affairs register in the clockwise affairs registers group, sources traffic node address, destination communication node address and significance bit " 1 " when promptly writing this paths and carrying out new communication; If be anticlockwise communication, the resource allocation parts upgrade the affairs register in the counterclockwise affairs registers group counterclockwise.

10. as claim 1 or 6 described high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor, it is characterized in that the resource recovery part writes down the operating position of all communication nodes and passage on the one hand, be divided into " doing ", " spare time " two states; On the other hand according to the transaction retraction signal with clockwise affairs registers group or the counterclockwise affairs register significance bit reset in the affairs registers group; The resource recovery part is connected to first control assembly and second control assembly in all communication stacks, receives the transaction retraction signal that control assembly sends after communication is finished; If clockwise communication, the resource recovery part receives the transaction retraction signal of sending as second control assembly in the communication stack of the communication node connection of main equipment, with the active position of this road affairs register in the clockwise affairs registers group is " 0 ", the communication node that this road office takies in the resource recovery part and the state of passage are changed to " spare time " simultaneously, the expression resource finishes, and takies resource and is released; If be anticlockwise communication, the resource recovery part receives the transaction retraction signal of sending as first control assembly in the communication stack of the communication node connection of main equipment, with the active position of this road affairs register in the counterclockwise affairs registers group is " 0 ", the communication node that this road office takies in the resource recovery part and the state of passage are changed to " spare time " simultaneously, the expression resource finishes, and takies resource and is released; Occupation condition new in the communication network has just been arranged like this, the visit next time of funding source distribution member in the resource recovery part.

11. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 1, first switch block that it is characterized in that channel controller in passage and the communication stack in the communication loop links to each other with the second switch parts, and first control assembly of channel controller links to each other with first control assembly in request signal line, confirmation signal line and the communication stack; The number K of passage is relevant with the number N of communication node, and K is that N/4 round numbers and K can only be even number; Every paths all is the path of transfer of data, and the transmission direction between adjacent two passages is opposite; The request signal line transmits request signal according to Handshake Protocol between communication stack, the confirmation signal line between communication stack according to Handshake Protocol delivery confirmation signal, transmission by request signal between the communication stack and confirmation signal finish receiving whole handshake procedure.

12. high-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor as claimed in claim 5, it is characterized in that resource allocation parts, counterclockwise resource allocation parts homogeneous phase connect clockwise in first control assembly, second control assembly and the moderator, channel arrangement signal according to clockwise resource allocation parts or counterclockwise resource allocation parts in the direction reception moderator of communication are sent generates the channel allocation signal according to the channel arrangement signal and issues first switch block and second switch parts respectively:

12.1 if present node is as the main equipment of communication, and carry out be clockwise communication the time, communication process is undertaken by second control assembly and second switch parts, the channel arrangement signal that the clockwise resource allocation parts of the second control assembly selective reception are sent; If carry out be anticlockwise communication the time, communication process is undertaken by first control assembly and first switch block, the channel arrangement signal that the counterclockwise resource allocation parts of the first control assembly selective reception are sent; A clockwise communication process is: second control assembly becomes " 1 " to send out request signal to destination communication node with the level on the request signal line by " 0 ", when second control assembly detects level on the confirmation signal line and becomes " 1 " by " 0 ", show that destination communication node has received request signal and sent the affirmation signal that can communicate; At this moment, the channel arrangement signal that second control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues the second switch parts, the second switch parts passage that communication transmission path is required is opened, close other unwanted passage, communication node communicates along the transmission path that forms, and second control assembly becomes " 0 " with the level on the request signal line by " 1 " simultaneously; When second control assembly detects level on the confirmation signal line and becomes " 0 " by " 1 ", the sign off between the expression communication node; Anticlockwise communication process is undertaken by first control assembly and first switch block, and the channel arrangement signal that first control assembly is sent according to counterclockwise resource allocation parts generates the channel allocation signal and issues first switch block, and other is the same with clockwise communication process;

12.2 current communication node as communication slave unit the time, if carry out clockwise communication, communication process is undertaken by first control assembly and first switch block, the channel arrangement signal that the clockwise resource allocation parts of the first control assembly selective reception are sent; If what carry out is anticlockwise communication, communication process is undertaken by second control assembly and second switch parts, the channel arrangement signal that the counterclockwise resource allocation parts of the second control assembly selective reception are sent; A clockwise communication process is: when first control assembly detects level on the request signal line and becomes " 1 " by " 0 ", first control assembly becomes " 1 " with the level on the confirmation signal line by " 0 ", expression has received request signal, can communicate, and the channel arrangement signal that first control assembly is sent according to clockwise resource allocation parts generates the channel allocation signal and issues first switch block, first switch block passage that communication transmission path is required is opened, and closes other unwanted passage; The level that detects on the request signal line when first control assembly becomes " 0 " by " 1 ", and after communication finished, first control assembly became " 0 " with the level on the confirmation signal line by " 1 ", finishes handshake procedure, the expression sign off; Anticlockwise communication process is undertaken by second control assembly and second switch parts, and the channel arrangement signal that second control assembly is sent according to counterclockwise resource allocation parts generates the channel allocation signal and issues the second switch parts, and other is the same with clockwise communication process;

12.3 if current communication node is neither main equipment neither slave unit, and the communication stack that is attached thereto is during just as the intermediate node on the master-slave equipment communication path, if carry out clockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that clockwise resource allocation parts are sent; If carry out anticlockwise communication, first control assembly and second control assembly all receive the channel arrangement signal that counterclockwise resource allocation parts are sent; First control assembly and second control assembly generate the channel allocation signal and issue first switch block and second switch parts respectively, and two switch blocks select the required passage of communication transmission path to open respectively, close other unwanted passage; Simultaneously, the switching circuit closure on inside request signals line and the inside confirmation holding wire, first control assembly is communicated with the confirmation signal line with request signal line on second control assembly, request signal and confirmation signal between the transmission master-slave equipment;

12.4 after communication process was finished, if carry out clockwise communication, second control assembly in the communication stack that connects as the communication node of main equipment was sent out the transaction retraction signal to moderator; If carry out anticlockwise communication, first control assembly in the communication stack that connects as the communication node of main equipment is sent out the transaction retraction signal to moderator; Control assembly is sent out the transaction retraction signal to moderator, and the request moderator is cancelled current affairs and discharged resource, and whole communication process finishes.

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