CN100502082C - 存储单元器件及其制造方法 - Google Patents
存储单元器件及其制造方法 Download PDFInfo
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Abstract
一种包含有一可通过施加能量而在各电性状态之间切换的存储材料的存储单元器件,其包括一电极、一相对于一电极表面的分隔层、一位于此分隔层中的孔洞、一位于此孔洞中的第二材料其定义一带有一向下并向内渐缩的空隙区域的空隙。一存储材料位于此空隙区域中并电接触至此电极表面。一第二电极电接触至此存储材料。流经此第一及第二电极之间的能量集中于此存储材料中,以便于转换此存储材料的一电性状态。此存储材料可包括一相变材料。此第二材料可包括一以高密度等离子沉积的材料。本发明同时公开一种用以制造一存储单元器件的方法。
Description
【相关申请资料】
本发明要求2005年11月22日申请的美国临时专利申请No.60/738,924,代理人案号为MXIC1661-1的权益。
【技术领域】
本发明涉及基于存储材料的高密度存储元件,例如电阻随机存取存储器(RRAM),此存储材料可通过施加能量而在不同电气状态之间切换。此存储材料可为基于相变的存储材料,包括基于硫属化物的材料以及其他材料。本发明亦涉及制造这些元件的方法。
【背景技术】
基于相变的存储材料被广泛地运用于读写光盘中。这些材料包括有至少两种固态相,包括如一大部分为非晶态的固态相,以及一大体上为结晶态的固态相。激光脉冲用于读写光盘中,以在二种相中切换,并读取此种材料在相变之后的光学性质。
如硫属化物及类似材料的这些相变存储材料,可通过施加其幅度适用于集成电路中的电流,而致使晶相变。一般而言非晶态的特征是其电阻高于结晶态,此电阻值可轻易测量得到而用以作为指示。这种特性则引发使用可编程电阻材料以形成非挥发性存储器电路等兴趣,此电路可用于随机存取读写。
从非晶态转变至结晶态一般为一低电流步骤。从结晶态转变至非晶态(以下指称为重置(reset))一般为一高电流步骤,其包括一短暂的高电流密度脉冲以融化或破坏结晶结构,其后此相变材料会快速冷却,抑制相变的过程,使得至少部份相变结构得以维持在非晶态。理想状态下,致使相变材料从结晶态转变至非晶态的重置电流幅度应越低越好。欲降低重置所需的重置电流幅度,可通过减低在存储器中的相变材料元件的尺寸、以及减少电极与此相变材料的接触面积而达成,因此可针对此相变材料元件施加较小的绝对电流值而达成较高的电流密度。
此领域发展的一种方法是致力于在一集成电路结构上形成微小孔洞,并使用微量可编程的电阻材料填充这些微小孔洞。致力于这些微小孔洞的专利包括:于1997年11月11日公告的美国专利第5,687,112号”Multibit Single Cell Memory Element HavingTapered Contact”、发明人为0vshinky;于1998年8月4日公告的美国专利第5,789,277号”Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等;以及于2000年11月21日公告的美国专利第6,150,253号”Controllable OvonicPhase-Change Semiconductor Memory Device and Methods ofFabricating the Same”、发明人为Doan等。
在以非常小的尺度制造这些元件、以及欲满足大规模生产存储元件时所需求的严格制程变数时,则会遭遇到问题。期望提供一种有小尺寸以及低重置电流的存储单元结构,以及用以制造这些结构的方法。
【发明内容】
本发明的第一目的是提供一种存储单元器件,其包括一种可通过施加能量而在不同电性状态之间切换的存储材料。此存储单元器件包括一第一电极,其包括有一电极表面。一第一材料位于此电极表面上以生成一带有一上表面的分隔层。此第一材料界定一孔洞,此孔洞被此分隔层中的一侧壁、一底面、以及由上表面所定义的一平面所包围。一第二材料位于侧壁上且界定一空隙。此空隙在此上表面的平面下,包括有一向下且向内渐缩的空隙区域。一存储材料位于此空隙区域的至少一部分,且电接触至此电极表面。一第二电极电接触至此存储材料。流经此第一与第二电极之间的能量,集中在此存储材料中,以便于改变此存储材料的电性状态。在某些实施例中,此存储材料包括一相变材料。此第二材料可包括一以高密度等离子沉积的材料。
本发明的第二目的是提供一种用以制造一包括有可通过施加能量而在不同电性状态之间切换的存储材料的存储元件的方法。首先形成第一电极,此第一电极包括有一电极表面。接着一第一材料沉积于此电极表面上而生成一带有一上表面的分隔层。一孔洞形成且贯穿此分隔层。此孔洞被此分隔层中的一侧壁、一底面、以及由上表面所定义的一平面所包围。接着选择一沉积制程。以第二材料通过所选择的沉积制程而沉积于侧壁上。此选择步骤以及第二材料沉积步骤的进行,使得此第二材料界定一空隙。此空隙在此上表面的平面下,包括有一向下并向内渐缩的空隙区域。一存储材料沉积于此空隙区域的至少一部份,并且电接触至此电极表面。一第二电极形成并电连接至此存储材料。流经此第一与第二电极之间的能量,集中于此存储材料,以便于改变此存储材料的电性状态。在某些实施例中,此选择步骤包括,选择一高密度等离子化学气相沉积(HDP CVD)制程,且此沉积步骤包括使用此高密度等离子化学气相沉积制程而沉积此第二材料于侧壁上。
本文中所描述的用以形成一存储单元器件以及例如一RRAM元件的方法,可被用以制造用于其他器件中的微小相变门(gate)、连接桥、或类似结构。
以下详细说明本发明的结构与方法。本发明内容说明章节目的并非在于定义本发明。本发明由权利要求所定义。举凡本发明的实施例、特征、观点及优点等将可通过以下描述及附图获得充分了解。
【附图说明】
图1为一根据本发明所制造的存储单元器件的放大截面图;
图2—5图示用以制造如图1中的元件的方法;
图2示出在一第一电极上进行材料的沉积,以生成一分隔层于此第一电极之上,此分隔层中包括有一贯穿至第一电极的孔洞;
图3示出将一材料以高密度等离子化学气相沉积(HDP CVD)而沉积至分隔层之上以及图2的孔洞中的结果,此沉积制程生成了一空隙,该空隙在此孔洞内包括有一向下并向内渐缩的空隙区域;
图4示出针对图3中所沉积于此空隙区域的底面的材料进行蚀刻以到达第一电极的结果;以及
图5示出在图4中的空隙区域的底部沉积一存储材料的结果。
【主要元件符号说明】
10 存储单元器件
12 第一电极(下电极)
13 电极表面
14 分隔层
16 孔洞
18 底面
20 侧壁
22 平面
24 上表面
26 材料
28 空隙
30 第一空隙区域
32 第二空隙区域
34 存储材料
36 较低部分
38 第二电极(上电极)
42 金属层间介电材料层
44 蚀刻停止层
45,49 侧壁
48 较大开口面积
52 较小开口区域
【具体实施方式】
图1为根据本发明的一实施例所制造的存储单元器件10的截面放大图。元件10大致上包括一第一或下电极12其包括有一电极表面13,其上沉积有一分隔层14。一孔洞16形成且贯穿分隔层14至第一电极12。孔洞16由一底面18、一侧壁20、以及一由分隔层14的上表面24所界定的平面22所包围。一材料26沉积于上表面24、侧壁20、以及底面上,较佳地利用一高密度等离子化学气相沉积(HDPCVD)制程所进行。此可形成一空隙28,其在平面22之上包括有一向下并向内渐缩的第一空隙区域30,并在平面22之下包括有一向下并向内渐缩的第二空隙区域32。一存储材料34沉积在此第二空隙区域32的较低部分36、并接触至第一电极12。最后,一第二或上电极38形成在材料26之上,并接触至存储材料34。如图1中所示,电流40限缩于仅流经此存储材料的一相对小部分。
存储单元装置10及其制造方法将参照图2-5而进行详细叙述。请参见图2,分隔层14经沉积至第一电极12之上,且孔洞16通过分隔层14而经图形化(pattern),且孔洞的底面18显露出电极表面13。孔洞16较佳地包括有一直径约为200至50nm,典型地为约100nm。在本实施例中,分隔层14包括一由如二氧化硅等材料所形成的金属层间介电层42;其他材料如FSG/PSG/BPSG或一低介电系数电介质亦可被使用。金属层间介电材料层42较佳地包括有一厚度为约50至400nm,典型地为约200nm。一蚀刻停止层44施加至层42之上,以在后续制程步骤中保护层42。此蚀刻停止层44不仅用作为孔洞图形化的一介电抗反射层(DARC),亦可在HDP沉积程序中保护层42,因为HDP沉积不仅牵涉到沉积,同时包括了高密度等离子蚀刻。蚀刻停止层44在HDP高密度等离子蚀刻时保护了层42,以维持孔洞16的形状。在本实施例中,蚀刻层间止层44包括氮氧化硅;其他材料如氮化硅等,亦可被使用。蚀刻停止层的厚度较佳地介于10至50nm之间,典型地为约30nm。
图3显示了材料26经过HDP CVD而沉积至表面以及孔洞16中的结果。材料26典型地为氧化物,但亦可为一低K(低介电常数)的薄膜电介质。此在第一空隙区域30内具有向下并向内渐缩的侧壁45的特征,在第一空隙区域30的入口处界定了一较大开口面积48,而在第二空隙区域中的向下并向内渐缩的侧壁49,则在第二空隙区域较低部分36界定了一较小开口面积52。如图4中所示,在较低部分36中的材料26接着被蚀刻至可显露出电极12的电极表面13。在平面22的侧壁49的直径,较佳地介于15至5nm之间,典型地为约8nm。在电极表面13处的侧壁49的直径较佳地介于10至1nm之间,典型地为约3nm。
存储材料34接着被沉积至图4的结构之上,以完成图5中所示的结构。重要的是,必须最小化存储材料34的体积,以将电流40限缩于仅流经此材料的一相对小部分体积。使用HDP CVD以沉积材料26提供了向下并向内渐缩的侧壁45,49的特征,而有助于适当地沉积存储材料34于第二空隙区域32中。可采用例如沉积一薄膜于整个结构之上、并接着蚀刻至将除了第二空隙区域32中的较低部分36以外的薄膜移除等适当制程步骤,以减少存储材料34在图4中的结构上所沉积的体积。通过在压力5~50mT、功率约为1000W、且使用氮气或氩气的溅镀沉积,而可将此存储材料沉积。溅镀沉积的标的如下所述。若仅使用氩气,则标的可为GeSbTe。若使用氩气/氮气,则标的可为N2-GeSbTe。存储材料35在第一电极12的上的的厚度或高度,较佳为100至10nm,典型地为约30nm。一HDP的配方范例如下所示:SiH4:95sccm/Ar:390sccm/O2:150sccm/等离子温度~300℃/上电极功率3550W/下电极功率2700W。
本发明的一项优点在于,上述的整个制程可在不需要化学机械研磨的情形下完成;所产生的制程也因此而大幅简化。与已知的CVD制程相比较之下,使用HPD CVD可在孔洞16中提供较佳的填充效果。同时,此制程可应用于较小直径的孔洞16,也因此可产生较高的深宽比(aspect ratio)。本发明有利于制程微缩化,因此此制程在晶片的关键尺度缩小时亦应能适用。
在所述实施例中的电极12,38较佳由氮化钛(TiN)所制成。虽然其他如氮化钽(TaN)、氮化铝钛(TiAlN)、或氮化铝钽(TaAlN)等材料亦可使用于电极12,38中,然而TiN是较佳的,因为其可与作为存储材料34的GST(后续有详述)产生良好的附着、其是在半导体制造中常用的材料、且其可在GST型存储材料34转换时的高温下(典型为介于600-700℃之间)提供良好的扩散障碍(diffuseion barrier)。
存储单元器件10的实施例,包括基于相变的存储材料,包括用作为存储材料34的以硫属化物(chalcogenide)为基础的材料以及其他材料。硫属化物包括下列四元素的任一者:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫属化物包括将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。一硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多基于相变的存储材料已经被描述于技术文件中,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。此成分可以下列特征式表示:TeaGebSb100-(a+b)。
一位研究员描述了最有用的合金为,在沉积材料中所包含的平均碲浓度远低于70%,典型地低于60%,并在一般型态合金中的碲含量范围从最低23%至最高58%,且最佳介于48%至58%的碲含量。锗的浓度高出约5%,且其在材料中的平均范围从最低8%至最高30%,一般低于50%。最佳地,锗的浓度范围介于8%至40%。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比,其为所有组成元素加总为100%。(Ovshinky‘112专利,栏10~11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(NoboruYamada,”Potential of Ge-Sb-Te Phase-change Optical Disks forHigh-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成一相变合金其包括有可编程的电阻性质。可使用的存储材料的特殊范例,如Ovshinsky‘112专利中栏11-13所述,其范例在此列入参考。
相变合金可在一第一结构态与第二结构态之间切换,其中第一结构态指此材料大体上为非晶固相,而第二结构态指此材料大体上为结晶固相。这些合金至少为双稳定的(bistable)。此词汇“非晶”用以指称一相对较无次序的结构,其较之一单晶更无次序性,而带有可检测的特征如比结晶态更高的电阻值。此词汇“结晶”用以指称一相对较有次序的结构,其较之非晶态更有次序,因此包括有可检测的特征例如比非晶态更低的电阻值。典型地,相变材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特中包括,原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质亦可能随之改变。
相变合金可通过施加一电脉冲而从一种相态切换至另一相态。先前观察指出,一较短、较大幅度的脉冲倾向于将相变材料的相态改变成大体为非晶态。一较长、较低幅度的脉冲倾向于将相变材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量,够大因此足以破坏结晶结构的键结,同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下,可决定特别适用于一特定相变合金的适当脉冲量变曲线。在本文中所描述的一种适用于RRAM中的材料,为Ge2Sb2Te5,一般称为GST。亦可使用其他类型的相变材料。
本发明的叙述参考相变材料。然而,其他存储材料(有时亦被称为可编程材料)亦可被使用。如在本应用中所使用者,存储材料为其如电阻等电气性质可通过施加能量而改变者;此改变可为一阶段化改变或一连续性改变、或为二者的组合。其他可用于本发明的其他实施例中的可编程电阻存储材料包括:掺杂N2的GST、GexSby、或其他以不同结晶态转换来决定电阻的物质;PrxCayMnO3、PrSrMnO、ZrOx、或其他使用一电脉冲以改变电阻状态的物质;TCNQ(7,7,8,8-tetracyanoquinodimethane)、PCBM(methanofullerene6,6-phenyl C61-butyric acid methyl ester)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其他物质掺杂的TCNQ、或任何其他聚合物材料其包括有以一电脉冲而控制的双稳定或多稳定电阻态。可编程电阻存储材料的其他范例包括,GeSbTe、GeSb、NiO、Nb-SrTiO3、Ag-GeTe、PrCaMnO、ZnO、Nb2O5、Cr-SrTiO3。
下列为描述四种电阻存储材料的概要。
1.硫属化物材料
GexSbyTez
x:y:z=2:2:5
或其他成分,其x:0~5;y:0~5;z:0~10
以氮、硅、泰、或其他元素所掺杂的锗锑碲。
形成方法:以PVD溅镀或磁控管(Magnetron)溅镀方式,其反应气体为氩气、氮气、及/或氦气、压力为1mtorr至100mtorr。此沉积步骤一般于室温下进行。一深宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器亦是可行的。
以真空或氮气氛围进行沉积后退火处理在某些时候是必须的,以改良硫属化物的结晶态。此退火温度典型地介于100至400℃,且退火时间短于30分钟。
硫属化物材料的厚度视此单元结构的设定而定。一般而言,厚度为8nm以上的硫属化物材料可包括有一相变特征,使得此材料显现至少二稳定的电阻态。
2.CMR(colossal magnetoresistance,超巨磁阻)材料
PrxCayMnO3
x:y=0.5:0.5
或其他成分,其x:0~1;y:0~1
另一包括有锰氧化物的CMR材料亦可被使用
形成方法:以PVD溅镀或磁控管(Magnetron)溅镀方式,其反应气体为氩气、氮气、及/或氦气、压力为1mtorr至100mtorr。此沉积步骤的温度可介于室温至600℃之间,视沉积后处理条件而定。一深宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器亦是可行的。可施加一数十高斯至10,000高斯的磁场以改善磁结晶相。
以真空或氮气氛围进行沉积后退火处理在某些时候是必须的,以改良硫属化物的结晶态。此退火温度典型地介于100至400℃,且退火时间短于2小时。
CMR材料的厚度视此单元结构的设定而定。一般而言,厚度为10至200nm的CMR材料可被用作为核心材料。
一YBCO(YBaCuO3,一种高温超导材料)缓冲层经常被用来改良CMR材料的结晶态。此YBCO的沉积在CMR材料的沉积前。YBCO的厚度范围介于30nm至200nm。
3.2元素化合物
NiOy;TixOy;AlxOy;WxOy;ZnxOy;ZrxOy;CuxOy等
x:y=0.5:0.5
其他材料,其x:0~1;y:0~1
形成方法:
1.以PVD溅镀或磁控管(Magnetron)溅镀方式,其反应气体为氩气、氮气、及/或氦气、压力为1mtorr至100mtorr,其标的为一金属氧化物如NiOy;TixOy;AlxOy;WxOy;ZnxOy;ZrxOy;CuxOy等。此沉积步骤一般在室温下进行。一深宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。如有必要时,同时合并使用直流偏压以及准直器亦是可行的。
有时需要以真空或氮气氛围或混合氧气/氮气的氛围进行沉积后退火,以改良金属氧化物的氧原子分布。此退火温度典型地介于400至600℃,且退火时间短于2小时。
2.反应沉积:以PVD溅镀或磁控管(Magnetron)溅镀方式,其反应气体为氩气/氧气、氩气/氮气/氧气、纯氧、氦气/氧气、氦气/氮气/氧气等,压力为1mtorr至100mtorr,其标的为一金属氧化物如镍、钛、铝、钨、锌、铬、或铜等。此沉积步骤一般在室温下进行。一深宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。如有必要时,同时合并使用直流偏压以及准直器亦是可行的。
有时需要以真空或氮气氛围或混合氧气/氮气的氛围进行沉积后退火,以改良金属氧化物的氧原子分布。此退火温度典型地介于400至600℃,且退火时间短于2小时。
3.氧化反应:通过一高温氧化系统如一火炉或RTP系统而完成。此温度介于200至700℃,且用纯氧或氮气/氧气混合气体、压力为数mtorr至1大气压。其持续时间可介于数分钟至数小时。另一氧化方式为等离子氧化。其使用一RF或一DC源等离子与氧气或氩气/氧气混合气体或氩气/氮气/氧气混合气体在1mtorr至100mtorr,以氧化下列金属的表面,如镍、钛、铝、钨、锌、铬、或铜等。此氧化时间可介于数秒钟至数分钟的间。此氧化温度可介于室温至300℃之间,视等离子氧化的程度而定。
4.聚合物材料
掺杂有铜、C60、银等的TCNQ
PCBM-TCNQ混合聚合物
形成方法:
1.蒸发:通过热蒸发、电子束蒸发、或分子束磊晶系统(molecular beam epitaxy system,MBE)而达成。一固态TCNQ以及掺杂物丸在一单反应室中共蒸发。此固态TCNQ以及掺杂物丸置于一钨船或钽船或一陶瓷船中。施加一大电流或一电子束以融化来源材料,使得这些材料经混合而沉积于晶片上。其中并无反应性化学物质或气体。此沉积步骤于压力为10-4torr至10-10torr下进行。此晶片温度介于室温至200℃之间。
有时需要以真空或氮气氛围进行沉积后退火处理,以改善聚合物材料的成分分布。此退火温度可介于室温至300℃之间,且退火时间少于1小时。
2.旋转涂布:通过一旋转涂布机与经掺杂的TCNQ溶液于低于1000rpm的转速下进行。在旋转涂布后,静置此晶片以在室温下或低于200℃的温度下等待固态生成。这些等待时间可介于数分钟至数日之间,视温度以及生成条件而定。
关于相变随机存取存储装置的制造、元件材料、使用与操作的额外信息,请参见美国专利申请No.11/155,067,发明名称为“Thin FilmFuse Phase Change RAM and Manufacturing Method”,申请日为2005年6月17日,代理人案号为MXIC 1621-1。
上述叙述中可能使用了如上、下、顶、底、之上、之下等词汇。这些词汇用以帮助了解本发明,而非用以限制本发明的范畴。
虽然本发明已参照较佳实施例来加以描述,将为本领域的技术人员所了解的是,本发明并未受限于其详细描述内容。替换方式及修改样式已于先前描述中所建议,并且其他替换方式及修改样式将为本领域的熟练技术人员所易于想到。特别是,根据本发明的结构与方法,所有具有实质上相同于本发明的构件结合而达成与本发明实质上相同结果者皆不脱离本发明的精神范畴。因此,所有这些替换方式及修改样式意欲落在本发明在随附权利要求及其等同物所界定的范畴中。
任何在前文中提及的专利申请以及印刷文本,均列为本案的参考。
Claims (22)
1、一种存储单元器件,其包括一可通过施加能量而在各电性状态间切换存储材料,该存储单元器件包括:
第一电极,具有一电极表面;
第一材料,位于该电极表面之上,以产生带有一上表面的一分隔层;
该第一材料界定一孔洞,该孔洞被该分隔层中的一侧壁、一底面、以及由该上表面所定义的一平面所包围;
第二材料,位于该侧壁上;
该第二材料界定一空隙,该空隙在该上表面的该平面之下包含有一向下并向内渐缩的空隙区域;
存储材料,位于该空隙区域中至少一部分,且其电接触至该电极表面;以及
第二电极,电接触至该存储材料;
其中流经该第一与第二电极之间的能量集中于该存储材料中,以便于改变该存储材料的电性状态。
2、根据权利要求1所述的存储单元器件,其中该存储材料包括一相变材料。
3、根据权利要求1所述的存储单元器件,其中该第二材料包括一以高密度等离子沉积的材料。
4、根据权利要求1所述的存储单元器件,其中该第二材料位于该分隔层的上表面。
5、根据权利要求4所述的存储单元器件,其中由该第二材料所界定的该空隙,在该上表面的该平面之上包括另一向下并向内渐缩的空隙区域。
6、根据权利要求1所述的存储单元器件,其中该第一材料包括在该上表面的一金属层间介电材料以及一停止层。
7、根据权利要求1所述的存储单元器件,其中该第二材料包括一氧化物。
8、根据权利要求1所述的存储单元器件,其中当该存储材料的电性改变时,该存储材料的电阻值亦改变。
9、根据权利要求1所述的存储单元器件,其中:
该空隙区域包含一上部分以及一下部分,该存储材料位于该空隙区域的该下部分中;以及
该第二电极位于该第二材料之上,且位于该空隙区域的该上部分中并与该存储材料直接接触。
10、根据权利要求1所述的存储单元器件,其中该底面位于或高于该电极表面。
11、一种存储单元器件,其包括一可通过施加能量而在大体非晶态与大体结晶态等二态中切换的相变材料,该存储单元器件包括:
第一电极,具有一电极表面;
第一材料,位于该电极表面之上,以产生带有一上表面的一分隔层;
该第一材料界定一孔洞,该孔洞被该分隔层中的一侧壁、一底面、以及由该上表面所定义的一平面所包围;
以高密度等离子沉积的第二材料,位于该侧壁上以及位于该分隔层的该上表面上;
该第二材料界定一空隙,该空隙在该上表面的该平面之上包含有一向下并向内渐缩的第一空隙区域,该空隙在该上表面的该平面之下包含有一向下并向内渐缩的第二空隙区域,该第二空隙区域包含一上部分以及一下部分;
一相变材料,位于该第二空隙区域的该下部分,且其直接电接触至该电极表面;以及
一第二电极,位于该第二材料之上、且位于该第二空隙区域的该上部分并直接接触至该相变材料;
其中流经该第一与第二电极之间的能量集中于该电极表面的该相变材料中,以便于改变该相变材料的电性状态。
12、一种用以制造一存储单元器件的方法,该器件包括一可通过施加能量而在各电性状态间切换的存储材料,该方法包括:
形成具有一电极表面的第一电极;
沉积第一材料在该电极表面之上,以产生包含有一上表面的分隔层;
形成一孔洞,其贯穿该分隔层,该孔洞被该分隔层中的一侧壁、一底面、以及由该上表面所定义的一平面所包围;
选择一沉积制程;
沉积第二材料在该侧壁上,其利用该所选择的沉积制程而进行;
该选择步骤以及该第二材料沉积步骤的进行,使得该第二材料界定一空隙,该空隙在该上表面的该平面之下包含有一向下并向内渐缩的空隙区域;
沉积一存储材料在该空隙区域的至少一部分,且其电接触至该电极表面;以及
形成第二电极,其电接触至该存储材料;
其中流经该第一与第二电极之间的能量集中于该存储材料中,以便于改变该存储材料的一电性状态。
13、根据权利要求12所述的方法,其中该孔洞形成步骤用以在该电极表面形成该孔洞。
14、根据权利要求12所述的方法,其中:
该选择步骤包括选择一高密度等离子化学气相沉积(HDPCVD)制程;以及
该第二材料沉积步骤包括利用所选择的该高密度等离子化学气相沉积制程,而沉积该第二材料在该侧壁上。
15、根据权利要求12所述的方法,其中该第二材料沉积步骤用以使该第二材料位于该孔洞的底面以及该电极表面间。
16、根据权利要求15所述的方法,其中该存储材料沉积步骤包括:在该孔洞的底面形成一贯穿该第二材料的开口,以显露出该电极表面。
17、根据权利要求12所述的方法,其中该存储材料沉积步骤利用一相变材料作为该存储材料而进行。
18、根据权利要求12所述的方法,其中该第二材料沉积步骤沉积该第二材料在该分隔层的该上表面,且其中该选择步骤以及第二材料沉积步骤,用以使得该孔洞在该上表面的该平面之上包括有另一向下及向内渐缩的孔洞区域。
19、根据权利要求12所述的方法,其中该孔洞形成步骤、该选择步骤、该第二材料沉积步骤、以及该存储材料沉积步骤,均不使用化学机械研磨步骤。
20、根据权利要求12所述的方法,其中该第一材料沉积步骤通过在该金属层间介电材料层之上沉积一金属层间介电材料层以及一停止层而进行,该停止层包括该上表面。
21、一种用以制造一存储单元器件的方法,该器件包括一可通过施加能量而在大体非晶态与大体结晶态等二态中切换的相变材料,该方法包括:
形成具有一电极表面的第一电极;
沉积第一材料在该电极表面之上、以形成包含有一上表面的分隔层;
形成一孔洞,其贯穿该分隔层,该孔洞被该分隔层中的一侧壁、一底面、以及由该上表面所定义的一平面所包围;
选择一高密度等离子化学气相沉积(HDP CVD)制程;
沉积一第二材料在该上表面以及该侧壁上,其利用该所选择的高密度化学气相沉积制程而进行;
该选择步骤以及该第二材料沉积步骤的进行,使得该第二材料界定一空隙,该空隙在该上表面的该平面之上包含有一向下并向内渐缩的第一空隙区域、且在该上表面的该平面之下包含有一向下并向内渐缩的第二空隙区域;
沉积一相变材料在该第二空隙区域的至少一部分,且其电接触至该电极表面;以及
形成一第二电极,其电接触至该相变材料;
其中流经该第一与第二电极之间的能量集中于该相变材料中,以便于改变该相变材料的一电性状态。
22、根据权利要求21所述的方法,其中该孔洞形成步骤、该高密度等离子化学气相沉积制程选择步骤、该第二材料沉积步骤、该相变材料沉积步骤、以及该第二电极形成步骤,均不使用一化学机械研磨步骤而进行。
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Cited By (2)
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CN104766925A (zh) * | 2014-01-07 | 2015-07-08 | 台湾积体电路制造股份有限公司 | 通过在HK HfO之前沉积Ti覆盖层改善RRAM的数据保持 |
CN104766925B (zh) * | 2014-01-07 | 2018-04-20 | 台湾积体电路制造股份有限公司 | 通过在HK HfO之前沉积Ti覆盖层改善RRAM的数据保持 |
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US20070117315A1 (en) | 2007-05-24 |
TWI323937B (en) | 2010-04-21 |
CN1971963A (zh) | 2007-05-30 |
TW200721458A (en) | 2007-06-01 |
US7599217B2 (en) | 2009-10-06 |
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