CN100517673C - 倒装芯片半导体器件的焊料凸块结构及其制造方法 - Google Patents

倒装芯片半导体器件的焊料凸块结构及其制造方法 Download PDF

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CN100517673C
CN100517673C CNB2006101519001A CN200610151900A CN100517673C CN 100517673 C CN100517673 C CN 100517673C CN B2006101519001 A CNB2006101519001 A CN B2006101519001A CN 200610151900 A CN200610151900 A CN 200610151900A CN 100517673 C CN100517673 C CN 100517673C
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CN1953166A (zh
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马克·A.·巴克曼
唐纳德·S.·比廷
塞勒西·奇逖皮迪
康承赫
塞勒西·M·莫扎特
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Avago Technologies International Sales Pte Ltd
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Agere Systems LLC
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Abstract

在一方面，本发明提供了一种半导体器件，此半导体器件包括位于半导体衬底上的互连。钝化层位于互连层上，并且其中形成有焊料凸块支持窗口。包含导电材料的支持小柱位于焊料凸块支持窗口内。

Description

倒装芯片半导体器件的焊料凸块结构及其制造方法
技术领域
本发明一般涉及到半导体器件，更确切地说是涉及到具有倒装芯片用途的改进了的焊料凸块结构的半导体器件。
背景技术
多年来，倒装芯片技术已经被微电子工业用来将半导体器件固定到衬底。在此技术中，器件具有“隆起的”焊料凸块，此焊料凸块可回流到衬底上相似的凸块”。当二者在回流炉中彼此相接触时，在器件和衬底二者上焊料能够被熔化。
虽然此方法为各种较老式的技术工作得很好，但此工业正在接近常规倒装芯片凸块制造方案不适应于当前器件的时刻。典型地由氮化钽/镍-钒/铜组成的凸块下方金属化(UBM)以及组成膜叠层的可靠性是成问题的，在这方面，最普遍出现的是机械和电学失效。与焊料的厚度典型地为50-100微米相比，UBM典型地由2个或3个总厚度小于1.5-2微米的膜组成。除非此UBM/芯片/衬底的键合在机械上和冶金上完好无缺，否则就会在UBM内出现破裂和剥离，导致不良的器件可靠性。
而且，在微电子工业中强调从器件和制造工艺消除铅基焊料，并在形成用来将集成电路(IC)芯片电学上固定到工作衬底的焊料凸块中开始采用无铅材料。
为了解决这一问题，工业界目前转向了铜柱技术。在这种技术中，钝化层被淀积在最上部的铜互连层上。窗口被形成在钝化层中，以便暴露下方的互连层，且势垒层被淀积在其中，随之以淀积铜引晶层。然后，光抗蚀剂被淀积和图形化，并被腐蚀，以便在光抗蚀剂中形成窗口，来暴露位于形成在钝化层中的窗口内的下方势垒层。铜被淀积到窗口中，以便部分地填充窗口。选自锡基或银-铜-锡基材料的无铅焊料，被淀积到窗口的其余部分中。清除光抗蚀剂，就得到一种位于其中并填充钝化层内窗口的单柱结构。
虽然此器件对于目前的技术是可接受的，但关切的是这种结构随着尺寸的缩小不会具有足够的机械稳定性。此关切的理由是，在这些结构中，仅仅存在着小面积的焊料可用于连接。考虑到此，无论采用铅焊料或是采用无铅焊料，连结都可能失效。而且，由于键合面积局限于仅仅小柱的顶部区，故若在装配工艺中出现稍许的不对准，就可能产生诸如电学上开路的问题。
因此，本技术所需要的是一种解决与上述常规结构相关的冶金问题和机械稳定性问题的焊料凸块结构。
发明内容
为了解决现有技术的上述不足，本发明在一个实施方案中提供了一种半导体器件，此半导体器件包含位于半导体衬底上的互连层。钝化层位于互连层上，且其中形成在焊料凸块支持窗口。包含导电材料的这些支柱位于焊料凸块支持窗口内。
上面已经概述了本发明的一个实施方案，使本技术领域的熟练人员可以更好地理解下列对本发明的详细描述。以下将描述本发明的其它实施方案和特点，它们构成了本发明各权利要求的内容。本技术领域的熟练人员应该理解的是，能够容易地使用所公开的概念和具体的实施方案作为设计或修正实施本发明相同目的的其它结构。本技术领域的熟练人员还应该理解的是，这些等效的结构不偏离本发明的构思与范围。
附图说明
为了更完整地理解本发明，下面结合附图来进行描述。
图1示出了一种IC的局部图，此IC包括本发明提供的一种焊料凸块结构的一个实施方案；
图2A-2E示出了本发明提供的一种焊料凸块的一个实施方案在制造的各个阶段的局部图；
图3A-3B示出了本发明提供的一种焊料凸块的另一实施方案在不同制造方法的各个阶段的局部图；
图4A-4D示出了本发明提供的一种焊料凸块的另一实施方案在不同制造方法的各个阶段的局部图；
图5A-5C示出了本发明提供的一种焊料凸块的另一实施方案在不同制造方法的各个阶段的局部图；
图6A-6E示出了本发明提供的一种焊料凸块的另一实施方案在不同制造方法的各个阶段的局部图。
具体实施方式
首先参照图1，示出了本发明提供的半导体器件100的一个实施方案。本发明提供的这些结构特别适用于半导体制造工业为其迅速转向的倒装芯片技术。在将芯片焊接到衬底或彼此之间焊接的过程中，倒装芯片技术提供了更大的方便。此外，倒装芯片技术的成本效率更高。在所示实施方案中，半导体器件100可以包括IC 105，其局部图被一般地示出了。由于IC 105可以是常规设计的，故无须详细地讨论其制作。而且，IC 105不局限于任何特殊的器件类型或设计。例如可以是光电子器件或电机械器件。
部分IC 105被电连接到焊料凸块结构110。焊料凸块结构110仅仅是本发明覆盖的一个实施方案。下面来讨论其它非限制的实施方案。电连接未被示出，但本技术领域的熟练人员可以理解器件如何被电连接。焊料凸块结构110位于形成在介质层120中的互连115上。互连115可以是常规设计的，诸如镶嵌或双重镶嵌互连结构。虽然互连结构115通常是位于半导体器件100最上层上的最终金属化层，但也可以位于最终层下方。
钝化层122位于介质层120和部分互连115上。如此处所用的那样，层可以是单层，或可以包含多个层的叠层。钝化层122可以是常规设计的，其中可以如所示由多个层的叠层组成。虽然所示的实施方案示出了直接位于介质层120上的钝化层122，但在其它实施方案中，也可以是位于二个层之间的插入层。
支持小柱124位于窗口125中，窗口125位于钝化层122二个部分之间。如下面所述，借助于清除部分钝化层122，或者，借助于形成二个分隔的钝化层122部分，可以形成窗口125。支持小柱124可以包括诸如图1所示实施方案那样的可选势垒层124a，或不包括势垒层124a。在图1所示的实施方案中，支持小柱124提供了对UBM 126的结构支持，UBM 126又提供了对焊料凸块28的支持。焊料凸块128可以是铅基或无铅的，诸如包含锡、铜、或银的，或者它们的组合。在本实施方案中，部分UBM 126位于各支持小柱124之间，并填充窗口125。随着器件总尺寸的不断缩小，位于窗口125中的多个支持小柱124能够提供相对于单个小柱结构得到了改善的支持。而且，能够使用的材料解决了国际工业界向基本上无铅系统转移的关切，同时提供了对焊料凸块128的必要程度的可连接性和结构支持。下面来说明本发明所覆盖的其它实施方案的例子。
图2A-2E示出了本发明提供的半导体器件200的一个实施方案在制造的各个阶段的局部图。这些图被局限于半导体器件200的上部。在图2A中，互连210被形成在介质层212中。互连层210可以是常规设计的，并可以包含诸如铜或铝之类的常规材料。而且，互连结构210可以是镶嵌或双重镶嵌结构。在所示的实施方案中，互连210可以是用来将半导体器件200连接到其它器件的最终金属化层。也可以由常规材料组成的介质层212，被示为半导体器件200的最终介质层或最上层。但互连结构210不一定要被形成在最终层；在某些实施方案中，可以位于最终介质层下方。
钝化层214位于介质层212上。常规的工艺和材料可以被用来制作钝化层214。例如，钝化层214可以由常规工艺淀积的氮化硅/二氧化硅/氮化硅的叠层或其组合组成。窗口216被形成在钝化层214中。在一个实施方案中，钝化层214被常规地图形化，以便在其中形成窗口216。窗口216可以是如所示的单个连续的窗口，或在其它的实施方案中，可以如下所述被分段。在另一实施方案中，以在二个面对的钝化层214之间提供了支持小柱224位于其中的窗口216或空间的方式，来形成钝化层214。
在钝化层214中形成窗口216之后，如所示，牺牲层218被淀积在钝化层214上和窗口216内。牺牲层218可以由常规材料组成，诸如用甩涂工艺或化学气相淀积(CVD)工艺之类的常规技术所淀积的甩涂玻璃、氧化物、氮化物、二氧化硅、或它们的组合之类。
在图2B中，牺牲层218被图形化，以便在窗口216内形成区段218a。诸如光刻和随后的腐蚀工艺之类的常规工艺，可以被用来形成区段218a。此图形化工艺暴露了下方的互连210。还应该指出的是，部分牺牲层218保留在窗口216的侧壁上，并用作后续形成的支持小柱的位置修正。
在适当的清洗步骤之后，如所示，可选的势垒层220被淀积在牺牲层218和区段218a上以及窗口中。势垒层220可以由诸如钽/氮化钽(Ta/TaN)、钛/氮化钛(Ti/TiN)、或它们的组合之类的常规材料组成，并可以用诸如物理气相淀积(PVD)或CVD工艺来淀积。势垒层220促进了后续淀积的各种材料的粘合，还阻止了不同材料之间的扩散。
诸如铝之类的导电材料被淀积在势垒层220上、各区段218a之间、以及窗口216内。常规的淀积工艺可以被用来达到这一步骤。
常规的化学/机械整平(CMP)工艺可以被用来清除过量的导电材料以及位于区段218a顶部上的势垒层220部分，以便得到图2C所示的结构。在CMP工艺之后，进行常规的腐蚀，以便清除位于钝化层214上以及窗口216内的牺牲层218。这导致在窗口216内形成分立的支持小柱224，图2D示出了这情况。如上所述，在包括势垒层220的那些实施方案中，势垒层220可以被考虑来形成部分支持小柱224。应该指出的是，支持小柱224不局限于任何特殊的几何形状或图形。例如，各支持小柱224可以组成类格栅图形或其它图形的沟槽结构，或可以如所示实施方案所表示的那样。由于位于窗口216侧壁上的牺牲层的存在，故邻近窗口216侧壁的端部支持小柱224就偏离于侧壁。
图2E示出了诸如钛、镍/钒-铜、或铜/铬之类的金属被满铺淀积在钝化层214上以及各支持小柱224之间后的图2D的半导体器件200。然后对金属进行图形化，并在一个实施方案中可以进行湿法腐蚀，以便形成UBM结构226。然后如所示，可以在UBM结构226上淀积焊料凸块228，此焊料凸块228可以由无铅材料组成。常规的工艺也可以被用来完成这些步骤。
在构成UBM结构226的金属的腐蚀过程中，支持小柱224被金属保护，并且支持小柱224由于被势垒层220保护而防止了被湿法腐蚀钻蚀，在现有技术中做不到这种情况。
支持小柱224提供了相对于常规焊料凸块结构得到了改善的结构支持。而且，利用位于各支持小柱24之间UBM结构226，此二种情况的组合提供了相对于现有技术所提供的额外的结构支持，并提供了能够被用于无铅焊料的材料系统。而且，此结构增大了表面积并提供了焊料凸块228更大的结构支持和更好的机械锚定。
本实施方案提供的另一好处在于，在支持小柱224包含铝的各实施方案中，UBM结构226包封着铝支持小柱，从而防止了氧化。于是能够防止或显著地降低现有技术工艺中发生的铝氧化。由于氧化物会降低各材料之间的冶金学键合从而降低机械稳定性，故氧化是不可取的。此外，许多现有技术工艺要求二个钝化层，一个在铜的顶部上，一个保护铝衬垫。利用本实施方案，由于UBM结构226被图形化，故所需要的仅仅是一次晶片钝化，这导致成本降低、工艺步骤减少、以及成品率改善。
图3A示出了本发明提供的另一半导体器件300的实施方案。此结构可以相同于图2A-2F所示实施方案所述的结构。因此，相似的参考号被用来表示相应的结构。图3A示出了已经以相同于图2A-2D所述方式制作了支持小柱324的制造步骤中的半导体器件300。但在本实施方案中，用来形成支持小柱324的金属是具有势垒层320的铜，此势垒层320包含Ta/TaN、Ti/TiN、或它们的组合。在淀积铜之后，本技术领域熟练人员所知的CMP技术可以被用来清除过量的铜，从而如其它实施方案所述对其进行整平。然后清除牺牲层。
也可以是最终钝化层的第二钝化层326，被常规地淀积在钝化层314上以及各支持小柱324上和各支持小柱324之间。然后可以用常规工艺来清除位于各支持小柱324上的第二钝化层326部分。此处的例外是，第二钝化层326以留下位于窗口316侧面与端部支持小柱324侧面之间的部分的方式而被图形化。这就包封了端部支持小柱的侧面，从而防止了它们受到氧化和后续腐蚀工艺的影响。
在对第二钝化层326进行图形化之后，如图3B所示，金属层被淀积并图形化，以便形成UBM 328。此处也可以采用前述实施方案中所用的相同的工艺和材料。UBM 328重叠着第二钝化层326，且位于各支持小柱324之间。然后，焊料凸块330可以如其它实施方案那样被淀积到UBM 328上。
如前述实施方案那样，支持小柱324提供了相对于常规结构改进了的支持。但当与UBM 328组合时，与支持小柱324相关的结构优点被进一步增强。而且，此结构增大了表面积，并提供了焊料凸块330更大的结构支持以及更好的机械锚定。
图4A-4D示出了本发明提供的另一半导体器件400的实施方案。除了势垒层320被省略之外，此结构可以相同于图3A-3B所示实施方案所述的结构。因此，相似的参考号被用来表示相应的结构。利用用来得到图3A所示结构的相同的工艺，可以得到图4A。亦即，铜支持小柱424被形成在窗口416内。第一牺牲层被淀积在钝化层414上，并被图形化。然后，诸如铜的金属被淀积在图形内，且牺牲层被清除。此铜被直接淀积在互连410上，而不插入势垒层。但本实施方案不排斥使用势垒层。也可以是最终钝化层的第二钝化层426，然后被淀积和图形化，使部分第二钝化层426保留在窗口416侧面与端部支持小柱422之间。
如在图4B中可见，势垒层428然后被淀积在第二钝化层426上以及各支持小柱424上和各支持小柱424之间。可以用常规的淀积工艺来淀积势垒层428，且势垒层428可以包含诸如Ta/TaN、Ti/TiN、或它们的组合之类的材料。
在图4C中，在淀积势垒层428之后，如所示，不同于包含支持小柱424的金属层430，被满铺淀积在半导体器件400上，并被图形化。在一个实施方案中，此金属包含铝。铝的使用带来对焊料凸块结构的一定程度的亲合性，因而对某些厂家更为可取。但本发明不局限于使用铝。诸如金、银、或铜之类的其它导电金属也可以使用。在使用铝的那些实施方案中，势垒层428防止了铝与铜之间的扩散。在金属层430可以包含铜或不容易与铜相互扩散的金属的其它实施方案中，可以省略势垒层428。
然后对金属层430进行腐蚀。金属层430重叠到第二钝化层426上，并完全包封了支持小柱424。在一个变通实施方案中，可以用CMP工艺清除金属层430。在这种实施方案中，与图4C所示被抬高相反，金属层430可能与第二钝化层426基本上齐平。
现在参照图4D，在完成金属层430的腐蚀之后，进行适当的清洗步骤，且UBM 432被形成在金属层430上。可以如上所述来制作此UBM 432。UBM 432包封着金属层430，从而防止其在形成UBM 432的过程中被钻蚀，并防止其被氧化。在完成UBM 432之后，焊料凸块434可以被淀积到UBM 432上。可以采用常规的工艺，且焊料可以是无铅焊料。图4E所示得到的结构提供了相同于上述各实施方案的结构和材料优点。
图5A-5C示出了本发明提供的另一半导体器件500的实施方案。除非另有说明，应该理解的是，用来制作相似于前述各实施方案的各组成部分的工艺和材料都可以是相似的或相同的。本实施方案的目的是形成一种不包括前述各实施方案那样的UBM的结构上优良的焊料结构。尽管如此，本特殊实施方案还是提供了相同于上述其它实施方案相关的结构和材料优点。此外，本实施方案还非常适用于包括层叠芯片的倒装芯片应用。
在图5A中，互连510位于介质层512中，且钝化层514位于介质层512上。在本实施方案中，钝化层514利用光抗蚀剂被图形化，并被腐蚀，以便在暴露下方互连510的窗口516内形成各个区段514a。常规的光刻工艺可以被用来对钝化层514进行图形化。可选的势垒层518可以被淀积在钝化层514上。势垒层518可以由Ti、TiN、Ta、TaN、Ni、Cr等组成。诸如PVD或CVD之类的常规工艺可以被用来淀积势垒层518。势垒层518的淀积之后随之以金属层520的淀积。
在一个有利的实施方案中，金属层520是金，但也可以采用诸如银和铂之类的其它贵金属。当金被选择作为此金属时，可以首先在势垒层518上淀积金的引晶层，随之以电镀金以填充位于各区段514a之间的窗口，以便得到图5A所示的结构。在形成金属层520之后，对图5A的半导体器件500执行CMP工艺，以便清除金属层520和势垒层518的过量部分，从而得到图5A所示的结构。
光抗蚀剂层522被淀积在金属层520上，并被图形化，以便得到图5B所示的结构。用来形成光抗蚀剂层522的工艺和材料都可以是常规的。以光抗蚀剂中的窗口522a基本上对应于或基本上对准于分区段的金属层520的方式，来对光抗蚀剂层522进行图形化。在光刻工艺变化的情况下，应该理解的是，各窗口522a相对于其下方相应区段金属层520的对准可以偏离一个可接受的量。
例如用电镀方法，金属层520的合金已经被常规地满铺淀积，并被整平以形成延伸区524。在一个金属层520是金的实施方案中，此合金可以包含例如金/锡(Au/Sn)、金/锗(Au/Ge)、或金/硅(Au/Si)。在这种实施方案中，Au/Sn的组分中Sn可以包含大约合金的28％重量比，且熔点约为280℃，而Au/Ge的组分中Ge可以包含大约合金的12％重量比，且熔点约为356℃。在合金是Au/Si的实施方案中，Si可以包含大约合金的6％重量比，且熔点约为370℃。在对用来形成延伸区524的合金进行整平之后，清除光抗蚀剂层522，以便得到图5C所示的结构，此结构包括延伸区524位于其上的支持小柱526。
延伸区524提供了对键合到衬底有用的一些特点。图5C所示的实施方案可用于具有非常小的形状指标的装置，例如表面积非常有限的用于手持装置或移动装置的那些装置。而且，金的合金在低温下熔化，从而容易装配到衬底上，并且是非常好的热导体和电导体。金还非常有用于要求良好导电性和导热性的装置，例如在其中要求大电流通过支持小柱526的高电压装置中。钝化层514用作其中可以不通过电流的介质。在本实施方案中，不需要额外的步骤来进行额外的钝化。此外，由于金被电镀到金上，故不需要UBM。
在某些方面相似于图5A-5C所示实施方案的另一实施方案，被示于图6A-6E。在图6A中，互连610位于介质层612中，且钝化层614位于介质层612上。牺牲层615利用光抗蚀剂被图形化，并被腐蚀，以便在暴露下方互连610的窗口616内形成各个区段614a。常规的光刻工艺可以被用来对牺牲层615进行图形化。然后，可选的势垒层618可以被淀积在牺牲层615上。势垒层618可以是与用于图5A-C所述实施方案相同的类型。势垒层618的淀积之后随之以金属层620的淀积。
在一个有利的实施方案中，金属层520是金，但也可以采用诸如银和铂之类的其它贵金属。当金被选择作为此金属时，可以首先在势垒层618上淀积金的引晶层，随之以电镀金以填充位于各区段614a之间的窗口。在形成金属层620之后，对半导体器件600执行CMP工艺，以便清除金属层620和势垒层618的过量部分，从而得到图6A所示的结构。
光抗蚀剂层622被淀积在金属层620上，并被图形化，以便得到图6B所示的结构。用来形成光抗蚀剂层622的工艺和材料都可以是常规的。以光抗蚀剂中的窗口622a基本上对应于或基本上对准于分区段的金属层620的方式，来对光抗蚀剂层622进行图形化。在光刻工艺变化的情况下，应该理解的是，各窗口622a相对于其下方相应区段金属层620的对准可以偏离一个可接受的量。
在图6C中，例如用电镀方法，金属层620的合金已经被常规地满铺淀积，并被整平，以便在光抗蚀剂622内形成延伸区624。在一个金属层620是金的实施方案中，此合金可以包含与图5A-5C所述相同类型的材料。在对用来形成延伸区624的合金进行整平之后，清除光抗蚀剂层622，以便得到图6C所示的结构。
牺牲层615也被清除，形成图6D所示具有位于其上的延伸区624的支持小柱626。如在图6D可见，具有延伸区624的支持小柱626恰当地延伸在钝化层614上方。若要求更好的机械稳定性或各耦合器件之间更大的距离，则这种结构特别有利。于是，当希望将二个倒装芯片630和635(各具有图6D所示的相同结构)如图6E那样键合到一起时，图6D所示的半导体器件就特别有用。各器件被回流，且各芯片上的延伸区624熔化并彼此键合，从而在二个器件之间提供电连接。
利用继续参照图6E，示出了IC倒装芯片640和645的局部图，此局部图包含被电连接到下方晶体管结构660和665的焊料凸块结构650和655。当然，应该理解的是，焊料凸块结构650和655能够被形成在倒装芯片各自的一侧上，使器件能够被层叠。还应该理解的是，焊料凸块结构的前述任何一个实施方案都可以被用来代替所示的实施方案。然后利用“非满填充”或相似的化合物来填充器件640与645之间的间隙，来完成最终结构的装配件。本技术领域的熟练人员还可以理解的是，IC倒装芯片640可以被固定到柔性衬底或另一包含相似装配特点的衬底。
虽然已经详细地描述了本发明，但本技术领域的熟练人员应该理解的是，能够在其中作出各种改变、替换、以及变通而不在其最广阔的形式内偏离本发明的构思与范围。

Claims (10)

1.一种半导体器件，包括：
互连层，此互连层位于半导体衬底上；
钝化层，此钝化层位于互连层上，并且其中形成有焊料凸块支持窗口；以及
支持小柱，此支持小柱位于焊料凸块支持窗口内，此支持小柱包含导电材料；
凸块下方金属层，即UBM层，位于所述支持小柱上，用于支持焊料凸块，并且其中，UBM层的部分位于所述支持小柱之间，并且被所述支持小柱支持。
2.如权利要求1所述的半导体器件，其中，UBM层的剩余部分还被所述钝化层支持。
3.如权利要求1所述的半导体器件，其中，所述钝化层是晶片钝化层，且还包含位于晶片钝化层上的最终钝化层，并且最终钝化层的部分位于窗口内，并且其中，UBM层的部分位于最终钝化层上面。
4.如权利要求1所述的半导体器件，还包括：
多个支持小柱组，各组具有位于其上的UBM层；以及
焊料凸块，此焊料凸块包括位于各UBM层上的铅焊料或无铅焊料，并且其中，所述半导体器件包括集成电路倒装芯片。
5.一种半导体器件制作方法，包括：
提供半导体衬底，此半导体衬底具有位于其上的互连；
在位于互连上的钝化层中产生焊料凸块支持窗口；
形成位于焊料凸块支持窗口内的支持小柱，所述支持小柱包含导电材料；以及
在支持小柱之上和之间形成凸块下方金属化层，即UBM层，以使得UBM层的部分被焊料凸块支持小柱支持。
6.如权利要求5所述的方法，其中，产生包括在钝化层上和窗口内淀积牺牲层，并且此方法还包括：
在窗口内牺牲层中形成图形；
在图形中淀积导电材料，以便形成支持小柱；
清除牺牲层；
在多个支持小柱之间和钝化层上形成UBM层；以及
在UBM层上淀积焊料凸块。
7.如权利要求6所述的方法，其中，所述钝化层是晶片钝化层，并且此方法还包括在清除牺牲层之后，在晶片钝化层上形成最终钝化层，并且其中，最终钝化层的部分位于多个端部支持小柱与晶片钝化层之间，并且还包括在多个支持小柱之间形成不同的导电材料。
8.一种半导体器件，包括：
互连层，此互连层位于半导体衬底上；
钝化层，此钝化层位于互连层上，并且其中形成有窗口；
支持小柱，此支持小柱位于窗口内，此支持小柱包括金属，并且每个支持小柱包括含有金属的延伸区；
凸块下方金属层，即UBM层，位于所述支持小柱上，用于支持焊料凸块，其中UBM层的部分位于所述支持小柱之间，并且被所述支持小柱支持；以及
位于UBM层上的焊料凸块。
9.如权利要求8所述的半导体器件，其中，所述金属是金，且各金支持小柱包括位于其上的金合金延伸区。
10.如权利要求9所述的半导体器件，其中，所述半导体器件包括相对的集成电路倒装芯片，各倒装芯片包括金支持小柱和金合金延伸区，各集成电路倒装芯片的金合金延伸区基本上彼此接触，以便在集成电路倒装芯片之间提供导电。
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