CN100580918C - Encapsulation structure capable of reducing encapsulation stress - Google Patents
Encapsulation structure capable of reducing encapsulation stress Download PDFInfo
- Publication number
- CN100580918C CN100580918C CN200810083425A CN200810083425A CN100580918C CN 100580918 C CN100580918 C CN 100580918C CN 200810083425 A CN200810083425 A CN 200810083425A CN 200810083425 A CN200810083425 A CN 200810083425A CN 100580918 C CN100580918 C CN 100580918C
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- CN
- China
- Prior art keywords
- intermediary substrate
- fluid sealant
- transition temperature
- carrier
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Wire Bonding (AREA)
Abstract
The present invention discloses a packaging construct for reducing packaging stress, which mostly include a load carrier, an intermediary substrate, multi- conductive element, the first sealant, the chip and the second sealant. The intermediary substrate is arranged at the load carrier, the conductive element electrically connected the intermediary substrate and the load carrier, the first sealant coats the conductive element, the multi- projection of the chip joints the intermediary substrate, the second sealant covers the projection, and the first gamma transition temperature of the first sealant is bigger than the second gamma transition temperature of the second sealant. Because the gamma transition temperature is different between the first sealant and the second sealant, and the first gamma transition temperature of the first sealant is bigger than the second gamma transition temperature of the second sealant, so the stress in the packaging construct is reduced, and the products yield is improved.
Description
Technical field
The present invention relates to a kind of packaging structure, particularly a kind of packaging structure that reduces encapsulation stress.
Background technology
The known package structure mainly comprises carrier; chip; intermediary substrate and fluid sealant; wherein this chip and this intermediary substrate can form by a plurality of projections of this chip and electrically connect; electrically then the needing of this intermediary substrate and this carrier form electric connection by a plurality of conducting elements in addition; and for this projection and this conducting element of protecting this chip; must this projection and this conducting element be coated with sealing glue; yet in the process of packaging technology; because this carrier; this chip is different with this intermediary substrate three's thermal coefficient of expansion; but use identical fluid sealant; make this carrier; this chip and this intermediary substrate produce deformation because of being heated and cause internal stress; so the known package structure can cause electrically connecting failure because of stress, increase not rate of finished products of product.
Summary of the invention
Main purpose of the present invention is to provide a kind of packaging structure that reduces encapsulation stress, carrier, intermediary substrate, a plurality of first conducting element, first fluid sealant, chip and second fluid sealant.The upper surface of this carrier is provided with a plurality of connection gaskets, the lower surface of this carrier is provided with a plurality of ball pads, this intermediary substrate is arranged at this upper surface of this carrier, this intermediary substrate has first surface, second surface and a plurality of via, this via electrically conduct a plurality of first contacts of this first surface and a plurality of second contacts of this second surface, this first conducting element is arranged between this carrier and this intermediary substrate and electrically connects this intermediary substrate and this carrier, this first fluid sealant coats this first conducting element, this first fluid sealant has first glass transition temperature, this flip-chip is engaged in this intermediary substrate, a plurality of bump bond of this chip are to this first contact of this intermediary substrate, this second fluid sealant coats this projection, this second fluid sealant has second glass transition temperature, and wherein this first glass transition temperature of this first fluid sealant is greater than this second glass transition temperature of this second fluid sealant.Effect of the present invention is to coat this first fluid sealant of this first conducting element and coats the two the glass transition temperature of this second fluid sealant of this projection different, and this first glass transition temperature of this first fluid sealant is greater than this second glass transition temperature of this second fluid sealant, this kind packaging structure can reduce the stress in the packaging structure, makes the finished product rate improve.
Mainly comprise carrier, intermediary substrate, a plurality of first conducting element, first fluid sealant, chip and second fluid sealant according to a kind of packaging structure that reduces encapsulation stress of the present invention.This carrier has upper surface and lower surface, this upper surface is provided with a plurality of connection gaskets, this lower surface is provided with a plurality of ball pads, this intermediary substrate is arranged at this upper surface of this carrier, this intermediary substrate has first surface, second surface and a plurality of via, this first surface is provided with a plurality of first contacts, this second surface is provided with a plurality of second contacts, this via electrically conduct this first contact and this second contact, this first conducting element is arranged between this carrier and this intermediary substrate and electrically connects this intermediary substrate and this carrier, this first fluid sealant coats this first conducting element, this first fluid sealant has first glass transition temperature, this flip-chip is engaged in this intermediary substrate, this chip has a plurality of projections, this bump bond is to this first contact of this intermediary substrate, this second fluid sealant coats this projection, this second fluid sealant has second glass transition temperature, and wherein this first glass transition temperature of this first fluid sealant is greater than this second glass transition temperature of this second fluid sealant.
Description of drawings
Fig. 1 is a kind of schematic cross-section that reduces the packaging structure of encapsulation stress according to the present invention's first specific embodiment.
Fig. 2 is for reducing the schematic cross-section of the packaging structure of encapsulation stress according to the another kind of the present invention's second specific embodiment.
Description of reference numerals
100 packaging structures, 110 carriers
111 upper surfaces, 112 lower surfaces
113 connection gaskets, 114 ball pads
120 intermediary substrates, 121 first surfaces
122 second surfaces, 123 vias
124 first contacts, 125 second contacts
126 integrated passive component 130 first conducting elements
140 first fluid sealants, 150 chips
151 active faces, 152 projections
160 second fluid sealants, 170 second conducting elements
Embodiment
See also Fig. 1, disclose a kind of packaging structure 100 that reduces encapsulation stress according to a specific embodiment of the present invention, it includes a carrier 110, intermediary substrate 120, a plurality of first conducting element 130, first fluid sealant 140, chip 150 and second fluid sealant 160.This carrier 110 has upper surface 111 and lower surface 112, this carrier 110 can be selected from organic substrate or lead frame, in the present embodiment, this carrier 110 is organic substrate, this upper surface 111 is provided with a plurality of connection gaskets 113, this lower surface 112 is provided with a plurality of ball pads 114, this intermediary substrate 120 is arranged at this upper surface 111 of this carrier 110, the material of this intermediary substrate 120 is a silicon, this intermediary substrate 120 has first surface 121, second surface 122 and a plurality of via 123, this first surface 121 is provided with a plurality of first contacts 124, this second surface 122 is provided with a plurality of second contacts 125, this via 123 electrically conduct this first contact 124 and this second contact 125, preferably, this intermediary substrate 120 have in addition at least one integrated passive component (Integrated Passive Device, IPD) 126, this integrated passive component 126 is embedded at this first surface 121 of this intermediary substrate 120.This first conducting element 130 is arranged between this carrier 110 and this intermediary substrate 120 and electrically connects this intermediary substrate 120 and this carrier 110, this first conducting element 130 can be projection and electrically connects this second contact 125 of this intermediary substrate 120 and this connection gasket 113 of this carrier 110, this first fluid sealant 140 coats this first conducting element 130, this first fluid sealant 140 has first glass transition temperature (first glass transition temperature, Tg
1), this first glass transition temperature of this first fluid sealant 140 is between 120 to 160 degree, and preferably, this first glass transition temperature of this first fluid sealant 140 is 140 degree.These chip 150 flip chip bondings are engaged in this intermediary substrate 120, in the present embodiment, this chip 150 is a functional chip, one active face 151 of this chip 150 has a plurality of projections 152, this first contact 124 that this projection 152 is engaged to this intermediary substrate 120 makes this chip 150 and this intermediary substrate 120 form electric connection, and be electrically connected at this carrier 110 by this intermediary substrate 120, in the present embodiment, the size of this intermediary substrate 120 is greater than the size of this chip 150, perhaps, as shown in Figure 2, the size of this chip 150 can equal the size of this intermediary substrate 120.Please consult Fig. 1 again, this second fluid sealant 160 coats this projection 152, and this second fluid sealant 160 has second glass transition temperature (second glass transition temperature, Tg
2), wherein this first glass transition temperature of this first fluid sealant 140 is greater than this second glass transition temperature of this second fluid sealant 160, this second glass transition temperature of this second fluid sealant 160 less than 100 degree and this second glass transition temperature of this second fluid sealant 160 between 50 to 90 degree, preferably, this second glass transition temperature of this second fluid sealant 160 is 70 degree, in addition, this packaging structure 100 includes a plurality of second conducting elements 170 in addition, this second conducting element 170 can be soldered ball and is arranged at this ball pad 114 of this carrier 110, with external tellite (figure does not draw).Because the two glass transition temperature of this first fluid sealant 140 that coats this first conducting element 130 and this second fluid sealant 160 that coats this projection 152 is also inequality, so effect of the present invention is that this first glass transition temperature by this first fluid sealant 140 is greater than this second glass transition temperature of this second fluid sealant 160, make the stress in this packaging structure 100 reduce, and then improve the finished product rate.
Protection scope of the present invention is when looking being as the criterion that accompanying Claim defines, and any variation and modification that those skilled in the art are done without departing from the spirit and scope of the present invention all belong to protection scope of the present invention.
Claims (10)
1, a kind of packaging structure that reduces encapsulation stress, it comprises:
Carrier, it has upper surface and lower surface, and this upper surface is provided with a plurality of connection gaskets, and this lower surface is provided with a plurality of ball pads;
Intermediary substrate, it is arranged at this upper surface of this carrier, and this intermediary substrate has first surface, second surface and a plurality of via, and this first surface is provided with a plurality of first contacts, this second surface is provided with a plurality of second contacts, this via electrically conduct this first contact and this second contact;
A plurality of first conducting elements, it is arranged between this carrier and this intermediary substrate, and by this first conducting element being electrically connected the connection gasket of this carrier and second contact of this intermediary substrate respectively, to electrically connect this intermediary substrate and this carrier;
First fluid sealant, it coats this first conducting element, and this first fluid sealant has first glass transition temperature;
Chip, its flip chip bonding is engaged in this intermediary substrate, and this chip has a plurality of projections, and this bump bond is to this first contact of this intermediary substrate; And
Second fluid sealant, it coats this projection, and this second fluid sealant has second glass transition temperature, and wherein this first glass transition temperature of this first fluid sealant is greater than this second glass transition temperature of this second fluid sealant.
2, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein this second glass transition temperature of this second fluid sealant is less than 100 degree.
3, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein this first glass transition temperature of this first fluid sealant is between 120 to 160 degree.
4, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein this chip is a functional chip.
5, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein the size of this chip equals the size of this intermediary substrate.
6, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein the size of this intermediary substrate is greater than the size of this chip.
7, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein the material of this intermediary substrate is a silicon.
8, the packaging structure that reduces encapsulation stress as claimed in claim 1, it includes a plurality of second conducting elements in addition, and this second conducting element is arranged at this ball pad of this carrier.
9, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein this carrier is selected from organic substrate or lead frame.
10, the packaging structure that reduces encapsulation stress as claimed in claim 1, wherein this intermediary substrate has at least one integrated passive component in addition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810083425A CN100580918C (en) | 2008-03-05 | 2008-03-05 | Encapsulation structure capable of reducing encapsulation stress |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810083425A CN100580918C (en) | 2008-03-05 | 2008-03-05 | Encapsulation structure capable of reducing encapsulation stress |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101256997A CN101256997A (en) | 2008-09-03 |
| CN100580918C true CN100580918C (en) | 2010-01-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810083425A Active CN100580918C (en) | 2008-03-05 | 2008-03-05 | Encapsulation structure capable of reducing encapsulation stress |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100580918C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013086754A1 (en) * | 2011-12-12 | 2013-06-20 | 清华大学 | Universal encapsulation substrate, encapsulation structure and encapsulation method |
| WO2016165074A1 (en) * | 2015-04-14 | 2016-10-20 | 华为技术有限公司 | Chip |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI394253B (en) | 2009-03-25 | 2013-04-21 | Advanced Semiconductor Eng | Chip having bump and package having the same |
| CN101853828B (en) * | 2009-04-03 | 2012-12-26 | 日月光半导体制造股份有限公司 | Chip with convex block and packaging structure of chip with convex block |
| TWI394221B (en) | 2009-04-30 | 2013-04-21 | Advanced Semiconductor Eng | Silicon wafer having a testing pad and method for testing the same |
| CN101976664B (en) * | 2010-09-06 | 2012-07-04 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacture process thereof |
| CN102368495A (en) * | 2011-10-09 | 2012-03-07 | 常熟市华海电子有限公司 | Anti-static chip packaging structure |
| CN103236425B (en) * | 2013-04-23 | 2015-11-18 | 山东华芯半导体有限公司 | A kind of DRAM dual chip stack package structure and packaging technology |
| CN104009014B (en) * | 2014-04-26 | 2017-04-12 | 华进半导体封装先导技术研发中心有限公司 | Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method |
| US10381301B2 (en) * | 2017-02-08 | 2019-08-13 | Micro Technology, Inc. | Semiconductor package and method for fabricating the same |
| CN108573885B (en) * | 2017-03-07 | 2021-03-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| DE102017223046A1 (en) * | 2017-12-18 | 2019-06-19 | Zf Friedrichshafen Ag | Method for warming up a pneumatic clutch actuator |
-
2008
- 2008-03-05 CN CN200810083425A patent/CN100580918C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013086754A1 (en) * | 2011-12-12 | 2013-06-20 | 清华大学 | Universal encapsulation substrate, encapsulation structure and encapsulation method |
| WO2016165074A1 (en) * | 2015-04-14 | 2016-10-20 | 华为技术有限公司 | Chip |
| US10475741B2 (en) | 2015-04-14 | 2019-11-12 | Huawei Technologies Co., Ltd. | Chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101256997A (en) | 2008-09-03 |
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