CN100586022C - Phase reverse, or/no gate, and/no gate with adjustable overturn point - Google Patents
Phase reverse, or/no gate, and/no gate with adjustable overturn point Download PDFInfo
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- CN100586022C CN100586022C CN200810082748A CN200810082748A CN100586022C CN 100586022 C CN100586022 C CN 100586022C CN 200810082748 A CN200810082748 A CN 200810082748A CN 200810082748 A CN200810082748 A CN 200810082748A CN 100586022 C CN100586022 C CN 100586022C
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- 239000004065 semiconductor Substances 0.000 claims abstract description 118
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 114
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 114
- 230000007306 turnover Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
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Abstract
The invention relates to an inverter, a nor gate and a nand gate which can adjust turnover points. The inverter comprises an input end which is used for receiving an input signal, an output end which is used for outputting an inverting signal of the input signal, a first P type metal oxide semiconductor transistor, a grid electrode of which is coupled at the input end, a drain electrode thereof is coupled at the output end, and a source electrode thereof is coupled at a bias voltage power source; a first N type metal oxide semiconductor transistor, a grid electrode of which is coupled at the input end, a drain electrode thereof is coupled at the output end, and a source electrode thereof is coupled at a grounding end; and an adjustable current supply coupled at the output end for outputting a current the intensity of which is adjustable so as to adjust turnover points of the inverter.
Description
Technical field
What the present invention relates to is a kind of inverter of adjusting overturn point, particularly be a kind of also inverter of temperature influence not simultaneously of overturn point of adjusting.
Background technology
Please refer to shown in Figure 1.It is the inverter 100 of a background technology.As shown in the figure, inverter 100 is made up of N type metal oxide semiconductor transistor (NMOS) Qn1 and P-type mos transistor (PMOS) Qp1, and comprises an input in order to receive an input signal Vin and an output in order to transmit an output signal Vout.The source electrode of metal oxide semiconductor transistor Qp1 is coupled in bias voltage VDD, grid is coupled in input and is coupled in output in order to receiving inputted signal Vin, drain electrode.The source electrode of metal oxide semiconductor transistor Qn1 is coupled in a ground end, grid is coupled in input and is coupled in output in order to receiving inputted signal Vin, drain electrode.
Please refer to shown in Figure 2ly, it is the schematic diagram of the relation of the input signal of inverter 100 of explanation background technology and output signal.As shown in the figure, VT is the current potential of overturn point (threshold).When the voltage of input signal Vin was higher than overturn point VT, output signal Vout just was electronegative potential VL; When the voltage of input signal Vin hanged down at overturn point VT, output signal Vout just was high potential VH.For instance, establishing high potential VH is that 5 volts, electronegative potential VL are that 0 volt, overturn point VT are 2.5 volts; Then when input signal Vin surpassed 2.5 volts, output signal Vout just became 0 volt; When input signal Vin hanged down at 2.5 volts, output signal Vout just became 5 volts.So function mode is reached the purpose of signal inversion operation.
Yet in general, the magnitude of voltage of overturn point VT is for fixing, and during P-type mos transistor AND gate N type metal oxide semiconductor transistor in making inverter 100, the passage length-width ratio of the two has just determined the size of overturn point VT.Therefore, the user is if want input signal Vin is operated in place than high potential, 3～4 volts scope for example, and the current potential of overturn point VT is always 2.5 volts, output signal Vout just can only maintain electronegative potential VL thus; Perhaps the user is if want input signal Vin is operated in the place of comparison electronegative potential, 1～2 volt scope for example, and output signal Vout just can only maintain electronegative potential VH thus.And for above-mentioned reasons, cause the scope of application of the inverter 100 of background technology to limit to some extent.
Moreover, the inverter that different processing are produced, its overturn point is not quite similar.Even and in fact same processing, overturn point can be all not identical yet.Also in particular, be example with the P-type mos transistor, even with a kind of processing, different batches P-type mos transistor, under identical bias voltage, the electric current of being exported all not necessarily can be the same.Therefore, the user is on using, and why its overturn point of inverter that can't clearly learn background technology causes user's inconvenience.
Summary of the invention
The invention provides a kind of to voltage, temperature, the insensitive inverter of adjusting overturn point of processing.Described inverter comprises an input, in order to receive an input signal; One output is in order to export the inversion signal of described input signal; One first P-type mos transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a grid bias power supply; One the one N type metal oxide semiconductor transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a ground end; With an adjustable current source, be coupled in described output, in order to export a sizable electric current to adjust the overturn point of described inverter, wherein, described adjustable current source comprises:
One attached metal oxide semiconductor transistor, its grid is coupled in a control voltage source, exports one first electric current in order to the size of the control voltage exported according to described control voltage source; With
One current mirror is coupled between described attached metal oxide semiconductor transistor and the described output, in order to produce one second electric current according to described first electric current to described output.
It is a kind of to voltage, temperature, the insensitive inverter of adjusting overturn point of processing that the present invention also provides.Described inverter comprises an input, in order to receive an input signal; One output is in order to export the inversion signal of described input signal; One first P-type mos transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a grid bias power supply; One the one N type metal oxide semiconductor transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a ground end; With an adjustable current source, be coupled in described output, in order to export a sizable electric current to adjust the overturn point of described inverter, wherein, described adjustable current source comprises:
One first attached metal oxide semiconductor transistor, its grid are coupled in one first control voltage source, export one first electric current in order to first size of exporting according to described first control voltage source of controlling voltage;
One second attached metal oxide semiconductor transistor, its grid are coupled in one second control voltage source, export one second electric current in order to second size of exporting according to described second control voltage source of controlling voltage;
One first current mirror is in order to produce one the 3rd electric current to described output according to described first electric current; With
One second current mirror is in order to produce one the 4th electric current to described output according to described second electric current.
It is a kind of to voltage, temperature, the insensitive NAND gate of adjusting overturn point of processing that the present invention provides in addition.Described NAND gate comprises a first input end, in order to receive one first input signal; One second input is in order to receive one second input signal; One output is in order to export described first input signal and the signal of described second input signal after NAND operation; One the one N type metal oxide semiconductor transistor, its grid is coupled in described first input end, and source electrode is coupled in a ground end; One the 2nd N type metal oxide semiconductor transistor, its grid is coupled in described second input, and source electrode is coupled in a described N type metal oxide semiconductor transistor drain, and drain electrode is coupled in described output; One first P-type mos transistor, its grid is coupled in described first input end, and source electrode is coupled in a grid bias power supply, and drain electrode is coupled in described output; One second P-type mos transistor, its grid are coupled in described second input, and source electrode is coupled in described grid bias power supply, and drain electrode is coupled in described output; With an adjustable current source, be coupled in described output, in order to export a sizable electric current to adjust overturn point, wherein: described adjustable current source comprises: an attached metal oxide semiconductor transistor pair and a current mirror; Wherein,
Described attached metal oxide semiconductor transistor is right, be coupled in a control voltage source, size in order to the control voltage exported according to described control voltage source is exported one first electric current, described attached metal oxide semiconductor transistor is to comprising: one first attached metal oxide semiconductor transistor, its source electrode is coupled in describedly to be held, and grid is coupled in described control voltage source; With one second attached metal oxide semiconductor transistor, its source electrode is coupled in the drain electrode of the described first attached metal oxide semiconductor transistor, and grid is coupled in described control voltage source;
Described current mirror is coupled between the drain electrode and described output of the described second attached metal oxide semiconductor transistor, in order to produce one second electric current according to described first electric current to described output.
It is a kind of to voltage, temperature, the insensitive NOR gate of adjusting overturn point of processing that the present invention provides in addition.Described NOR gate comprises a first input end, in order to receive one first input signal; One second input is in order to receive one second input signal; One output is in order to export described first input signal and the signal of described second input signal after NOR-operation; One the one N type metal oxide semiconductor transistor, its grid is coupled in described first input end, and its source electrode is coupled in a ground end, and its drain electrode is coupled in described output; One the 2nd N type metal oxide semiconductor transistor, its grid is coupled in described second input, and its source electrode is coupled in describedly to be held, and its drain electrode is coupled in described output; One first P-type mos transistor, its grid is coupled in described first input end, and its source electrode is coupled in a grid bias power supply; One second P-type mos transistor, its grid are coupled in described second input, and its source electrode is coupled in the described first P-type mos transistor drain, and its drain electrode is coupled in described output; With an adjustable current source, be coupled in described output, in order to export a sizable electric current to adjust overturn point, wherein: described adjustable current source comprises: an attached metal oxide semiconductor transistor pair and a current mirror; Wherein,
Described attached metal oxide semiconductor transistor is right, be coupled in a control voltage source, size in order to the control voltage exported according to described control voltage source is exported one first electric current, described attached metal oxide semiconductor transistor is to comprising: one first attached metal oxide semiconductor transistor, its source electrode is coupled in described grid bias power supply, and grid is coupled in described control voltage source; With one second attached metal oxide semiconductor transistor, its source electrode is coupled in the drain electrode of the described first attached metal oxide semiconductor transistor, and grid is coupled in described control voltage source; With
Described current mirror is coupled between the drain electrode and described output of the described second attached metal oxide semiconductor transistor, in order to produce one second electric current according to described first electric current to described output.
Description of drawings
Fig. 1 is the schematic diagram of the inverter of a background technology;
Fig. 2 is the schematic diagram of the relation of the input signal of inverter of explanation background technology and output signal;
Fig. 3 is a schematic diagram of adjusting the inverter of overturn point of the present invention;
Fig. 4 is the schematic diagram of first embodiment of the adjustable current source of the inverter of adjusting overturn point of the present invention;
Fig. 5 is the schematic diagram of second embodiment of the adjustable current source of the inverter of adjusting overturn point of the present invention;
Fig. 6 is the schematic diagram of the 3rd embodiment of the adjustable current source of the inverter of adjusting overturn point of the present invention;
Fig. 7 is a schematic diagram of adjusting the NAND gate of overturn point of the present invention;
Fig. 8 is the schematic diagram of first embodiment of the adjustable current source of the NAND gate of adjusting overturn point of the present invention;
Fig. 9 is a schematic diagram of adjusting the NOR gate of overturn point of the present invention;
Figure 10 is the schematic diagram of first embodiment of the adjustable current source of the NOR gate of adjusting overturn point of the present invention.
Description of reference numerals: Qn1Qn2Qn3Qn4N-type metal oxide semiconductor transistor; Qp1Qp2Qp3Qp4P-type metal oxide semiconductor transistor; The VinVinaVinb-input signal; The Vout-output signal; The VDD-bias voltage; The VT-overturn point; The VH-high potential; The VL-electronegative potential; The I-electric current; X-controls voltage; 100,300-inverter; The 310610810-adjustable current source; 600,620-NAND gate; 800,820-NOR gate.
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
Please refer to Fig. 3.Fig. 3 is a schematic diagram of adjusting the inverter 300 of overturn point of the present invention.As shown in the figure, inverter 300 comprises an inverter 100 and an adjustable current source 310.Inverter 300 function modes are the output at inverter 100, add an adjustable current source 310 and arrive transistor Qp1 or Qn1 to change overturn point VT so that electric current I to be provided.For instance, when input signal Vin from electronegative potential slowly toward high potential when climbing, the electric current that transistor Qp1 exported will diminish gradually and electric current that transistor Qn1 is exported will become greatly gradually, that is to say that the current potential of output signal Vout will be gradually toward electronegative potential VL convergence; Be higher than overturn point VT (being made as 2.5 volts) up to input signal Vin, the electric current of transistor Qp1 institute conducting will be less than the electric current of transistor Qn1 institute conducting, and this moment, output signal Vout was pulled low to electronegative potential VL by transistor Qn1 fully.Therefore, adjustable current source 310 provided by the present invention can provide electric current I at output, up promote with current potential output signal Vout, thus, the current potential of input signal Vin just must make that the degree of transistor Qn1 conducting is also big, that the pull-down current of output signal Vout is also big going back high, output signal could be pulled down to electronegative potential VL.So, just can promote the size of overturn point VT.So if the overturn point VT of original inverter 100 is located at 2.5 volts, bias voltage VDD is made as 5 volts, then via design of the present invention, overturn point VT can be heightened be 3.5 volts to make things convenient for input signal Vin to be operable in also high scope (3～4 volts).On the contrary, when input signal Vin when high potential slowly descends toward electronegative potential, the electric current that transistor Qn1 exported will diminish gradually and electric current that transistor Qp1 is exported will become greatly gradually, that is to say that the current potential of output signal Vout will be gradually toward high potential VH convergence; Hang down at overturn point VT up to input signal Vin, the electric current of transistor Qn1 institute conducting is less than the electric current of transistor Qp1 institute conducting, and this moment, output signal Vout was drawn high to high potential VH by transistor Qp1 fully.Therefore, adjustable current source 310 provided by the present invention also can provide electric current I at output, down drag down with current potential output signal Vout, thus, the current potential of input signal Vin just must could be promoted to output signal Vout high potential VH also low and make that the degree of transistor Qp1 conducting is also big, that the lifting electric current of output signal Vout is also big.So, just can reduce the size of overturn point VT.So be made as 5 volts if the overturn point VT of original inverter 100 is located at 2.5 volts and bias voltage VDD,, overturn point VT can be reduced to 1.5 volts to make things convenient for input signal Vin to be operable in also low scope (1～2 volt) then via design of the present invention.And the electric current I that adjustable current source 310 is exported is big more, and the degree of overturn point lifting/decline is just high more.And inverter 300 provided by the present invention just can be controlled the size of current of adjustable current source 310 outputs according to user's voltage range of action required input signal in fact, and then adjusts overturn point VT, to meet user's needs.
Please refer to Fig. 4.Fig. 4 is the schematic diagram of adjustable current source 310 first embodiment of the inverter 300 of adjusting overturn point of the present invention.As shown in the figure, adjustable current source 310 comprises two N type metal oxide semiconductor transistor Qn2, Qn3 and a P-type mos transistor Qp4.The source electrode of P-type mos transistor Qp4 is coupled in bias voltage VDD, grid in order to receive the drain electrode that a control voltage Vx, drain electrode are coupled in N type metal oxide semiconductor transistor Qn3.The grid of N type metal oxide semiconductor transistor Qn3 is coupled in that drain electrode, the source electrode of P-type mos transistor Qp4 are held with being coupled in, draining is coupled in the drain electrode of P-type mos transistor Qp4.The grid of N type metal oxide semiconductor transistor Qn2 is coupled in that drain electrode, the source electrode of P-type mos transistor Qp4 are held with being coupled in, draining is coupled in the output of inverter 100.The coupling mode of transistor Qn2 and transistor Qn3 is to form a current mirror, in order to the electric current of the replica transistor Qp4 institute conducting output to inverter 100; Control voltage Vx is in order to the size of current of oxide-semiconductor control transistors Qp4 institute conducting.So just can control size of current and and then control overturn point VT that adjustable current source 310 exports inverter 100 to.In this embodiment, the electric current that adjustable current source 310 is exported will drag down the output signal of inverter 100, that is to say, can reduce overturn point VT.Therefore, when user's desire operates in lower voltage range with input signal Vin, can use this embodiment that overturn point VT is turned down.And adjust the electric current except changing control voltage Vx, inverter 300 of the present invention, also control voltage Vx can be made as 0 volt (ground connection),, adjust electric current that adjustable current source 310 exported to adjust overturn point VT against passage length and the width of adjusting transistor Qp4.In the actual application, be to be easier to use against passage length that changes transistor Qp4 or width then for the user with the grounded-grid of transistor Qp4.In addition, in this embodiment, because the size of current of metal oxide semiconductor transistor institute conducting, except relevant, also relevant with temperature, channel length, channel width with conducting voltage.That is to say metal oxide semiconductor transistor when temperature rises, the size of current of institute's conducting also can and then rise, and the amplitude of its rising, is that the passage length, width etc. with described metal oxide semiconductor transistor become a positively related relation.Therefore, in the inverter 100 of background technology, can be because of the difference of temperature, its overturn point VT also can and then change.Difficulty in the time of so will influencing the user and operate.And inverter 300 of the present invention can utilize the P-type mos transistor Qp4 in the adjustable current source 310 to offset for variation of temperature.When wanting the variation of compensation temperature with inverter of the present invention, because transistor Qp1 and Qp4 because during actual fabrication in same pocket, so temperature can be consistent, make all parameter Yin Wendu change and identical change is arranged, therefore can be to temperature-insensitive, and also can utilize the only different a little and identical uncorrelated effect that obtains the best of length of channel width absolute between identical or the transistor Qp1 and the Qp4 of channel length absolute between transistor Qp1 and the Qp4 and channel width with temperature.Also in particular, inverter 300 of the present invention can be made as a proportionate relationship with channel length, the channel width of P-type mos transistor Qp1 and Qp4, and thus, when temperature rises, the lifting electric current of transistor Qp1 institute conducting will become big; And the also and then change big (under the immovable situation of control voltage Vx) of the ascending current of transistor Qp4 institute conducting simultaneously, so the pull-down current I that is duplicated also and then becomes greatly.The amplitude that pull-down current I and the electrorheological of transistor Qp1 institute conducting are big is the same, and meets at the output of inverter 100 simultaneously, therefore can cancel each other.So, can't produce change because of any variation of temperature for output signal Vout.Therefore, the overturn point VT of inverter 300 does not just have any variation yet.In addition, in actual state, grid bias power supply VDD also might drift about.Therefore, the overturn point of the inverter 100 of background technology still can be subjected to the influence of grid bias power supply VDD.And inverter 300 of the present invention, because the design of transistor Qp4 is arranged, when grid bias power supply VDD drifted about, the electric current change that transistor Qp1 is circulated will be offset by the change of the electric current of transistor Qp4.Therefore, overturn point still can be kept the value of original setting.Moreover, as discussed previously, the transistor of different processing or same processing but different batches, the relation of its electric current and bias voltage has a little drift.Therefore, the influence of the overturn point of the inverter 100 of the background technology drift that still can be subject to processing.And inverter 300 of the present invention owing to there is transistor Qp4 to make with transistor Qp1, that is to say must be same processing with a collection of transistor, even so both can drift about, the amplitude of drift also can be the same.And this point of facility of the present invention is cancelled each other both degree of drift.Therefore, overturn point still can be kept the value of original setting.When wanting the variation of compensation temperature, voltage, processing, can utilize that the only different a little and length of channel width absolute between identical or the transistor Qp1 and the Qp4 of channel length absolute between transistor Qp1 and the Qp4 and channel width is identical to obtain best and temperature, voltage, the uncorrelated effect of processing with inverter of the present invention.So for the user, can be convenient to use inverter 300 of the present invention significantly operates.
Please refer to Fig. 5.Fig. 5 is the schematic diagram of adjustable current source 310 second embodiment of the inverter 300 of adjusting overturn point of the present invention.As shown in the figure, adjustable current source 310 comprises two P-type mos transistor Qp2, Qp3 and a N type metal oxide semiconductor transistor Qn4.The source electrode of N type metal oxide semiconductor transistor Qn4 is held with being coupled in, grid is in order to receive the drain electrode that a control voltage Vx, drain electrode are coupled in P-type mos transistor Qp3.Drain electrode, the source electrode that the grid of P-type mos transistor Qp3 is coupled in N type metal oxide semiconductor transistor Qn4 is coupled in bias voltage VDD, draining is coupled in the drain electrode of N type metal oxide semiconductor transistor Qn4.Drain electrode, the source electrode that the grid of P-type mos transistor Qp2 is coupled in N type metal oxide semiconductor transistor Qn4 is coupled in bias voltage VDD, draining is coupled in the output of inverter 100.The coupling mode of transistor Qp2 and transistor Qp3 is to form a current mirror, in order to the electric current of the replica transistor Qn4 institute conducting output to inverter 100; Control voltage Vx is in order to the size of current of oxide-semiconductor control transistors Qn4 institute conducting.So just can control size of current and and then control overturn point VT that adjustable current source 310 exports inverter 100 to.In this embodiment, the electric current that adjustable current source 310 is exported will promote the output signal of inverter 100, that is to say, can promote overturn point VT.Therefore, when user's desire operates in the higher voltage scope with input signal Vin, can use this embodiment that overturn point VT is heightened.And adjust the electric current except changing control voltage Vx, inverter 300 of the present invention, also control voltage Vx can be made as 0 volt (ground connection),, adjust electric current that adjustable current source 310 exported to adjust overturn point VT against channel length, the channel width of adjusting transistor Qn4.In the actual application, be to be easier to use against the channel length, the channel width that change transistor Qn4 then for the user with the grounded-grid of transistor Qn4.In addition, in this embodiment, because the size of current of metal oxide semiconductor transistor institute conducting, except relevant, also relevant with temperature, channel length, channel width with conducting voltage.That is to say metal oxide semiconductor transistor when temperature rises, the size of current of institute's conducting also can and then rise, and the amplitude of its rising, is that the channel length, channel width etc. with described metal oxide semiconductor transistor become a positively related relation.Therefore, in the inverter 100 of background technology, can be because of the difference of temperature, its overturn point VT also can and then change.Difficulty in the time of so will influencing the user and operate.And inverter 300 of the present invention can utilize the N type metal oxide semiconductor transistor Qn4 in the adjustable current source 310 to offset for variation of temperature.When wanting the variation of compensation temperature with inverter of the present invention, because transistor Qn1 and Qn4 because during actual fabrication in same pocket, so temperature can be consistent, make all parameter Yin Wendu change and identical change is arranged, therefore can be to temperature-insensitive, and also can utilize the only different a little and identical uncorrelated effect that obtains the best of length of channel width absolute between identical or the transistor Qn1 and the Qn4 of channel length absolute between transistor Qn1 and the Qn4 and channel width with temperature.Also in particular, inverter 300 of the present invention can be made as a proportionate relationship with the passage length-width ratio of N type metal oxide semiconductor transistor Qn1 and Qn4, and thus, when temperature rises, the pull-down current of transistor Qn1 institute conducting will become big; And the also and then change big (under the immovable situation of control voltage Vx) of the pull-down current of transistor Qn4 institute conducting simultaneously, so the lifting electric current I of being duplicated also and then becomes greatly.It is the same to promote the big amplitude of electric current I and the electrorheological of transistor Qn1 institute conducting, and meets at the output of inverter 100 simultaneously, so can cancel each other.So, can't produce change because of any variation of temperature for output signal Vout.Therefore, the overturn point VT of inverter 300 does not just have any variation yet.In addition, in actual state, grid bias power supply VDD also might drift about.Therefore, the overturn point of the inverter 100 of background technology still can be subjected to the influence of grid bias power supply VDD.And inverter 300 of the present invention, because the design of transistor Qn4 is arranged, when grid bias power supply VDD drifted about, the electric current change that transistor Qn1 is circulated will be offset by the change of the electric current of transistor Qn4.Therefore, overturn point still can be kept the value of original setting.Moreover, as discussed previously, the transistor of different processing or same processing but different batches, the relation of its electric current and bias voltage has a little drift.Therefore, the influence of the overturn point of the inverter 100 of the background technology drift that still can be subject to processing.And inverter 300 of the present invention owing to there is transistor Qn4 to make with transistor Qn1, that is to say must be same processing with a collection of transistor, even so both can drift about, the amplitude of drift also can be the same.And this point of facility of the present invention is cancelled each other both degree of drift.Therefore, overturn point still can be kept the value of original setting.When wanting the variation of compensation temperature, voltage, processing, can utilize that the only different a little and length of channel width absolute between identical or the transistor Qn1 and the Qn4 of channel length absolute between transistor Qn1 and the Qn4 and channel width is identical to obtain best and temperature, voltage, the uncorrelated effect of processing with inverter of the present invention.So for the user, can be convenient to use inverter 300 of the present invention significantly operates.
Please refer to Fig. 6.Fig. 6 is the schematic diagram of adjustable current source 310 the 3rd embodiment of the inverter 300 of adjusting overturn point of the present invention.As shown in Figure 6, the 3rd embodiment of adjustable current source 310 of the present invention is by being made of first embodiment of the adjustable current source 310 of Fig. 4 and second embodiment with the adjustable current source 310 of Fig. 5.The description of related work principle does not repeat them here as the description of Fig. 4 and the description of Fig. 5.Therefore, of the present inventionly adjust the adjustable current source 310 that overturn point inverter 300 can utilize Fig. 6, offer also operation easily of user.
Please refer to Fig. 7.Fig. 7 is a schematic diagram of adjusting the NAND gate 600 of overturn point of the present invention.As shown in the figure, NAND gate 600 comprises a NAND gate 620 and an adjustable current source 610.NAND gate 620 comprises two N type metal oxide semiconductor transistor Qn1 and Qn2, two P-type mos transistor Qp1 and Qp2.The source electrode of transistor Qn1 source electrode, the grid that is coupled in transistor Qn2 of holding with being coupled in, drain is coupled in the first input end of NAND gate 620 in order to receiving inputted signal Vina; The source electrode of transistor Qn2 is coupled in the drain electrode of transistor Qn1, output, the grid that drain electrode is coupled in NAND gate 620 is coupled in second input of NAND gate 620 in order to receiving inputted signal Vinb; The source electrode of transistor Qp1 is coupled in bias voltage VDD, output, the grid that is coupled in NAND gate 620 that drain is coupled in first input end in order to receiving inputted signal Vina; The source electrode of transistor Qp2 is coupled in bias voltage VDD, output, the grid that is coupled in NAND gate 620 that drain is coupled in second input in order to receiving inputted signal Vinb.NAND gate 620 is in order to input signal Vina, Vinb; After then Vina and Vinb being done anti-and computing (NAND), export operation result at output.The function mode of NAND gate 600 is the output in NAND gate 620, add an adjustable current source 610 with provide electric current I to the output of NAND gate 620 to change overturn point VT.Therefore, NAND gate 600 can be adjusted the height of overturn point according to user's demand.If user's desire operates in the higher voltage scope with input signal, NAND gate 600 just can be heightened the electric current of adjustable current source to heighten overturn point.And the electric current I that adjustable current source 610 is exported is big more, and the degree that overturn point promotes is just high more.And NAND gate 600 provided by the present invention just can be controlled the size of current of adjustable current source 610 outputs according to user's voltage range of action required input signal in fact, and then adjusts overturn point VT, to meet user's needs.
Please refer to Fig. 8.Fig. 8 is the schematic diagram of adjustable current source 610 first embodiment of the NAND gate 600 of adjusting overturn point of the present invention.As shown in the figure, adjustable current source 610 comprises two N type metal oxide semiconductor transistor Qn2 and Qn3, two P-type mos transistor Qp3 and Qp4.The source electrode of transistor Qp4 is coupled in bias voltage VDD, grid is coupled in the grid of transistor Qp3, the output that drain electrode is coupled in NAND gate 620; The source electrode of transistor Qp3 is coupled in bias voltage VDD, grid is coupled in the drain electrode of transistor Qn4, the drain electrode that drain electrode is coupled in transistor Qn4; The drain electrode, grid that the source electrode of transistor Qn4 is coupled in transistor Qn3 is in order to receive the drain electrode that a control voltage Vx, drain electrode are coupled in transistor Qp3; The source electrode of transistor Qn3 is held with being coupled in, grid is controlled voltage Vx in order to receive, draining is coupled in the source electrode of transistor Qn4.The coupling mode of transistor Qp3 and transistor Qp4 is to form a current mirror, in order to the electric current of replica transistor Qn3 and the conducting of the Qn4 institute output to NAND gate 620; Control voltage Vx is in order to the size of current of oxide-semiconductor control transistors Qn3, Qn4 institute conducting.So just can control size of current and and then control overturn point VT that adjustable current source 610 exports NAND gate 620 to.In this embodiment, the electric current that adjustable current source 610 is exported will promote the output signal of NAND gate 620, that is to say, can promote overturn point VT.Therefore, when user's desire operates in the higher voltage scope with input signal Vin, can use this embodiment that overturn point VT is heightened.And adjust the electric current except changing control voltage Vx, NAND gate 600 of the present invention, also control voltage Vx can be made as 0 volt (ground connection),, adjust electric current that adjustable current source 610 exported to adjust overturn point VT against adjusting transistor Qn3, the channel length of Qn4, channel width.In the actual application, be to be easier to use against the length-width ratio that changes transistor Qn3, Qn4 then for the user with the grounded-grid of transistor Qn3, Qn4.In addition, in this embodiment, because the size of current of metal oxide semiconductor transistor institute conducting, except relevant, also relevant with temperature, channel length-width ratio with conducting voltage.That is to say metal oxide semiconductor transistor when temperature rises, the size of current of institute's conducting also can and then rise, and the amplitude of its rising is the one-tenth one positively related relations such as channel length channel width with described metal oxide semiconductor transistor.Therefore, in the NAND gate 620 of background technology, can be because of the difference of temperature, its overturn point VT also can and then change.Difficulty in the time of so will influencing the user and operate.And NAND gate 600 of the present invention can utilize N type metal oxide semiconductor transistor Qn3, Qn4 in the adjustable current source 610 to offset for variation of temperature.Also in particular, NAND gate 600 of the present invention can be made as a proportionate relationship with N type metal oxide semiconductor transistor Qn1, Qn2, Qn3, the channel length of Qn4, channel width, thus, when temperature rises, the pull-down current of transistor Qn1, Qn2 institute conducting will become big; And also and then change big (under the immovable situation of control voltage Vx) of the pull-down current of transistor Qn3, the conducting of Qn4 institute simultaneously, so the lifting electric current I of being duplicated also and then becomes greatly.The amplitude that pull-down current I and the electrorheological of transistor Qn1, Qn2 institute conducting are big is the same, and meets at the output of NAND gate 620 simultaneously, therefore can cancel each other.So, can't produce change because of any variation of temperature for output signal Vout.Therefore, the overturn point VT of NAND gate 600 does not just have any variation yet.In addition, in actual state, grid bias power supply VDD also might drift about.And NAND gate 600 of the present invention, because the design of transistor Qp3, Qp4 is arranged, when grid bias power supply VDD drifted about, the electric current change that transistor Qp1, Qp2 are circulated will be offset by the change of the electric current of transistor Qp3, Qp4.Therefore, overturn point still can be kept the value of original setting.Moreover, as discussed previously, the transistor of different processing or same processing but different batches, the relation of its electric current and bias voltage has a little drift.And NAND gate 600 of the present invention owing to have transistor Qn3, Qn4 to make with transistor Qn1, Qn2, that is to say must be same processing with a collection of transistor, even therefore can drift about, the amplitude of drift also can be the same.And this point of facility of the present invention is cancelled each other the degree of this four transistor drift.Therefore, overturn point still can be kept the value of original setting.When wanting the variation of compensation temperature, voltage, processing, can utilize that the only different a little and length of channel width absolute between identical or transistor Qn3, the Qn4 of channel length absolute between transistor Qn3, Qn4 and transistor Qp1, the Qp2 and channel width and transistor Qp1, the Qp2 is identical to obtain best and temperature, voltage, the uncorrelated effect of processing with inverter of the present invention.So for the user, can be convenient to use NAND gate 600 of the present invention significantly operates.
Please refer to Fig. 9.Fig. 9 is a schematic diagram of adjusting the NOR gate 800 of overturn point of the present invention.As shown in the figure, NOR gate 800 comprises a NOR gate 820 and an adjustable current source 810.NOR gate 820 comprises two N type metal oxide semiconductor transistor Qn1 and Qn2, two P-type mos transistor Qp1 and Qp2.The source electrode of transistor Qn1 output, the grid that is coupled in NOR gate 820 of holding with being coupled in, drain is coupled in the first input end of NOR gate 820 in order to receiving inputted signal Vina; The source electrode of transistor Qn2 output, the grid that is coupled in NOR gate 820 of holding with being coupled in, drain is coupled in second input of NOR gate 820 in order to receiving inputted signal Vinb; The source electrode of transistor Qp1 is coupled in the drain electrode of transistor Qp2, output, the grid that drain electrode is coupled in NOR gate 820 is coupled in second input in order to receiving inputted signal Vinb; The source electrode of transistor Qp2 is coupled in bias voltage VDD, source electrode, the grid that is coupled in transistor Qp1 that drain is coupled in first input end in order to receiving inputted signal Vina.NOR gate 820 is in order to input signal Vina, Vinb; After then Vina and Vinb being done anti-and computing (NOR), export operation result at output.The function mode of NOR gate 800 is the output in NOR gate 820, adds an adjustable current source 810 to provide electric current I to change overturn point VT.Therefore, NOR gate 800 can be adjusted the height of overturn point according to user's demand.If user's desire operates in lower voltage range with input signal, NOR gate 800 just the electric current of adjustable big adjustable current source to turn down overturn point.And the electric current I that adjustable current source 810 is exported is big more, and the degree that overturn point descends is just high more.And NOR gate 800 provided by the present invention just can be controlled the size of current of adjustable current source 810 outputs according to user's voltage range of action required input signal in fact, and then adjusts overturn point VT, to meet user's needs.
Please refer to Figure 10.Figure 10 is the schematic diagram of adjustable current source 810 first embodiment of the NOR gate 800 of adjusting overturn point of the present invention.As shown in the figure, adjustable current source 810 comprises two N type metal oxide semiconductor transistor Qn3 and Qn4, two P-type mos transistor Qp3 and Qp4.The source electrode of transistor Qp4 is coupled in bias voltage VDD, grid in order to receive the source electrode that a control voltage Vx, drain electrode are coupled in transistor Qp3; The source electrode of transistor Qp3 is coupled in the drain electrode of transistor Qp4, grid is coupled in transistor Qn4 in order to reception control voltage Vx, drain electrode drain electrode; The drain electrode that the source electrode of transistor Qn4 is held with being coupled in, grid is coupled in transistor Qp3, drain electrode are coupled in the drain electrode of transistor Qn3; The drain electrode that the source electrode of transistor Qn3 is held with being coupled in, grid is coupled in transistor Qn3, drain electrode are coupled in the output of NOR gate 820.The coupling mode of transistor Qn3 and transistor Qn4 is to form a current mirror, in order to the electric current of replica transistor Qp3 and the conducting of the Qp4 institute output to NOR gate 820; Control voltage Vx is in order to the size of current of oxide-semiconductor control transistors Qp3, Qp4 institute conducting.So just can control size of current and and then control overturn point VT that adjustable current source 810 exports NOR gate 820 to.In this embodiment, the electric current that adjustable current source 810 is exported will reduce the output signal of NOR gate 820, that is to say, can reduce overturn point VT.Therefore, when user's desire operates in lower voltage range with input signal Vin, can use this embodiment that overturn point VT is turned down.And adjust the electric current except changing control voltage Vx, NOR gate 800 of the present invention, also control voltage Vx can be made as 0 volt (ground connection),, adjust electric current that adjustable current source 810 exported to adjust overturn point VT against adjusting transistor Qp3, the channel length of Qp4, channel width.In the actual application, be to be easier to use against changing transistor Qp3, the channel length of Qp4, channel width then for the user with the grounded-grid of transistor Qp3, Qp4.In addition, in this embodiment, because the size of current of metal oxide semiconductor transistor institute conducting, except relevant, also relevant with temperature, channel length, channel width with conducting voltage.That is to say metal oxide semiconductor transistor when temperature rises, the size of current of institute's conducting also can and then rise, and the amplitude of its rising, is that the channel length, channel width etc. with described metal oxide semiconductor transistor become a positively related relation.Therefore, in the NOR gate 820 of background technology, can be because of the difference of temperature, its overturn point VT also can and then change.Difficulty in the time of so will influencing the user and operate.And NOR gate 800 of the present invention can utilize P-type mos transistor Qp3, Qp4 in the adjustable current source 810 to offset for variation of temperature.Also in particular, NOR gate 800 of the present invention can be made as a proportionate relationship with channel length, channel width and transistor Qp1, the Qp2 of P-type mos transistor Qp3, Qp4, thus, when temperature rises, the lifting electric current of transistor Qp1, Qp2 institute conducting will become big; And also and then change big (under the immovable situation of control voltage Vx) of the lifting electric current of transistor Qp3, the conducting of Qp4 institute simultaneously, so the pull-down current I that is duplicated also and then becomes greatly.The amplitude that pull-down current I and the electrorheological of transistor Qp1, Qp2 institute conducting are big is the same, and meets at the output of NOR gate 820 simultaneously, therefore can cancel each other.So, can't produce change because of any variation of temperature for output signal Vout.Therefore, the overturn point VT of NOR gate 820 does not just have any variation yet.In addition, in actual state, grid bias power supply VDD also might drift about.And NAND gate 600 of the present invention, because the design of transistor Qp3, Qp4 is arranged, when grid bias power supply VDD drifted about, the electric current change that transistor Qp1, Qp2 are circulated will be offset by the change of the electric current of transistor Qp3, Qp4.Therefore, overturn point still can be kept the value of original setting.Moreover, as discussed previously, the transistor of different processing or same processing but different batches, the relation of its electric current and bias voltage has a little drift.And NAND gate 600 of the present invention owing to have transistor Qp3, Qp4 to make with transistor Qp1, Qp2, that is to say must be same processing with a collection of transistor, even therefore can drift about, the amplitude of drift also can be the same.And this point of facility of the present invention is cancelled each other the degree of this four transistor drift.Therefore, overturn point still can be kept the value of original setting.When wanting the variation of compensation temperature, voltage, processing, can utilize that the only different a little and length of channel width absolute between identical or transistor Qp3, the Qp4 of channel length absolute between transistor Qp3, Qp4 and transistor Qp1, the Qp2 and channel width and transistor Qp1, the Qp2 is identical to obtain best and temperature, voltage, the uncorrelated effect of processing with inverter of the present invention.So for the user, can be convenient to use NOR gate 800 of the present invention significantly operates.
To sum up state, utilize design of the present invention, can adjust the overturn point of logic lock effectively, also can resist temperature effect, voltage, overturn point drift that processing caused, give the user higher convenience.
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limited, revise, even equivalence, but all will fall within the scope of protection of the present invention.
Claims (15)
1. one kind to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, and it is characterized in that: it comprises:
One input is in order to receive an input signal;
One output is in order to export the inversion signal of described input signal;
One first P-type mos transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a grid bias power supply;
One the one N type metal oxide semiconductor transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a ground end; With
One adjustable current source is coupled in described output, in order to export a sizable electric current to adjust the overturn point of described inverter; Wherein, described adjustable current source comprises:
One attached metal oxide semiconductor transistor, its grid is coupled in a control voltage source, exports one first electric current in order to the size of the control voltage exported according to described control voltage source; With
One current mirror is coupled between described attached metal oxide semiconductor transistor and the described output, in order to produce one second electric current according to described first electric current to described output.
2. according to claim 1 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: described current mirror comprises:
One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled in described output, and source electrode is coupled in describedly and holds; With
One the 3rd N type metal oxide semiconductor transistor, its grid is coupled in the transistorized grid of described the 2nd N type metal oxide semiconductor, drain electrode is coupled in the drain electrode of described transistorized grid of the 2nd N type metal oxide semiconductor and described attached metal oxide semiconductor transistor, and source electrode is coupled in describedly and holds.
3. according to claim 2 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: described attached metal oxide semiconductor transistor is a P-type mos transistor, and source electrode is coupled in described grid bias power supply.
4 is according to claim 1 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, and it is characterized in that: described current mirror comprises:
One second P-type mos transistor, its drain electrode is coupled in described output, and source electrode is coupled in described grid bias power supply; With
One the 3rd P-type mos transistor, its grid is coupled in the drain electrode of transistorized grid of described second P-type mos and described attached metal oxide semiconductor transistor, drain electrode is coupled in the transistorized grid of described second P-type mos, and source electrode is coupled in described grid bias power supply.
5. according to claim 4 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: described attached metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, and source electrode is coupled in describedly and holds.
6. one kind to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, and it is characterized in that: it comprises:
One input is in order to receive an input signal;
One output is in order to export the inversion signal of described input signal;
One first P-type mos transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a grid bias power supply;
One the one N type metal oxide semiconductor transistor, its grid is coupled in described input, and drain electrode is coupled in described output, and source electrode is coupled in a ground end; With
One adjustable current source is coupled in described output, in order to export a sizable electric current to adjust the overturn point of described inverter; Wherein, described adjustable current source comprises:
One first attached metal oxide semiconductor transistor, its grid are coupled in one first control voltage source, export one first electric current in order to first size of exporting according to described first control voltage source of controlling voltage;
One second attached metal oxide semiconductor transistor, its grid are coupled in one second control voltage source, export one second electric current in order to second size of exporting according to described second control voltage source of controlling voltage;
One first current mirror is in order to produce one the 3rd electric current to described output according to described first electric current; With
One second current mirror is in order to produce one the 4th electric current to described output according to described second electric current.
7. according to claim 6 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: described first current mirror comprises:
One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled in described output, and its source electrode is coupled in describedly to be held; With
One the 3rd N type metal oxide semiconductor transistor, its grid is coupled in the transistorized grid of described the 2nd N type metal oxide semiconductor, its drain electrode is coupled in the drain electrode of described transistorized grid of the 2nd N type metal oxide semiconductor and the described first attached metal oxide semiconductor transistor, and its source electrode is coupled in describedly to be held.
8. according to claim 7 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: the described first attached metal oxide semiconductor transistor is a P-type mos transistor, and source electrode is coupled in described grid bias power supply.
9. according to claim 6 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: described second current mirror comprises:
One the 3rd P-type mos transistor, its drain electrode is coupled in described output, and source electrode is coupled in described grid bias power supply; With
One the 4th P-type mos transistor, its grid is coupled in the transistorized grid of described the 3rd P-type mos, drain electrode is coupled in the drain electrode of transistorized grid of described the 3rd P-type mos and the described second attached metal oxide semiconductor transistor, and source electrode is coupled in described grid bias power supply.
10. according to claim 9 to voltage, temperature, the insensitive inverter of adjusting overturn point of processing, it is characterized in that: the described second attached metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, and source electrode is coupled in describedly and holds.
11. one kind to voltage, temperature, the insensitive NAND gate of adjusting overturn point of processing, it is characterized in that: it comprises:
One first input end is in order to receive one first input signal;
One second input is in order to receive one second input signal;
One output is in order to export described first input signal and the signal of described second input signal after NAND operation;
One the one N type metal oxide semiconductor transistor, its grid is coupled in described first input end, and source electrode is coupled in a ground end;
One the 2nd N type metal oxide semiconductor transistor, its grid is coupled in described second input, and source electrode is coupled in a described N type metal oxide semiconductor transistor drain, and drain electrode is coupled in described output;
One first P-type mos transistor, its grid is coupled in described first input end, and source electrode is coupled in a grid bias power supply, and drain electrode is coupled in described output;
One second P-type mos transistor, its grid are coupled in described second input, and source electrode is coupled in described grid bias power supply, and drain electrode is coupled in described output; With
One adjustable current source is coupled in described output, and in order to export a sizable electric current to adjust overturn point, wherein: described adjustable current source comprises: an attached metal oxide semiconductor transistor is to reaching a current mirror; Wherein,
Described attached metal oxide semiconductor transistor is right, be coupled in a control voltage source, size in order to the control voltage exported according to described control voltage source is exported one first electric current, described attached metal oxide semiconductor transistor is to comprising: one first attached metal oxide semiconductor transistor, its source electrode is coupled in describedly to be held, and grid is coupled in described control voltage source; With one second attached metal oxide semiconductor transistor, its source electrode is coupled in the drain electrode of the described first attached metal oxide semiconductor transistor, and grid is coupled in described control voltage source;
Described current mirror is coupled between the drain electrode and described output of the described second attached metal oxide semiconductor transistor, in order to produce one second electric current according to described first electric current to described output.
12. according to claim 11 to voltage, temperature, the insensitive NAND gate of adjusting overturn point of processing, it is characterized in that: described current mirror comprises:
One the 3rd P-type mos transistor, its drain electrode is coupled in described output, and source electrode is coupled in described grid bias power supply; With
One the 4th P-type mos transistor, its grid is coupled in the transistorized grid of described the 3rd P-type mos, drain electrode is coupled in the drain electrode of transistorized grid of described the 3rd P-type mos and the described second attached metal oxide semiconductor transistor, and source electrode is coupled in described grid bias power supply.
13. according to claim 12 to voltage, temperature, the insensitive NAND gate of adjusting overturn point of processing, it is characterized in that: described first, second attached metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor.
14. one kind to voltage, temperature, the insensitive NOR gate of adjusting overturn point of processing, it is characterized in that: it comprises:
One first input end is in order to receive one first input signal;
One second input is in order to receive one second input signal;
One output is in order to export described first input signal and the signal of described second input signal after NOR-operation;
One the one N type metal oxide semiconductor transistor, its grid is coupled in described first input end, and its source electrode is coupled in a ground end, and its drain electrode is coupled in described output;
One the 2nd N type metal oxide semiconductor transistor, its grid is coupled in described second input, and its source electrode is coupled in describedly to be held, and its drain electrode is coupled in described output;
One first P-type mos transistor, its grid is coupled in described first input end, and its source electrode is coupled in a grid bias power supply;
One second P-type mos transistor, its grid are coupled in described second input, and its source electrode is coupled in the described first P-type mos transistor drain, and its drain electrode is coupled in described output; With
One adjustable current source is coupled in described output, and in order to export a sizable electric current to adjust overturn point, wherein: described adjustable current source comprises: an attached metal oxide semiconductor transistor is to reaching a current mirror; Wherein,
Described attached metal oxide semiconductor transistor is right, be coupled in a control voltage source, size in order to the control voltage exported according to described control voltage source is exported one first electric current, described attached metal oxide semiconductor transistor is to comprising: one first attached metal oxide semiconductor transistor, its source electrode is coupled in described grid bias power supply, and grid is coupled in described control voltage source; With one second attached metal oxide semiconductor transistor, its source electrode is coupled in the drain electrode of the described first attached metal oxide semiconductor transistor, and grid is coupled in described control voltage source; With
Described current mirror is coupled between the drain electrode and described output of the described second attached metal oxide semiconductor transistor, in order to produce one second electric current according to described first electric current to described output.
15. according to claim 14 to voltage, temperature, the insensitive NOR gate of adjusting overturn point of processing, it is characterized in that: described current mirror comprises:
One the 3rd N type metal oxide semiconductor transistor, its drain electrode is coupled in described output, and source electrode is coupled in describedly and holds; With
One the 4th N type metal oxide semiconductor transistor, its grid is coupled in the transistorized grid of described the 3rd N type metal oxide semiconductor, drain electrode is coupled in the drain electrode of described transistorized grid of the 3rd N type metal oxide semiconductor and the described second attached metal oxide semiconductor transistor, and source electrode is coupled in describedly and holds.
16. according to claim 15 to voltage, temperature, the insensitive NOR gate of adjusting overturn point of processing, it is characterized in that: described first, second attached metal oxide semiconductor transistor is the P-type mos transistor.
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| US20120081165A1 (en) * | 2010-09-30 | 2012-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage tolerative driver |
| CN102446555B (en) * | 2010-10-09 | 2016-01-06 | 旺宏电子股份有限公司 | A kind of storer and using method thereof |
| CN103856207A (en) * | 2012-12-06 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Electrical level switching circuit and electrical level switching method |
| US9172365B2 (en) * | 2013-08-31 | 2015-10-27 | Freescale Semiconductor, Inc. | Method and circuit for controlling turnoff of a semiconductor switching element |
| CN104270144A (en) * | 2014-08-22 | 2015-01-07 | 浙江工业大学 | Three-input general logic gate circuit |
| CN108155901B (en) * | 2016-12-05 | 2023-11-24 | 中国工程物理研究院电子工程研究所 | Parameter drift resistance inverter |
| CN114127915A (en) * | 2019-07-15 | 2022-03-01 | 华为技术有限公司 | Detection circuit and sensor |
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