CN101036117B - 低延时存储器的直接存取 - Google Patents

低延时存储器的直接存取 Download PDF

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CN101036117B
CN101036117B CN2005800334834A CN200580033483A CN101036117B CN 101036117 B CN101036117 B CN 101036117B CN 2005800334834 A CN2005800334834 A CN 2005800334834A CN 200580033483 A CN200580033483 A CN 200580033483A CN 101036117 B CN101036117 B CN 101036117B
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processor
cache memory
instruction
load
memory
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CN101036117A (zh
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格雷格·A·鲍查德
大卫·A·卡尔森
理查德·E·科斯勒
穆罕默德·R·休斯塞恩
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Kaiwei International Co
Marvell Asia Pte Ltd
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Cavium Networks LLC
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Abstract

提供了一种内容识别应用处理系统，用于允许越过高速缓冲存储器直接访问存储在非高速缓冲存储器中的数据。处理器包括高速缓冲存储器的系统接口和非高速缓冲存储器的低延时存储器接口。系统接口用来将由处理器执行的普通加载/存储指令的存储器存取引导到高速缓冲存储器中；低延时存储器系统接口用来将由处理器执行的非普通加载/存储指令的存储器存取引导到非高速缓冲存储器中，从而越过高速缓冲存储器。非普通加载/存储指令可以是协同处理器指令。存储器可以是低延时型存储器。处理器可以包含多个处理器内核。

Description

低延时存储器的直接存取
技术领域
本发明是2004年12月28日提交的第11/024,002号美国专利申请的后继申请，本申请要求2004年9月10日提交的第60/669,672号美国临时专利的权益。上述申请的全部教导在此通过认证并入本文。
背景技术
开放式通信系统互联参考模型(OSI)用来限定在传输媒体上通信的七个网络协议层(L1-L7)。上层(L4-L7)负责端到端的通信，下层(L1-L3)负责本地通信。
网络应用系统需要处理、过滤和交换L3到L7网络协议层，例如，L7网络协议层的超文本传输协议(HTTP)和简单邮件传输协议(SMTP)，L4网络协议层的传输控制协议(TCP)。除处理网络协议层外，网络应用系统需要基于通过L4-L7网络协议层(包括防火墙，虚拟专用网(VPN)，安全套接字协议层(SSL)，入侵检测系统(IDS)，互联网协议安全性(IPSec)，线速的反病毒(AV)and反垃圾邮功能)的安全性来同时保证这些协议的访问和内容。
网络处理器可以提供高吞吐量的L2和L3层上的网络协议处理，也就是说，完成数据包的处理以便以线速度传输数据包。通常，处理L4-L7层网络协议的通用的处理器需要非常智能的处理能力。例如，传输控制协议(TCP)——L4网络协议需要一些加强计算的工作，包括计算信息包在整个有效载荷上的校验和，管理TCP片段缓冲器，和在一个连接中保持多计时器。虽然通用处理器可以完成所述加强计算的工作，但是它不能提供足以处理数据以致能够以网速转发的性能。
而且，内容应用检查数据包中的内容需要在数据流中搜索包含混合字符串和多次重复的特征类的表达式。可以在软件中使用几种搜索算法来运行这种任务。一种算法是确定有限自动机(DFA)。使用DFA搜索算法时有许多局限性，例如，在一个重复模式的数据流中以指数形式增长的图像大小和错误的匹配。
由于这些局限性，内容处理应用需要对模式搜索产生的结果进行足够量的后处理。后处理需要满足对其他连接状态信息的匹配模式，例如连接类型，和数据包中包含的协议标题中的某些值。还需要特定的其它类型的加强计算的限定，例如，一种模式匹配只有在数据流中的某种位置排列时才有效，或被另一种模式所跟随而且与前面的模式在某种排列中或在前面模式特定分支之中或之后。例如，规则表达式匹配把不同的操作符和单个字合并成结构化的复杂表达式。
发明内容
本发明涉及提高处理器完成内容处理请求的速度。处理器包括高速缓冲存储器的系统接口和非高速缓冲存储器的低延时存储器接口。系统接口用来将由处理器执行的普通加载/存储指令的存储器存取引导到高速缓冲存储器中；低延时存储器系统接口用来将由处理器执行的非普通加载/存储指令的存储器存取引导到非高速缓冲存储器中，从而越过高速缓冲存储器。非普通加载/存储指令可以是协同处理器指令。存储器可以是低延时型存储器。处理器可以包含多个处理器内核。
在一个实施方案中，低延时存储器接口可以是将处理器和非高速缓冲存储器内存耦合在一起的总线，耦合允许处理器和非高速缓冲存储器内存之间的直接存取。在另一个具体实施方案中，数据可以在内存中被存储为确定有限自动机(DFA)图来响应处理请求。
在另一个实施方案中，处理器可以包括用于在处理器内核和内存之间传输数据的多个寄存器。多个寄存器可以安装在处理器内。安装在处理器内部的多个寄存器可以和处理器内部的主寄存器区分开来。
在一个实施方案中，低延时存储器可以从动态随机存储器(DRAM)，减少延时动态随机存储器(RLDRAM)，静态随机存储器(SRAM)，快速循环随机存储器(FCRAM)中选择。低延时存储器存取RLDRAM的延时小于或等于30纳秒。
依照本发明的理论，一种网络服务处理器将网络、安全和内容处理器集成在一起。网络服务处理器包括加速内容和安全性处理进程的嵌入式硬件，带有协同处理器模块。
附图说明
本发明的前述和其它方面的特征和优点，从下面更加具体的描述中可以体现出来，如下带标注附图以实例从不同角度展现。附图不是严格依据比例绘制，重点在于用图示说明发明的原理。
图1A是根据本发明的原理的包含网络处理器的网络处理系统框图；
图1B是图1A中显示的网络处理器框图；
图2示了典型的DFA图像；
图3是根据本发明原理的精简指令集计算处理器的框图；
图4示了LLM加载/存储指令格式；
图5显示的是基于本发明的加载/存储操作的实施例。
具体实施方式
本发明的优选的实施方案的描述如下。
图1A是根据本发明原理的包含网络服务处理器110的安全设备100的框图。安全设备110是一种独立的系统，可以将数据包从一个以太网端口(Gig E)转发到另一个以太网端口(Gig E)，对收到的数据包在传递它们之前运行一系列的安全功能。例如，安全设备100能用来在把经过处理的信息包转发到局域网(LAN)之前完成对在广域网(WAN)上收到的信息包的安全处理。
网络服务处理器110包括硬件包处理、缓冲、工作分发、管理、同步和高速缓存支持以加快所有包处理任务。网络服务处理器110处理包括在收到的信息包中的开放式系统互连网络L2-L7层协议。
网络服务处理器110通过物理接口PHY104a、104b接收来自以太网端口(Gig E)的数据包，对接收到的执行L7-L2层网络协议的处理，将处理过的包通过物理接口104a、104b或PCI总线106向前传递。网络协议处理可以包括处理网络安全协议，如防火墙，应用防火墙，包括IP安全性(IPSEC)或安全套接字层(SSL)的虚拟专用网(VPN)，入侵检测系统(IDS)和反病毒(AV)。
网络服务处理器110中的动态随机存储器(DRAM)控制对扩展DRAM 108的访问，其与网络服务处理器110耦合。DRAM108储存从物理接口104a，104b或可扩展外部设备互联(PCI-X)接口106接收到的数据包以供网络服务处理器110处理。
网络服务处理器110中的低延时存储控制器控制低延时存储器(LLM) 118。LLM 118可以被网络服务或安全设备使用进行快速查询，包括可能是入侵检测系统(IDS)或反病毒(AV)设备所需要的规则表达式匹配。
规则表达式是表示字符串匹配模式的一种通同方法。规则表达式的原子元素是要被匹配的单个字符。这些元素与元字符操作符合并允许用户表示连接，交替，星号等等。当使用交替来(|)创建可以匹配两个或更多子字符串中的任何一个时，连接用来创建混合字符匹配模式从一个单特征(或子字符串)。星号(*)允许一种模式匹配零(0)或在一个字符串中存在的更多模式。合并不同的操作符和单独字母们允许结构化的的复杂表达式。例如，表达式th(is|at)*)会匹配th，this，that，thisis，thisat，thatis，thatat，等等。
图1B是图1A中所示网络服务处理器110的框图。网络服务处理器110使用结合图1A描述的至少一个处理器核心120递送高的应用性能。通过一个SPI-4.2或RGMII接口，GMX/SPX单元122a，122b中的某一个收到要处理的数据包。GMX/SPX单元(122a，122b)对接收的包进行L2层网络协议标题中各种范围检查的预请求，然后传递包到包输入单元126。
数据包输入单元126对包含在接收到的包中的网络协议标题(L3层和L4层)进行进一步的预处理。这个预处理包括对传输控制协议(TCP)/用户数据包协议(UDP)(L3层网络协议)的校验和检查。
一种自由池分配器(FPA)128保持二级缓冲存储器130和DRAM 108的自由存储的指针池。数据包输入单元126使用一个指针池来存储接收到的分组数据在二级缓冲存储器130或DRAM 108，另一个指针池来分配进入处理器内核120的工作队列。
然后，数据包输入单元126以一种便于在多于一个处理器内核120中执行的更高层软件的格式将分组数据写入二级缓冲存储器130或DRAM 108的缓冲区中。
网络服务处理器110包括专用的协同处理器，代替了处理器内核120，所以网络服务处理器达到了高的吞吐量。压缩/解压缩协同处理器132对接收的数据包进行压缩和解压缩的处理。在一个实施方案中，一种确定有限自动机模块(没有表示出来)可以包括DFA引擎，用于加速特性曲线和特征与反病毒(AV)，侵入窃密检测(IDS)和其他包含处理请求的必要的匹配，速度可达4Gb每秒。
一种I/O接口(IOI) 136管理总的协议和分配，提供连贯的I/O分割。IOI 136包括I/O桥(IOB)138和取和加单元(FAU)140。FAU140中的寄存器用来保持输出队列的长度，传递处理过的包通过包输出单元126。IOB 138包括缓冲队列，保存在I/O总线142，高速存储器总线144，包输入单元126和包输出单元146之间传递的信息。
包次序/工作(POW)模块148为处理器内核120排列和分配工作。在进入一个队列中增加一个工作队列来排列工作。  例如，数据包输入单元126在每个数据包到达时增加一个工作队列进入。计时器150用来为处理器内核分配工作。
处理器内核120从POW模块148中请求工作。POW模块148为处理器选择(例如，分配)工作，并返回一个指针到工作队列入口向处理器内核120描述工作。
处理器内核120包括指令缓冲152，一级(L1)数据缓冲154和加密加速156。在一个实施方案中，网络服务处理器110包含16个超级标量RISC(精简指令集计算)型处理器内核120。在一个实施方案中，每个超级标量RISC型处理器内核120是MIPS64处理器内核第二版的扩展。
二级(L2)缓冲存储器130和DRAM 108由所有处理器内核120和I/O同步处理器设备共享使用。每个处理器内核120通过高速存储器总线144配给二级缓冲存储器130。在处理器内核100，IOB 136和二级缓冲存储器130和二级缓冲存储器131之间，高速存储器总线144是所有存储器和I/O事务的通讯通道。在一个实施方案中，高速存储器总线144可以达到16个处理器内核120，通过高缓冲和优先列入I/O支持完全连续一级数据缓冲154的写入。
二级缓冲存储控制器131保持存储引用的一致性。无论块是存储在二级缓冲存储器130，DRAM 108或在传输中，它都返回每个请求块的最新拷贝。在每个处理器内核120中，它还保存了数据缓冲154的标志的副本。它对缓冲块存储的请求和数据缓冲标记进行比较，当从另一个处理器内核或一个I/O组件通过IOI136传来的存储指令时，将处理器内核120的数据缓冲标志设为无效(所有拷贝)。
一种DRAM控制器133支持16兆的DRAM。DRAM控制器133支持DRAM 108的64比特或128比特的接口。DRAM控制器133支持DDR-I(双倍数据速率)和DDR-II协议。
在数据包被处理器内核120处理后，数据包输出单元(PKO)146从存储器读取分组数据，运行L4层网络协议后处理(例如，产生TCP/UDP检查和)，通过GMX/SPC单元122a，122b将数据包向前传递，释放数据包使用的二级缓冲130/DRAM 108。
低延时存储控制器160管理传递中的事务(读取/存储)到/从LLM 118。低延时存储器(LLM) 118由所有的处理器内核120共享使用。LLM 118可以是动态随机访问存储器(DRAM)，减少延时动态随机访问存储器(RLDRAM)，同步随机访问存储器(SRAM)，快速循环随机访问存储器(FCRAM)，或者任何其它类型的低延时存储器。RLDRAM提供30纳秒的存储器延时或更好，也就是，时间用来满足处理器120发起的存储器请求。每个处理器内核120通过低延时存储器总线158直接与LLM控制器160耦合。低延时存储器总线158是处理器内核120和LLM控制器160之间内容应用处理的通讯通道。LLM控制器160在处理器内核120和LLM 118之间耦合，用来控制对LLM 118的访问。
内容识别应用处理利用存储在LLM 118里的模式/表达式(数据)。模式/表达式可以是确定有限自动机(DFA)形式。DFA是一种状态机器。DFA状态机的输入是一个8位字节字符串(例如，DFA的字母是一个字节)。每个输入字节使状态机从一个状态转变为下一个状态。图2A中图示的图像200可以表示出状态和转变功能，每个图像节点(210a...210c)是一个状态，弧线(220a...220d)表示不同输入字节的状态过渡。状态可以包含状态相关的字符，例如“A...Z，a...z，0...9，”等等。状态机的当前状态是一个节点标识符用来选择一个特定的图像节点。例如，假定输入包含文本“Richard”。当读到“R”时，DFA从初始状态1(210a)移动到状态2(210b。对于接下来的五个字符，“i”“c”“h”“a”“r”“d”，DFA继续循环(220b)到状态2。
图3A是根据本发明原理的精简指令集计算(RISC)处理器的框图。处理器(处理器内核)120包括集成执行单元302，指令分配单元304，指令获取单元306，存储器管理单元(MMU)308，系统接口310，低延时接口350，加载/保存单元314，写缓冲316和安全加速器156。处理器内核120还包括允许执行调试操作的EJTAG接口330。系统接口310控制对扩展存储器的访问，也就是，处理器120的扩展存储器，例如，扩展二级缓冲存储器130或者首/主存储器108。
集成执行单元302包括乘法器单元326，至少一个寄存器文件(主寄存器文件)328和两个保持寄存器330a，330b。保持寄存器330a和330b用来保存要写入LLM 118的数据和使用LLM加载/保存指令从LLM 118中读出的数据。通过在流水线延迟之前允许两个未决负载，保持寄存器330a和330b提高了指令流水线的效率。虽然显示了两个保持寄存器，但可能使用一个或多个保持寄存器。乘法器326有64位直接寄存乘法器。指令读取单元306包括指令缓冲(ICache)152。加载/保存单元314包括数据缓存154。在一个实施方案中，指令缓存152是32K字节，数据缓存154是8K字节，写入缓冲器316是2K字节。存储器管理单元308包括翻译后援缓冲器(TLB)340。
在一个实施方案中，处理器120包括加密加速模块(安全加速器)156，包括对三重数据加密标准(3DES)，高级加密标准(AES)，安全散列算法(SHA-I)，信息摘要算法#5(MD5)密码体系的加速。加密加速器模块156通过在执行单元302中移动到和从主寄存器文件328进行通讯。在乘法器单元326中运行RSA和Diffie-Hellman(DH)算法。
图4指示说明了内核120用来访问LLM 118的LLM加载/存储指令格式410。这些加载/存储指令格式不同与通用的加载/存储指令，通用的加载/存储指令将数据加载/存储在主寄存器328和高速缓冲存储器系统之间，包括L1数据高速缓冲存储器154，L2高速缓冲存储器130，和DRAM 108(图3)。相反的，这些新的指令启动了64位或36位加载/存储，直接来自/到LLC 118到内核120。这些指令允许数据被找回/存储在LLM存储器118里，比通过高速缓存相干的存储系统要快。从LLM加载/存储指令到低延时存储器118之间道路的开辟，改进了应用程序的性能，不需要高速缓存了，例如，匹配正则表达式。这些加载/存储指令是“DMTC2”  (加倍移动到协同处理器)的和“DMFC2”(协同处理器的加倍移动)的。
参照图4，COP2字段412指明了这条指令是协同处理指令。(例如，不是通用的指令)。DMT/DMF字段414存储了操作码(例如，指明指令的类型)。指令类型DMT表示数据是从低延时存储器118到保持寄存器(330a，330b)。指令类型DMF表示数据从保持寄存器(330a，330b)到主寄存器字段载入的寄存器。在一个实施方案中，低延时存储器118是36位宽，每个DMT/DMF指令允许36位移动。DMT/DMF字段416在主寄存器字段限定了寄存器。与操作码相关的执行字段418，限定了协同处理器移动指令的类型，还限定了保持寄存器330a，330b。
为加载(DMF)保持寄存器的目录到主寄存器文件338中的寄存器，rt字段识别寄存器文件中的寄存器，存储在保持寄存器里的数据存储在这里。例如：
GPR[rt]＝LLM_DATA0<63:0>，其中
LMM_DATA0是保持寄存器330a；以及
GPR是通用寄存器。
对于写指令(DMT)，rt字段(416)限定在寄存器文件里存储低延时存储器118位置地址的寄存器。例如：
LLM_DATA0<63：0>＝llmemory[rt]，其中
LMM_D ATA0是保持寄存器330a；
llmemory是低延时存储器。
例如可以使用下面的低延时存储器加载指令(DMTC2)来加载内容是低延时存储器位置指令的保持寄存器330a，例如：
DMTC2，$5，0x0400
DMT是指令类型，例如从低延时存储器(414)加载保持寄存器；
C2(COP2)指示协同处理器指令(412)；
主寄存器文件328(图3)中的寄存器#5保持低延时存储器的地址；以及
0x0400标识保持寄存器330(图3)(418)(这个值是常量，在其它具体实施方案中可以不同)。
同样的，可以使用低延时存储器存储指令将保持寄存器330中的数据移动入主寄存器文件328(图3)。例如，可以使用下面的低延时存储器存储指令：
DMFC2，$6，0x0402
DMF是指令类型，例如存储寄存器$6中的保持寄存器的内容到主寄存器文件328(414)；
C2(COP2)表示协同处理器指令(412)；
主寄存器文件328中的寄存器#6是目的寄存器(rt)(416)；以及
0x0402标识保持寄存器330(图3)(418)(这个值是一个常量，在其它具体实施方案中可以不同)。
上面是通过实例显示的指令格式，应该会被对指令格式熟悉的理解，可以是非普通加载/存储指令允许的任何格式。
图5显示根据本发明使用非普通加载指令从LLM存储器位置加载数据到寄存器文件的寄存器中。使用非普通加载指令来加载LLM地址到主寄存器文件328中的寄存器6($6)中，使用下面的指令序列：
DMTC2$5，Cl(Cl是常量值，例如，0x0400)；
DMFC2$6，C2(C2是常量值，例如0x0402)。
源自低延时寄存器118中的地址(位置)的加载数据先存储在主寄存器文件328的寄存器5($5)中。″DMTC2$5，0x0400″指令从通过存储在寄存器5中地址标识位置的LLM118中读取数据到保持寄存器330a中。然后，″DMFC2$6，0x0402″指令加载存储在保持寄存器330a中的数据到主寄存器文件328的$6中。通过使用LLM总线158，这些指令有效的越过所有的缓冲。
通过改变C1、C2的值可以使用保持寄存器330b代替保持寄存器330a。例如，C1＝0x0408可以改变为C2＝0x040a。
虽然本发明已经对关于其优选的实施方式进行了具体的描述和介绍，但本领域技术人员应当理解，在不脱离本发明所附权利要求保护的范围的情况下，本发明在形式和细节上可以进行多种改变。

Claims (18)

1.一种处理器，该处理器包括：
高速缓冲存储器的系统接口，用来将由处理器执行的普通加载/存储指令的存储器存取引导到高速缓冲存储器；以及
非高速缓冲存储器的低延时存储器接口，用来将由处理器执行的非普通加载/存储指令的存储器存取引导到非高速缓冲存储器中，从而越过高速缓冲存储器，
其中普通加载/存储指令是用于加载/存储数据从/到高速缓冲存储器的指令，而非普通加载/存储指令是用于直接加载/存储数据从/到非高速缓冲存储器的指令。
2.根据权利要求1的处理器，其中低延时存储器接口是耦合在处理器和非高速缓冲存储器之间的总线，所述耦合允许处理器和非高速缓冲存储器间的直接访问。
3.根据权利要求1的处理器，其中非普通加载/存储指令是协同处理器指令。
4.根据权利要求1的处理器，进一步包括用来在低延时存储器接口和非高速缓冲存储器间移动数据的多个寄存器。
5.根据权利要求4的处理器，其中多个寄存器都位于处理器的执行单元中。
6.根据权利要求5的处理器，其中多个寄存器与位于处理器执行单元内的主寄存器文件是分离的。
7.根据权利要求4的处理器，其中数据存储在为完成内容应用处理的非高速缓冲存储器中的确定有限自动机图像中。
8.根据权利要求1的处理器，其中非高速缓冲存储器是低延时存储器。
9.根据权利要求8的处理器，其中低延时存储器是从由动态随机访问存储器、减少延时动态随机访问存储器、静态随机访问存储器和快速循环随机访问存储器组成的组中选择的。
10.根据权利要求9的处理器，其中动态随机访问存储器的延迟时间少于或等于20纳秒。
11.根据权利要求1的处理器，进一步包括多个处理器内核。
12.一种在处理器和非高速缓冲存储器之间直接访问的方法，该方法包括：
通过高速缓冲存储器的系统接口将由处理器执行的普通加载/存储指令的存储器存取引导到高速缓冲存储器；以及
通过非高速缓冲存储器的低延时存储器接口将由处理器执行的非普通加载/存储指令的存储器存取引导到非高速缓冲存储器，从而越过高速缓冲存储器，
其中普通加载/存储指令是用于加载/存储数据从/到高速缓冲存储器的指令，而非普通加载/存储指令是用于直接加载/存储数据从/到非高速缓冲存储器的指令。
13.根据权利要求12的方法，其中非普通加载/存储指令是协同处理器指令。
14.根据权利要求12的方法，其中数据存储在为完成内容应用处理的非高速缓冲存储器中的确定有限自动机图像中。
15.根据权利要求12的方法，其中非高速缓冲存储器是低延时存储器。
16.根据权利要求15的方法，其中低延时存储器是从由动态随机访问存储器、减少延时动态随机访问存储器、静态随机访问存储器和快速循环随机访问存储器组成的组中选择的。
17.根据权利要求16的方法，其中处理器以少于或等于20纳秒的延时访问动态随机访问存储器。
18.一种在处理器和非高速缓冲存储器之间直接访问的装置，该装置包括：
装置，其用于将由处理器执行的普通加载/存储指令的存储器存取通过高速缓冲存储器的系统接口引导到高速缓冲存储器中；以及
装置，其用于将由处理器执行的非普通加载/存储指令的存储器存取通过非高速缓冲存储器的低延时存储器接口引导到非高速缓冲存储器中，从而越过高速缓冲存储器，
其中普通加载/存储指令是用于加载/存储数据从/到高速缓冲存储器的指令，而非普通加载/存储指令是用于直接加载/存储数据从/到非高速缓冲存储器的指令。
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