CN101044727A - 使用直插式信用扩充器与主机总线适配器的方法及系统 - Google Patents

使用直插式信用扩充器与主机总线适配器的方法及系统 Download PDF

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CN101044727A
CN101044727A CNA2005800329484A CN200580032948A CN101044727A CN 101044727 A CN101044727 A CN 101044727A CN A2005800329484 A CNA2005800329484 A CN A2005800329484A CN 200580032948 A CN200580032948 A CN 200580032948A CN 101044727 A CN101044727 A CN 101044727A
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奥斯卡·L·格里哈尔瓦
杰拉尔德·K·奥尔斯顿
埃里克·R·格里菲思
詹姆斯·A·孔兹
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QLogic LLC
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    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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Abstract

本发明提供一种存储区域网络(“SAN”)及一种系统。所述SAN包括与信用扩充器在操作上耦接的主机总线适配器，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间来将所接收到的帧发送至所述HBA。所述HBA将所述信用扩充器中的可用缓冲器空间通知其他光纤信道端口。所述HBA向所述信用扩充器发送信号，以将所述HBA中的可用缓冲器空间通知所述信用扩充器。所述HBA包括一用于将所述HBA与所述信用扩充器介接的管理端口。

Description

使用直插式信用扩充器与主机总线适配器的方法及系统
技术领域
本发明涉及联网系统，且更具体而言涉及将主机总线适配器与直插式信用扩充器相耦接。
背景技术
存储区域网络(“SAN”)通常在有多个存储器存储装置可供用于各种主机计算系统时使用。SAN中的数据通常通过各种控制器/适配器自多个主机系统移至存储系统。
主机系统通常包括数个功能组件。这些组件可包含中央处理器(CPU)、主存储器、输入/输出(“I/O”)装置及流式存储装置(例如磁带驱动器)。在常规系统中，主存储器经由系统总线或局部存储器总线耦接至CPU。主存储器用于使CPU在执行时能够存取存储于主存储器中的数据及/或程序信息。通常，主存储器由随机存取存储器(RAM)电路构成。具有CPU及主存储器的计算机系统通常称作主机系统。
主机系统通常使用“PCI”总线接口经由主机总线适配器(“HBA”，亦可称作“控制器”及/“适配器”)来与存储系统通信。PCI代表外围组件互连(Peripheral ComponentInterconnect)，其是一种由Intel Corporation开发的局部总线标准。PCI标准以引用方式全文并入本文中。
PCI-X为与使用PCI总线的现有PCI卡兼容的另一标准总线。PCI-X提高了PCI的数据传送速率。
还使用各种其他标准接口来将数据自主机系统移至存储装置。光纤信道(FiberChannel)即为一种这样的标准。光纤信道(其以引用方式全文并入本文中)为一组美国国家标准协会(ANSI)标准，其为存储及网络协议(例如HIPPI、SCSI、IP、ATM及其他协议)提供串行传输协议。光纤信道提供输入/输出接口来满足信道及网络用户二者的要求。
光纤信道支持三种不同的拓扑：点对点、仲裁环路及光纤信道结构。点对点拓扑直接附接两个装置。仲裁环路拓扑以环路形式附接各装置。光纤信道结构拓扑则将主机系统直接附接至结构上，然后将各主机系统连接至多个装置。光纤信道结构拓扑允许互连多个媒体类型。
光纤信道是一种封闭系统，其依靠多个端口来交换关于属性及特性的信息，以确定各端口是否可一起运行。如果各端口可一起工作，则所述端口规定其用以进行通信的标准。在光纤信道中，在两个节点之间建立路径，其中路径的主要任务是将数据自一个点输送至另一个点。
光纤信道结构装置包括用于管理结构连接的节点端口或“N_端口”。N_端口建立接至具有结构端口或F_端口的结构元件(例如开关)的连接。
在光纤信道中，使用缓冲器-缓冲器信用机制来控制光纤信道链路上的帧流。此种机制需要发射机在发送帧前以R_RDY基元形式接收信用。目的地只有在其具有足以接受完整帧的缓冲器空间时才发送R_RDY。
一旦发射机针对其所接收到的每一R_RDY发送出帧，其便停止传输，直至另一R_RDY自目的地到达为止。除非发射机接收到足以覆盖使帧通过链路传播至目的地及R_RDY通过所述链路自目的地返回所需的时间的R_RDY，否则发射机会停止并等待R_RDY。
数据通量随着光纤信道链路的长度在距离上的增加而受到阻碍。在传统系统中，使用附加数据缓冲来允许发送更多的R_RDY并使空闲周期最小化。此解决方式具有缺点。例如，当用于只使用短链路的环境中时，具有大缓冲器的装置会浪费存储资源。此外，使用外部存储器缓冲器代价高昂且需要附加的引脚及数据端口。
因此，需要一种能实现有效数据传送而不永久地使用附加存储器缓冲器的系统。
发明内容
在本发明的一个方面中，提供一种存储区域网络(“SAN”)。所述SAN包括与信用扩充器在操作上耦接的主机总线适配器，其中所述信用扩充器自光纤信道网络接收帧并根据HBA中的可用缓冲器空间将所接收到的帧发送至HBA。所述HBA将所述信用扩充器中的可用缓冲器空间通知其他光纤信道端口。所述HBA向所述信用扩充器发送信号，以将所述HBA中的可用缓冲器空间通知所述信用扩充器。
在本发明的另一个方面中，提供一种用于在光纤信道网络中传送数据的系统。所述系统包括与信用扩充器在操作上耦接的HBA，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间来将所接收到的帧发送至所述HBA。
在本发明的再一个方面中，提供一种HBA。所述HBA包括用于将所述HBA与信用扩充器介接的管理端口，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间将所接收到的帧发送至所述HBA。
提供此简要说明旨在使人们可更快地理解本发明的性质。结合附图参阅下文对本发明较佳实施例的详细说明，可实现对本发明的更全面理解。
附图说明
现将参考较佳实施例的图式来阐述本发明的上述特征及其他特征。在图式中，相同组件具有相同参考编号。所显示的实施例仅旨在图解说明而非限定本发明。所述图式包含下列各图：
图1A显示一使用SAN的网络的顶层方块图；
图1B显示一根据本发明一个方面与信用扩充器介接的HBA的顶层图；
图2显示一根据本发明一个方面在信用扩充器与HBA之间具有介接信号的方块图；及
图3显示一根据本发明一个方面用于介接信用扩充器与HBA的过程流程图。
具体实施方式
定义：
提供下述定义，因为其通常(但不具有排他性)在构建本发明各个自适应性方面的光纤信道环境中使用。
“光纤信道ANSI标准”：该标准(其以引用方式全文并入本文中)描述用于支持与IPI、SCSI、IP、ATM及其他标准相关联的其他高级协议的高性能串行链路的物理接口、传输及信令协议。
“N_端口”：直接光纤附接端口，例如磁盘驱动器或HBA。
“SAN”：存储区域网络
为便于理解所述较佳实施例，将阐述SAN及HBA的通用架构及操作。然后，将参照主机系统及HBA的通用架构来阐述所述较佳实施例的具体架构及操作。
图1A显示SAN系统100，SAN系统100使用HBA 106(亦称作“适配器106”)，以用于使用光纤信道存储区域网络114及115在具有主机存储器101的主机系统(例如图2中的200)与各种装置/系统(例如存储子系统116及121、磁带库118及120及服务器117及119)之间进行通信。主机系统200使用驱动器102，驱动器102使用输入/输出控制块(“IOCB”)经由适配器106来协调数据传送。
请求队列103及响应队列104保持在主机存储器101中，以便使用适配器106来传送信息。如图1B中所示，主机系统200通过PCI核心模块(接口)137经由PCI总线105来与适配器106进行通信。
在传统系统中，使用附加缓冲器108A来提高远距离情况下的链路通量，而此会造成浪费。
HRA 106：
图1B显示一根据本发明一个方面所使用的适配器106的方块图。适配器106包括分别用于在传输及接收路径中处理数据的传输及接收侧处理器(其亦可称作“序列发生器”)112及109。传输路径在此上下文中是指自主机存储器101经由适配器106至存储系统的数据路径。接收路径是指经由适配器106来自存储子系统的数据路径。值得注意的是，对接收及传输路径使用仅一个处理器，且本发明并不仅限于任一特定的处理器数量/类型。缓冲器111A及111B分别用来在接收及传输路径中存储信息。
HBA 106在接收路径中在操作上耦接至光纤信道信用扩充器146。来自光纤信道网络的帧流量146A进入信用扩充器146并随后发送至HBA 106的接收路径(其显示成146B)。
信用扩充器146及其各种组件阐述于2002年6月10日提出申请的第10/166570号及2003年9月9日提出申请的第10/664,548号美国专利申请案中；这两个申请案的揭示内容以引用方式全文并入本文中。下面的图2详细阐述HBA 106与信用扩充器146之间的交互作用。
除接收及传输路径上的专用处理器外，适配器106还包括处理器106A，处理器106A可为用于在适配器106中实施各种功能的简化指令集计算机(“RISC”)。
适配器106还包括光纤信道接口(亦称作光纤信道协议管理器“FPM”)113A，光纤信道接口113A包括分别位于接收及传输路径中的FPM 113B及113(其在图1B中显示为FC RCV及FC XMT)。FPM 113A及FPM 113使数据能够移至/来自其他装置(未显示)。
适配器106还通过局部存储器接口122(分别经由连接线116A及116B(图1A))耦接至外部存储器108及110(其在下文中可互换地加以指代)。局部存储器接口122提供用来管理局部存储器108及110。局部DMA模块137A用于获取存取权以自局部存储器(108/110)移动数据。
适配器106还包括用于将数据从10位串行格式变换至8位并行格式及进行相反变换的串行/反串行器(“SERDES”)。
适配器106进一步包括：与请求队列103及响应队列104介接的请求队列DMA信道(0)130、响应队列DMA信道131、请求队列(1)DMA信道132；及用于管理命令信息的命令DMA信道133。
接收及传输路径二者分别具有DMA模块129及135。传输路径还具有耦接至处理器112并对传输操作进行调度的调度器134。仲裁器107在多个DMA信道请求之间进行仲裁。
图2显示一在HBA 106与信用扩充器146之间具有各种接口信号的方块图，其中将来自HBA 106的传输路径显示成146C。HBA 106可存取静态随机访问存储器(“SRAM”)108B、闪速存储器108C及电可擦可编程只读存储器(“EEPROM”)108D，以执行各种可编程指令/代码。
HBA 106使用最少数量的管理端口来连接至信用扩充器146。在本发明的一个方面中，使用为一种标准协议的管理数据输入输出(“MDIO”)协议。所述MDIO协议/标准以引用方式全文并入本文中。管理端口201用于使用信号202及203来与信用扩充器146介接。
信用扩充器146接收入局帧146A。信用_调整(Credit_Adjust)信号204自HBA106发送至信用扩充器146，以传达HBA 106具有可供用于帧的缓冲器(即准许信用扩充器146在接收路径中传输帧)。信用扩充器146接收信号204，使信号204与其本身的参考时钟同步并随后验证信号204。信号204对时间敏感且每当在HBA 106中腾出帧缓冲器时其便在低至高与高至低跃迁之间双态切换。信号204双态切换的速率决定帧可如何快地自信用扩充器移至HBA 106。
信用扩充器146向HBA 106发送ATTN信号205。信号205指示已出现需要HBA106进行管理干预的例外情况。在本发明的一个方面中，信号205保持为高，直至被来自HBA 106的响应(其是经由信号203接收到)清除为止。由于信号205保持为高，因此其使HBA 106能够使信号205同步、识别并响应于信号205。由于信号205只有在例外情况下才得到确定，因此此机制不影响HBA 106在有利于数据传送方面的总体性能。
在初始化期间，由固件(RISC 106A及其他模块所使用的软件)来设置HBA 106。所述设置指示在信用扩充器146中可供使用的缓冲器空间量。当HBA 106与另一个光纤信道端口连接时，HBA 106根据信用扩充器146的缓冲容量，使用R_RDY基元来传输可用信用的数量。
图3显示一用于将信用扩充器146与HBA 106一起使用的过程流程图。在步骤300中，由固件设置HBA 106。在设置期间，HBA 106确定(或知道)信用扩充器146中可供使用的缓冲器空间量。
在步骤S302中，HBA 106将可用缓冲器空间通知其他光纤信道端口(使用R_RDY基元)。此使其他端口能够根据信用扩充器146的缓冲器容量将数据发送至HBA 106。
在步骤S304中，HBA 106将可供用于接收/处理帧的缓冲器空间通知信用扩充器146。
在步骤S306中，信用扩充器146将帧发送到HBA 106。在步骤S308中，RSEQ 109处理所述帧。
在本发明的一个方面中，使用信用扩充器146会消除对附加数据端口/缓冲器的需要并减小光纤信道传输中的总等待时间。
尽管已参考特定实施例阐述了本发明，然而这些实施例仅为例示性而非限定性实施例。根据此揭示内容及上文权利要求书，本发明的诸多其他应用及实施例将显而易见。例如，除SAN及光纤信道标准外，也可使用自动DMA选择。上述自适应性方面适用于其中在链路传送速率之间存在不一致性的任何联网环境。

Claims (12)

1、一种存储区域网络(“SAN”)，其包括：
与信用扩充器在操作上耦接的主机总线适配器(HBA)，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间将所述所接收到的帧发送至所述HBA。
2、如权利要求1所述的SAN，其中所述HBA将所述信用扩充器中的可用缓冲器空间通知其他光纤信道端口。
3、如权利要求1所述的SAN，其中所述HBA向所述信用扩充器发送信号，以将所述HBA中的可用缓冲器空间通知所述信用扩充器。
4、如权利要求1所述的SAN，其中所述信用扩充器将例外情况通知所述HBA。
5、一种用于在光纤信道网络中传送数据的系统，其包括：
与信用扩充器在操作上耦接的主机总线适配器(HBA)，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间将所述所接收到的帧发送至所述HBA。
6、如权利要求5所述的系统，其中所述HBA将所述信用扩充器中的可用缓冲器空间通知其他光纤信道端口。
7、如权利要求5所述的系统，其中所述HBA向所述信用扩充器发送信号，以将所述HBA中的可用缓冲器空间通知所述信用扩充器。
8、如权利要求5所述的系统，其中所述信用扩充器将例外情况通知所述HBA。
9、一种主机总线适配器(“HBA”)，其包括：
用于将所述HBA与信用扩充器介接的管理端口，其中所述信用扩充器自光纤信道网络接收帧并根据所述HBA中的可用缓冲器空间将所述所接收到的帧发送至所述HBA。
10、如权利要求9所述的HBA，其中所述HBA将所述信用扩充器中的可用缓冲器空间通知其他光纤信道端口。
11、如权利要求9所述的HBA，其中所述HBA向所述信用扩充器发送信号，以将所述HBA中的可用缓冲器空间通知所述信用扩充器。
12、如权利要求9所述的HBA，其中所述信用扩充器将例外情况通知所述HBA。
CN2005800329484A 2004-10-01 2005-09-27 使用直插式信用扩充器与主机总线适配器的方法及系统 Expired - Fee Related CN101044727B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106415513A (zh) * 2014-06-26 2017-02-15 英特尔公司 用于分组发送的优化的信用返回机制

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7877466B2 (en) * 2005-01-11 2011-01-25 Cisco Technology, Inc. Network topology based storage allocation for virtualization
US7406546B1 (en) * 2005-08-17 2008-07-29 Nvidia Corporation Long-distance synchronous bus

Family Cites Families (148)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4162375A (en) 1972-03-23 1979-07-24 Siemens Aktiengesellschaft Time-divison multiplex switching network with spatial switching stages
US4268906A (en) 1978-12-22 1981-05-19 International Business Machines Corporation Data processor input/output controller
US4783739A (en) 1979-11-05 1988-11-08 Geophysical Service Inc. Input/output command processor
US4333143A (en) 1979-11-19 1982-06-01 Texas Instruments Input process sequence controller
GB2074815B (en) 1980-04-24 1984-06-27 Plessey Co Ltd Telecommunications switching network using digital switching modules
US4382159A (en) 1981-05-29 1983-05-03 Bowditch Robert S Blow actuated microphone
US4449182A (en) 1981-10-05 1984-05-15 Digital Equipment Corporation Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
US4475192A (en) 1982-02-16 1984-10-02 At&T Bell Laboratories Data packet flow control scheme for switching networks
US4777595A (en) 1982-05-07 1988-10-11 Digital Equipment Corporation Apparatus for transferring blocks of information from one node to a second node in a computer network
US4546468A (en) 1982-09-13 1985-10-08 At&T Bell Laboratories Switching network control circuit
US4549263A (en) 1983-02-14 1985-10-22 Texas Instruments Incorporated Device interface controller for input/output controller
US4569043A (en) 1983-06-22 1986-02-04 Gte Automatic Electric Inc. Arrangement for interfacing the space stage to the time stages of a T-S-T digital switching system
US4725835A (en) 1985-09-13 1988-02-16 T-Bar Incorporated Time multiplexed bus matrix switching system
US4783730A (en) 1986-09-19 1988-11-08 Datapoint Corporation Input/output control technique utilizing multilevel memory structure for processor and I/O communication
US4821034A (en) 1987-02-06 1989-04-11 Ancor Communications, Inc. Digital exchange switch element and network
US5276807A (en) 1987-04-13 1994-01-04 Emulex Corporation Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking
US4803622A (en) 1987-05-07 1989-02-07 Intel Corporation Programmable I/O sequencer for use in an I/O processor
US5129064A (en) 1988-02-01 1992-07-07 International Business Machines Corporation System and method for simulating the I/O of a processing system
US5144622A (en) 1988-02-15 1992-09-01 Hitachi, Ltd. Network system
US5212795A (en) 1988-10-11 1993-05-18 California Institute Of Technology Programmable DMA controller
US5321816A (en) 1989-10-10 1994-06-14 Unisys Corporation Local-remote apparatus with specialized image storage modules
US5249279A (en) 1989-11-03 1993-09-28 Compaq Computer Corporation Method for controlling disk array operations by receiving logical disk requests and translating the requests to multiple physical disk specific commands
US5347638A (en) 1991-04-15 1994-09-13 Seagate Technology, Inc. Method and apparatus for reloading microinstruction code to a SCSI sequencer
EP0551191B1 (en) 1992-01-09 2000-04-12 Cabletron Systems, Inc. Apparatus and method for transferring data to and from host system
US5371861A (en) 1992-09-15 1994-12-06 International Business Machines Corp. Personal computer with small computer system interface (SCSI) data flow storage controller capable of storing and processing multiple command descriptions ("threads")
US5367520A (en) 1992-11-25 1994-11-22 Bell Communcations Research, Inc. Method and system for routing cells in an ATM switch
US5448702A (en) 1993-03-02 1995-09-05 International Business Machines Corporation Adapters with descriptor queue management capability
US5412653A (en) * 1993-10-15 1995-05-02 International Business Machines Corporation Dynamic switch cascading system
GB9401092D0 (en) 1994-01-21 1994-03-16 Newbridge Networks Corp A network management system
GB9408574D0 (en) 1994-04-29 1994-06-22 Newbridge Networks Corp Atm switching system
US6049802A (en) 1994-06-27 2000-04-11 Lockheed Martin Corporation System and method for generating a linked list in a computer memory
US5633867A (en) 1994-07-01 1997-05-27 Digital Equipment Corporation Local memory buffers management for an ATM adapter implementing credit based flow control
US5568614A (en) 1994-07-29 1996-10-22 International Business Machines Corporation Data streaming between peer subsystems of a computer system
US5828903A (en) 1994-09-30 1998-10-27 Intel Corporation System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
US5598541A (en) 1994-10-24 1997-01-28 Lsi Logic Corporation Node loop port communication interface super core for fibre channel
KR0132944B1 (ko) 1994-12-23 1998-04-21 양승택 데이터 교환장치
US5761427A (en) 1994-12-28 1998-06-02 Digital Equipment Corporation Method and apparatus for updating host memory in an adapter to minimize host CPU overhead in servicing an interrupt
US5687172A (en) 1994-12-30 1997-11-11 Lucent Technologies Inc. Terabit per second distribution network
US5528591A (en) 1995-01-31 1996-06-18 Mitsubishi Electric Research Laboratories, Inc. End-to-end credit-based flow control system in a digital communication network
DE69614291T2 (de) 1995-03-17 2001-12-06 Lsi Logic Corp (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5706279A (en) 1995-03-24 1998-01-06 U S West Technologies, Inc. Methods and systems for managing packet flow into a fast packet switching network
US5623492A (en) 1995-03-24 1997-04-22 U S West Technologies, Inc. Methods and systems for managing bandwidth resources in a fast packet switching network
US5701416A (en) 1995-04-13 1997-12-23 Cray Research, Inc. Adaptive routing mechanism for torus interconnection network
US5729762A (en) 1995-04-21 1998-03-17 Intel Corporation Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
US5664197A (en) 1995-04-21 1997-09-02 Intel Corporation Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller
US5917723A (en) 1995-05-22 1999-06-29 Lsi Logic Corporation Method and apparatus for transferring data between two devices with reduced microprocessor overhead
US5956342A (en) 1995-07-19 1999-09-21 Fujitsu Network Communications, Inc. Priority arbitration for point-to-point and multipoint transmission
US5748612A (en) 1995-08-10 1998-05-05 Mcdata Corporation Method and apparatus for implementing virtual circuits in a fibre channel system
US6047323A (en) 1995-10-19 2000-04-04 Hewlett-Packard Company Creation and migration of distributed streams in clusters of networked computers
US5671365A (en) 1995-10-20 1997-09-23 Symbios Logic Inc. I/O system for reducing main processor overhead in initiating I/O requests and servicing I/O completion events
US5828475A (en) 1995-10-25 1998-10-27 Mcdata Corporation Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch using a bypass bus and buffer
US5610745A (en) 1995-10-26 1997-03-11 Hewlett-Packard Co. Method and apparatus for tracking buffer availability
US6055618A (en) 1995-10-31 2000-04-25 Cray Research, Inc. Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel
US5968143A (en) 1995-12-13 1999-10-19 International Business Machines Corporation Information handling system for transfer of command blocks to a local processing side without local processor intervention
JPH09247176A (ja) 1996-03-11 1997-09-19 Hitachi Ltd 非同期転送モード交換方式
US5892969A (en) 1996-03-15 1999-04-06 Adaptec, Inc. Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation
US5758187A (en) 1996-03-15 1998-05-26 Adaptec, Inc. Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure
US6031842A (en) 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture
US5894481A (en) 1996-09-11 1999-04-13 Mcdata Corporation Fiber channel switch employing distributed queuing
US5881296A (en) 1996-10-02 1999-03-09 Intel Corporation Method for improved interrupt processing in a computer system
US5835752A (en) 1996-10-18 1998-11-10 Samsung Electronics Co. Ltd. PCI interface synchronization
KR100194813B1 (ko) 1996-12-05 1999-06-15 정선종 멀티채널/멀티캐스트 스위칭 기능을 갖는 패킷 스위칭장치 및 이를 이용한 패킷 스위칭 시스템
US6026092A (en) 1996-12-31 2000-02-15 Northern Telecom Limited High performance fault tolerant switching system for multimedia satellite and terrestrial communications networks
US6014383A (en) 1997-02-10 2000-01-11 Compaq Computer Corporation System and method for controlling multiple initiators in a fibre channel environment
US5954796A (en) 1997-02-11 1999-09-21 Compaq Computer Corporation System and method for automatically and dynamically changing an address associated with a device disposed in a fire channel environment
US6233244B1 (en) 1997-02-14 2001-05-15 Advanced Micro Devices, Inc. Method and apparatus for reclaiming buffers
US6185203B1 (en) 1997-02-18 2001-02-06 Vixel Corporation Fibre channel switching fabric
US6118776A (en) * 1997-02-18 2000-09-12 Vixel Corporation Methods and apparatus for fiber channel interconnection of private loop devices
US6160813A (en) 1997-03-21 2000-12-12 Brocade Communications Systems, Inc. Fibre channel switching system and method
US5825748A (en) 1997-04-08 1998-10-20 International Business Machines Corporation Credit-based flow control checking and correction system
US5987028A (en) 1997-05-12 1999-11-16 Industrial Technology Research Insitute Multiple channel ATM switch
US6115761A (en) 1997-05-30 2000-09-05 Lsi Logic Corporation First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment
US6108738A (en) 1997-06-10 2000-08-22 Vlsi Technology, Inc. Multi-master PCI bus system within a single integrated circuit
US6081512A (en) 1997-06-30 2000-06-27 Sun Microsystems, Inc. Spanning tree support in a high performance network device
KR100259841B1 (ko) 1997-07-31 2000-06-15 윤종용 씽글 칩을 이용한 피씨아이 버스의 핫 플러그 제어기
US5905905A (en) 1997-08-05 1999-05-18 Adaptec, Inc. System for copying IOBS from FIFO into I/O adapter, writing data completed IOB, and invalidating completed IOB in FIFO for reuse of FIFO
US6055603A (en) 1997-09-18 2000-04-25 Emc Corporation Method and apparatus for performing pre-request operations in a cached disk array storage system
US5983292A (en) 1997-10-15 1999-11-09 International Business Machines Corporation Message transport mechanisms and methods
US6078970A (en) 1997-10-15 2000-06-20 International Business Machines Corporation System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory
US6085277A (en) 1997-10-15 2000-07-04 International Business Machines Corporation Interrupt and message batching apparatus and method
US6138176A (en) 1997-11-14 2000-10-24 3Ware Disk array controller with automated processor which routes I/O data according to addresses and commands received from disk drive controllers
US6144668A (en) 1997-11-26 2000-11-07 International Business Machines Corporation Simultaneous cut through and store-and-forward frame support in a network device
US6105122A (en) 1998-02-06 2000-08-15 Ncr Corporation I/O protocol for highly configurable multi-node processing system
CN1309849A (zh) 1998-02-24 2001-08-22 西加特技术有限责任公司 采用动态半双工保持环路的公平
US6006340A (en) 1998-03-27 1999-12-21 Phoenix Technologies Ltd. Communication interface between two finite state machines operating at different clock domains
US6185620B1 (en) 1998-04-03 2001-02-06 Lsi Logic Corporation Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion
US6134617A (en) 1998-04-03 2000-10-17 Lsi Logic Corporation Method and apparatus for managing access to a loop in a data processing system
US6108778A (en) 1998-04-07 2000-08-22 Micron Technology, Inc. Device for blocking bus transactions during reset
US6324181B1 (en) 1998-04-16 2001-11-27 3Com Corporation Fibre channel switched arbitrated loop
US6101166A (en) 1998-05-01 2000-08-08 Emulex Corporation Automatic loop segment failure isolation
US6188668B1 (en) 1998-05-01 2001-02-13 Emulex Corporation Automatic isolation in loops
US6289386B1 (en) 1998-05-11 2001-09-11 Lsi Logic Corporation Implementation of a divide algorithm for buffer credit calculation in a high speed serial channel
US6411599B1 (en) * 1998-05-29 2002-06-25 International Business Machines Corporation Fault tolerant switching architecture
US6330236B1 (en) 1998-06-11 2001-12-11 Synchrodyne Networks, Inc. Packet switching method with time-based routing
US6353612B1 (en) 1998-06-19 2002-03-05 Brocade Communications Systems, Inc. Probing device
US7165152B2 (en) * 1998-06-30 2007-01-16 Emc Corporation Method and apparatus for managing access to storage devices in a storage system with access control
US7756986B2 (en) * 1998-06-30 2010-07-13 Emc Corporation Method and apparatus for providing data management for a storage system coupled to a network
US6401128B1 (en) 1998-08-07 2002-06-04 Brocade Communiations Systems, Inc. System and method for sending and receiving frames between a public device and a private device
US6269413B1 (en) 1998-10-30 2001-07-31 Hewlett Packard Company System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections
US6308220B1 (en) 1999-01-29 2001-10-23 Neomagic Corp. Circulating parallel-search engine with random inputs for network routing table stored in a wide embedded DRAM
US6546010B1 (en) * 1999-02-04 2003-04-08 Advanced Micro Devices, Inc. Bandwidth efficiency in cascaded scheme
US6233629B1 (en) * 1999-02-05 2001-05-15 Broadcom Corporation Self-adjusting elasticity data buffer with preload value
US6504846B1 (en) * 1999-05-21 2003-01-07 Advanced Micro Devices, Inc. Method and apparatus for reclaiming buffers using a single buffer bit
US6564271B2 (en) * 1999-06-09 2003-05-13 Qlogic Corporation Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
US6697359B1 (en) * 1999-07-02 2004-02-24 Ancor Communications, Inc. High performance switch fabric element and switch systems
US6343324B1 (en) 1999-09-13 2002-01-29 International Business Machines Corporation Method and system for controlling access share storage devices in a network environment by configuring host-to-volume mapping data structures in the controller memory for granting and denying access to the devices
US6721799B1 (en) * 1999-09-15 2004-04-13 Koninklijke Philips Electronics N.V. Method for automatically transmitting an acknowledge frame in canopen and other can application layer protocols and a can microcontroller that implements this method
US6859435B1 (en) * 1999-10-13 2005-02-22 Lucent Technologies Inc. Prevention of deadlocks and livelocks in lossless, backpressured packet networks
US20030046396A1 (en) * 2000-03-03 2003-03-06 Richter Roger K. Systems and methods for managing resource utilization in information management environments
US6718497B1 (en) * 2000-04-21 2004-04-06 Apple Computer, Inc. Method and apparatus for generating jitter test patterns on a high performance serial bus
US6865157B1 (en) * 2000-05-26 2005-03-08 Emc Corporation Fault tolerant shared system resource with communications passthrough providing high availability communications
US6725388B1 (en) * 2000-06-13 2004-04-20 Intel Corporation Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains
JP2002084019A (ja) * 2000-09-08 2002-03-22 Canon Inc 磁気デバイス及び固体磁気メモリ
US6697368B2 (en) * 2000-11-17 2004-02-24 Foundry Networks, Inc. High-performance network switch
US7002926B1 (en) * 2000-11-30 2006-02-21 Western Digital Ventures, Inc. Isochronous switched fabric network
US20040081394A1 (en) * 2001-01-31 2004-04-29 Giora Biran Providing control information to a management processor of a communications switch
US7050392B2 (en) * 2001-03-30 2006-05-23 Brocade Communications Systems, Inc. In-order delivery of frames during topology change
US7000025B1 (en) * 2001-05-07 2006-02-14 Adaptec, Inc. Methods for congestion mitigation in infiniband
US7200108B2 (en) * 2001-06-29 2007-04-03 International Business Machines Corporation Method and apparatus for recovery from faults in a loop network
US20030056000A1 (en) * 2001-07-26 2003-03-20 Nishan Systems, Inc. Transfer ready frame reordering
US7215680B2 (en) * 2001-07-26 2007-05-08 Nishan Systems, Inc. Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop
US6532212B1 (en) * 2001-09-25 2003-03-11 Mcdata Corporation Trunking inter-switch links
US20030084219A1 (en) * 2001-10-26 2003-05-01 Maxxan Systems, Inc. System, apparatus and method for address forwarding for a computer network
JP2003141055A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 計算機システムの接続設定方法
US6862293B2 (en) * 2001-11-13 2005-03-01 Mcdata Corporation Method and apparatus for providing optimized high speed link utilization
US7206287B2 (en) * 2001-12-26 2007-04-17 Alcatel Canada Inc. Method and system for isolation of a fault location in a communications device
US6915463B2 (en) * 2001-12-26 2005-07-05 Richard Charles Vieregge System and method for performing pre-emptive protection switching
US7499410B2 (en) * 2001-12-26 2009-03-03 Cisco Technology, Inc. Fibre channel switch that enables end devices in different fabrics to communicate with one another while retaining their unique fibre channel domain—IDs
US7047326B1 (en) * 2002-01-31 2006-05-16 Harman International Industries, Inc. Use of a remote control with a device having a built-in communication port
KR100449102B1 (ko) * 2002-03-19 2004-09-18 삼성전자주식회사 멀티미디어용 시스템온칩 프로세서
US7194538B1 (en) * 2002-06-04 2007-03-20 Veritas Operating Corporation Storage area network (SAN) management system for discovering SAN components using a SAN management server
US6961813B2 (en) * 2002-06-21 2005-11-01 Hewlett-Packard Development Company, L.P. System and method for providing multi-initiator capability to an ATA drive
TWI231424B (en) * 2002-06-28 2005-04-21 Quanta Comp Inc Management and preparation system of blade server
US7664018B2 (en) * 2002-07-02 2010-02-16 Emulex Design & Manufacturing Corporation Methods and apparatus for switching fibre channel arbitrated loop devices
US7154886B2 (en) * 2002-07-22 2006-12-26 Qlogic Corporation Method and system for primary blade selection in a multi-module fiber channel switch
US20040015638A1 (en) * 2002-07-22 2004-01-22 Forbes Bryn B. Scalable modular server system
US7230929B2 (en) * 2002-07-22 2007-06-12 Qlogic, Corporation Method and system for dynamically assigning domain identification in a multi-module fibre channel switch
US7055068B2 (en) * 2002-07-25 2006-05-30 Lsi Logic Corporation Method for validating operation of a fibre link
WO2004015764A2 (en) * 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
US7352706B2 (en) * 2002-09-16 2008-04-01 Finisar Corporation Network analysis scalable analysis tool for multiple protocols
US6886141B1 (en) * 2002-10-07 2005-04-26 Qlogic Corporation Method and system for reducing congestion in computer networks
US20040100944A1 (en) * 2002-11-27 2004-05-27 Scott Richmond Serial ATA frame structure routing circuitry and protocols
US7289434B2 (en) * 2002-12-05 2007-10-30 Cisco Technology, Inc. Method for verifying function of redundant standby packet forwarder
US7221650B1 (en) * 2002-12-23 2007-05-22 Intel Corporation System and method for checking data accumulators for consistency
US7127534B2 (en) * 2003-06-27 2006-10-24 Emulex Design & Manufacturing Corporation Read/write command buffer pool resource management using read-path prediction of future resources
TWI249681B (en) * 2003-07-02 2006-02-21 Via Tech Inc Circuit and method for aligning data transmitting timing of a plurality of lanes
US7930377B2 (en) * 2004-04-23 2011-04-19 Qlogic, Corporation Method and system for using boot servers in networks
US7716315B2 (en) * 2004-09-24 2010-05-11 Emc Corporation Enclosure configurable to perform in-band or out-of-band enclosure management

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106415513A (zh) * 2014-06-26 2017-02-15 英特尔公司 用于分组发送的优化的信用返回机制
CN106415513B (zh) * 2014-06-26 2019-06-04 英特尔公司 用于分组发送的优化的信用返回机制

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