CN101080800B - 具有基于非陶瓷的窗口框架的半导体封装 - Google Patents

具有基于非陶瓷的窗口框架的半导体封装 Download PDF

Info

Publication number
CN101080800B
CN101080800B CN2004800035768A CN200480003576A CN101080800B CN 101080800 B CN101080800 B CN 101080800B CN 2004800035768 A CN2004800035768 A CN 2004800035768A CN 200480003576 A CN200480003576 A CN 200480003576A CN 101080800 B CN101080800 B CN 101080800B
Authority
CN
China
Prior art keywords
window frame
flange
ring flange
gold
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2004800035768A
Other languages
English (en)
Other versions
CN101080800A (zh
Inventor
杰弗里·维尼加斯
保罗·加兰
乔舒亚·洛布辛格
琳达·卢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Serra Keogh International Ltd By Share Ltd
Original Assignee
Kyocera America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera America Inc filed Critical Kyocera America Inc
Publication of CN101080800A publication Critical patent/CN101080800A/zh
Application granted granted Critical
Publication of CN101080800B publication Critical patent/CN101080800B/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/36Mechanical coupling means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

Abstract

一种用于功率晶体管等的半导体封装具有:其上安装了至少一个管芯的热沉法兰盘;在法兰盘上邻近管芯安装的非陶瓷窗口框架;以及安装在窗口框架上,并通过引线键合电耦合至管芯的多根引线。所述的非陶瓷基的窗口框架与法兰盘通常采用的铜或其它高度导电的材料热匹配以在高温下促进半导体封装的装配。非陶瓷基的窗口框架是柔性的,并且与高度导电的法兰盘热匹配,从而以相似于法兰盘的速度膨胀和收缩来防止在半导体封装的装配期间失效。窗口框架的非陶瓷基材料包括主要为有机材料的基体,例如聚四氟乙烯,其中填充可以为玻璃纤维或陶瓷纤维的纤维。采用铜或铝等金属包覆所述基体,并可以采用镍和金进行涂覆以用金/锗焊料促进窗口框架与法兰盘和引线的接合。也可以使用环氧树脂将窗口框架接合到所述法兰盘上。可以通过在所述基体上层压足够厚度的铜或其它包层材料的方式执行对窗口框架的包覆,从而形成法兰盘。可以为法兰盘提供基座,其由位于法兰盘的中央部分的上表面向上延伸以界定管芯贴附区域,并形成用于阻挡将窗口框架焊接到法兰盘上所需的焊接材料的壁垒。

Description

具有基于非陶瓷的窗口框架的半导体封装
技术领域
本发明涉及半导体封装,更具体来讲,涉及一种在位于一个窗口框架的开口内的法兰盘上安装一个或多个管芯的封装,所述窗口框架安装在所述法兰盘上,并且在其上安装有引线。
背景技术
提供其中在位于一窗口框架的开口内的热沉法兰盘上安装一个或多个管芯并在所述法兰盘上安装和绝缘多根引线的半导体封装在本领域是公知的。所述管芯可以是LDMOS(横向扩散金属氧化物半导体)型,所述封装可以是用于封装所述LDMOS功率晶体管的封装类型。通常由基于例如氧化铝的陶瓷的材料制成的窗口框架用于在半导体封装上安装多根引线,并使所述引线与所述热沉法兰盘和其它封装部分绝缘。所述窗口框架在其中具有一围绕所述半导体管芯的开口。所述管芯电耦合到诸如引线键合的导体。
在上述类型的半导体封装中,通过诸如硬焊/软焊将其包括法兰盘、窗口框架和引线在内的构成部件结合起来,形成一个头。然后,将一个或多个管芯诸如通过硬焊/软焊安装到所述头,并诸如通过引线键合电贴附到所述引线。在所述头的组装过程中,通常要使半导体封装承受700-900℃的温度,以实施硬焊。这样的高温使得具体包括热沉法兰盘和窗口框架在内的被接合的材料具有类似的热膨胀系数(CTE)。理想地,法兰盘由例如铜的高度导电的材料制成。但是,由于窗口框架的氧化铝或其它陶瓷材料具有低得多的热膨胀率,因此,经常需要使法兰盘由具有与窗口框架的陶瓷材料更加接近的CTE匹配的更小导电性的材料构成。在没有如此接近的CTE匹配的情况下,法兰盘和窗口框架就会以显著不同的速率膨胀或收缩,以使在封装上施加了显著的应力。使如此的情况复杂是窗口框架的陶瓷材料的易碎特性,导致由如此的应力造成它断裂或其它的失效。
因此希望提供一种封装,该封装允许采用诸如纯铜的高导电材料用于热沉法兰盘。窗口框架的材料应当提供与法兰盘的接近的CTE匹配,并且,理想地是柔性的,不易破碎的,从而更好的承受在组装封装期间产生的应力。
在头的组装期间,尤其是在采用硬焊将部件结合起来时,可能出现进一步的问题。在窗口框架的开口内的法兰盘的顶表面形成了用于安装一个或多个管芯的管芯贴附区域。如此的管芯贴附区域必须光滑并且没有硬焊材料,从而使管芯适当地贴附于所述区域。但是,在头的组装期间,位于窗口框架和法兰盘之间的界面处的硬焊材料可能流到管芯贴附区域,从而干扰了对该区域内管芯的后续安装。因此,希望在头的组装期间防止硬焊材料流入管芯贴附区域。
发明内容
本发明提供了一种改进的半导体封装结构。更具体来讲,本发明提供了一种改进的窗口框架,使得在热沉法兰盘中可以采用高度导电的材料而且同时防止在装配期间产生不适当的应力和失效。
根据本发明,所述窗口框架由基于非陶瓷的材料,例如具有玻璃纤维的PTFE制成。如表1所示,由具有玻璃纤维的PTFE制成的基于非陶瓷的窗口框架的弹性模量明显低于由氧化铝制成的传统窗口框架。较低的模量表示材料刚性更低,更不易于失效。
表1:传统头设计vs新型头设计
 材料性能
  部件  材料  X-Y方向CTE(ppm)   热导率(W/mK)   弹性模量(Gpa)
  窗口框架  氧化铝  -7    360
 PTFE基体+玻璃纤维  24    1
  热沉(法兰盘)  铜钨  -7   -200    240
 铜  17   398    120
根据本发明的半导体封装还提供了改进的法兰盘,具有位于其中央部分的升高基座,从而在所述窗口框架的开口内界定了一个分开的,升高的管芯贴附区域。所述基座防止了硬焊材料在头的装配期间流到管芯贴附区域上。
根据本发明的半导体封装包括一个基于非陶瓷材料的窗口框架,该材料提供了与纯铜或其它高度导电材料的接近的CTE匹配,所述的纯铜和其它高度导电材料可以用于形成表1所示的热沉法兰盘。随着两个接合部件之间的CTE差异的增大,部件内部的应力也增大。纯铜和替他高度导热材料提供了对于电子封装的操作性能的显著增强。采用氧化铝窗口框架的传统封装局限于导电性较差的热沉法兰盘,例如铜钨,以更好地匹配CTE。非陶瓷基的材料包括主要为有机材料的基体,其中填充纤维或其它几何填充物。所述基体可以包括聚四氟乙烯(PTFE)或环氧树脂,所述纤维可以是玻璃或陶瓷纤维/填充物。所述非陶瓷基的材料优选为金属的包层,以提供用于将窗口框架硬焊/软焊或采用其它方式接合到头的其它部件上的可浸润表面。软焊/硬焊/粘合的实施温度必须低于非陶瓷窗口框架的分解温度。根据选择,可以相应涂布所述包层的表面条件。在采用金/锗焊接材料的情况下,所述包层优选用镍和金涂布,最为优选的情况下,采用金/锗焊料用于将窗口框架与其它部件结合。用于所述基体的包层的金属优选包含铜或铝。
根据本发明的窗口框架的非陶瓷基的材料具有与相对纯的铜或其它高度导电材料接近的CTE匹配的热特性,所述相对纯的铜或其它高度导电的材料优选用作热沉法兰盘。因为这样的匹配,可以避免否则由热膨胀和收缩量不均匀的量引起的应力。此外,所述窗口框架的非陶瓷基材料从实质上来讲是柔性的,从而进一步降低否则可能产生的裂纹或失效的可能性。
根据本发明的窗口框架的非陶瓷基材料可以诸如通过硬焊的方法贴附于法兰盘和引线。可以采用硬焊/软焊/粘合材料可以用于结合所述部件,在这种情况下,可以采用一种材料将管芯随后接合到所述法兰盘,相对于传统的头装配而言,这种材料具有较低的熔解温度,从而不会干扰对封装的装配期间产生的接合。参见表2中的示例。
可以通过各种方法,例如层压、压轧(rolling)、压热(autoclave)或镀覆(plating)来包覆所述窗口框架的非陶瓷基的材料。通过选择适当的铜或其它金属的厚度来包覆所述窗口框架的非陶瓷基的材料,所述金属还可以形成热沉法兰盘和/或引线以产生期望的结构。在需要电绝缘空间的情况下,可以通过光刻曝光或其它机械磨制的方法对贴附于所述的非陶瓷基的材料的金属进行构图。优选地,对贴附有金属的非陶瓷基的材料进行光刻处理以获得金属图案。
表2用于头和管芯的接合材料基体
头部件(硬焊/软焊的熔点)   管芯的接合材料(硬焊/软焊的熔点)
72Ag28Cu(780C)   88Au12Ge(356C)   80Au20Sn(280C)   63Sn37Pb(183C)
88Au12Ge(356C)   80Au20Sn(280C)   63Sn37Pb(183C)
80Au20Sn(280C)   63Sn37Pb(183C)
根据本发明,可以用从其中央部分的平坦上部表面向上延伸的升高基座形成所述法兰盘,从而界定用于在所述法兰盘上安装一个或多个管芯的管芯贴附区域。所述升高基适于在所述窗口框架中的开口内,并在所述管芯贴附区域周围形成了对于焊接材料的壁垒。在将所述窗口框架焊接到法兰盘期间,如此的壁垒可以防止焊接材料流到管芯贴附区域上。
附图说明
下面,将参照附图对本发明的优选实施例予以详细说明,其中:
图1是根据本发明的半导体封装的透视图;
图2是形成图1中所示的半导体封装的头的部件的分解图;
图3是图1中所示的半导体封装的窗口框架的放大透视图;
图4A和图4B是显著放大的截面图,其说明了在图1所示的半导体封装中,采用金属包覆窗口框架的非陶瓷基的材料的方式;
图5是根据本发明具有升高基座的法兰盘的备选实施例的透视图;
图6A和图6B是其中安装了图5中所示的法兰盘的半导体封装的局部截面图,其说明了所述基座防止焊接材料流入法兰盘的管芯贴附区域的方式;
图7A和图7B为半导体封装的局部截面图,其说明了包覆材料成为所述法兰盘和/或引线的方式。
具体实施方式
图1示出了根据本发明的半导体封装10。图1中的封装10包括具有延长的,平坦的,通常为平面结构的热沉法兰盘12,其具有安装于其上的窗口框架14。在与法兰盘12相对的窗口框架14上安装多根引线16。所述窗口框架14具有位于其中的暴露一部分法兰盘12的开口18。半导体管芯20安装在法兰盘12的开口18中,并电耦合至引线16。可以用引线键合22完成如此的电耦合,在图1中示出了两个引线键合22用于举例说明。图1中示出了单个管芯,用于举例说明,如果需要的话,可以在所述开口内安装多个管芯。可以在所述引线16上安装盖子(未示出),使其在开口18和包括的管芯20的上方延伸并包围。
图2是图1所示的半导体封装的几个部件的分解图,其示出了对这些部件进行装配以形成头24的方式。头24包括法兰盘12、窗口框架14和引线16。例如通过焊接的方法将窗口框架14与法兰盘12相结合,随后,采用类似的方式将引线16安装到窗口框架14上与法兰盘12相对的位置。通过在头24的窗口框架14内安装一个或多个管芯20,并通过引线键合将管芯20电耦合至引线16来完成半导体封装10。然后可以采用环氧树脂或其它封装(potting)化合物填充开口18,如果期望,然后采用在封装10上方安装的一个盖子。
除窗口框架14之外,图1中的半导体封装均为传统构造。根据本发明,在图3中采用放大的详细的方式示出的窗口框架由非陶瓷基的材料构成。所述材料优选包括基本上为有机材料的基体,和填充的纤维或其它填充物。所述基体可以包括PTFE或环氧树脂。所述纤维或填充物可以包括玻璃或陶瓷。
与通常用于传统半导体封装中的窗口框架的氧化铝或其它陶瓷基的材料不同,根据本发明的所述窗口框架的非陶瓷基的材料提供了很多突出的优点。窗口框架14的非陶瓷基的材料提供了与优选用于法兰盘12的高度导电的铜或其它材料之间的接近的热膨胀或CTE匹配。因此,在法兰盘12、窗口框架14和引线16经受焊接过程中的通常为400℃以上的量级的高温时,所述窗口框架14经历相似于高度导电的法兰盘12的热膨胀和压缩速度。因此,避免了现有技术存在的结构和方法中的高热应力(详细内容参见表1)。
此外,与传统的窗口框架的陶瓷基的材料不同,根据本发明的窗口框架14的非陶瓷基的材料不是易碎的,而是在本质上柔性的,因此,进一步避免了传统结构中出现的断裂或其它失效。
为了与其它部件焊接或以其它方式接合的目的而对窗口框架14提供一个可浸润表面,优选采用诸如铜或铝的金属层包覆窗口框架14。由于窗口框架14的非陶瓷基的材料的本质,可能难于在包层金属和非陶瓷基的材料之间提供良好的接合。但是,通过图4A和图4B所示的技术可以提供良好的接合。图4A示出了与金属包层24隔开的窗口框架14。如图4A所示,在抵靠在窗口框架14上设置包层24之前,对包层24的表面26进行糙化处理。之后通过施加压力和高温的方式将层24层压到窗口框架14上。窗口框架14的非陶瓷基的材料流入到包层24的经过糙化处理的表面26中。在经过足够的时间之后,冷却所述结构且去除压力。图4B显示了最终的层压产品。如图4B所示,经过糙化处理的表面26与窗口框架14集成,从而在否则难于接合到一起的材料之间形成非常牢固的接合。之后,可以诸如采用为用金/锗焊料接合而准备的镍和金镀覆包层24。优选焊料具有88Au12Ge的成分,尽管可以采用其它焊料。
根据本发明的一个特征,在形成包层的同时,可以使用如图4A和图4B所示的包覆和层压操作提供其上贴附了法兰盘的窗口框架。只需使包层24具有足够的厚度以形成具有适当厚度的法兰盘,在包层24接合到窗口框架14上时,在窗口框架14的底部就形成所述法兰盘。这消除了形成分开的法兰盘12并将所述法兰盘贴附于所述窗口框架14的必要。
根据本发明,可以使用各种工艺将法兰盘12、窗口框架14和引线16结合起来。如前所述,可以使用金/锗焊料将所述窗口框架14结合到所述法兰盘12和引线16上。在采用这种方法的情况下,在对其包覆金属之后优选采用镍涂布窗口框架14。或者,可以在不进行软焊/硬焊的情况下结合窗口框架14。这可以使用环氧树脂或任何适当的粘合剂完成。环氧树脂具有与非陶瓷基的窗口框架的牢固粘合。与此同时,它们还能够与铜或铝包层以及窗口框架14上的镍/金镀层接合。可以使用环氧树脂将窗口框架14接合到法兰盘12和引线16上。
如前所述,可以使用层压技术将法兰盘12直接结合到窗口框架14的非陶瓷基的材料上。而且,正如前面结合图4A和图4B的说明,可以为包层24提供足够的厚度,使得在结合到窗口框架14上的同时形成法兰盘12。
图5示出了根据本发明的法兰盘30的备选实施例。法兰盘30与图1和图2中的法兰盘12类似之处在于其具有延长的,较薄的,通常为平面的构造,并且其上具有平坦上表面32。但是,与图1和图2中的法兰盘12不同,图5中的法兰盘30具有从平坦上表面32的中心部分向上延伸的升高部分或基座34。配置基座34使得在将所述窗口框架14安装到法兰盘30上时,使基座34的外侧周边适于在窗口框架14的开口18内。基座34自身具有界定管芯贴附区域的平坦上表面36。
图6A和图6B为类似于图1中的封装10的半导体封装的局部截面图,但在其中采用了法兰盘30。在图6B中的下部示出了具有升高基座34的法兰盘30。在图6B的右上部示出了窗口框架14的一部分。在窗口框架14的顶部结合了引线16。在图6A和图6B的实例中,通过焊接将所述窗口框架14、引线16和法兰盘30接合起来。如图6B中可见,在窗口框架14和引线16之间设置焊接材料的薄层38从而使所述部件结合起来。类似地,焊接材料的包层40沿窗口框架14和法兰盘30之间的界面延伸。在将窗口框架14与法兰盘30接合期间,焊接材料层40沿所示的位于其间的界面延伸。但是,所述的升高的基座34阻止焊接材料流到由基座36的平坦上部表面36形成的管芯贴附区域上。
贴附于头24上的管芯需要相对光滑的表面,通常要求表面粗糙度小于40u。法兰盘30的升高外围34作为防止焊接材料流到形成所述管芯贴附区域的平坦上部表面的壁垒。可以通过诸如机械加工或冲压的任何适当的技术形成法兰盘30的基座34。在焊接层38和窗口框架14之间,以及焊接层40和窗口框架14之间示出了具有可选涂层的包层材料42。
仍然如前所述,可以使用层压技术将法兰盘直接结合到窗口框架的非陶瓷基的材料上。此外,可以为包层提供足够的厚度,从而在结合到窗口框架上时形成法兰盘。图7A时具有前述法兰盘12的半导体封装的截面图,其不具有基座。在图7B中,所示的窗口框架通过包层贴附于引线16和法兰盘12。所述包层在窗口框架14的相对表面的界面处提供黏附。
从所有的角度来考虑,本发明公开的实施例均为举例说明和非限制性的,本发明的范围由权利要求书指示,而不是前面的描述,且因此在权利要求的等同含义和范围内做出的所有改变均旨在包含于本发明之内。

Claims (3)

1.一种半导体封装,包括:热沉法兰盘;非陶瓷基材料的窗口框架,安装在所述热沉法兰盘上;以及引线,安装于所述窗口框架上,其中,所述窗口框架由聚四氟乙烯基体制成,所述聚四氟乙烯基体填充了纤维并且具有金属包层,其中采用镍和/或金对所述金属包层镀覆,并采用了硬焊/软焊/粘合材料将所述窗口框架焊接到所述法兰盘和引线上。
2.如权利要求1所述的半导体封装,其中,用铜包覆所述窗口框架,并且所述法兰盘和引线中的至少一个包括窗口框架的部分铜包层。
3.如权利要求1所述的半导体封装,其中,所述窗口采用金/锗焊料接合到所述法兰盘,所述金/锗焊料具有指定熔解温度,所述半导体封装还包括采用金/锡混合物接合到所述法兰盘上的管芯,所述金/锡混合物的熔解温度低于所述金/锗焊料的指定熔解温度。
CN2004800035768A 2003-01-10 2004-01-09 具有基于非陶瓷的窗口框架的半导体封装 Expired - Fee Related CN101080800B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/339,834 US7298046B2 (en) 2003-01-10 2003-01-10 Semiconductor package having non-ceramic based window frame
US10/339,834 2003-01-10
PCT/US2004/000621 WO2004064120A2 (en) 2003-01-10 2004-01-09 Semiconductor package having non-ceramic based window frame

Publications (2)

Publication Number Publication Date
CN101080800A CN101080800A (zh) 2007-11-28
CN101080800B true CN101080800B (zh) 2012-02-22

Family

ID=32711185

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004800035768A Expired - Fee Related CN101080800B (zh) 2003-01-10 2004-01-09 具有基于非陶瓷的窗口框架的半导体封装

Country Status (10)

Country Link
US (2) US7298046B2 (zh)
EP (1) EP1584101B1 (zh)
JP (1) JP4466645B2 (zh)
KR (1) KR101015749B1 (zh)
CN (1) CN101080800B (zh)
AT (1) ATE515053T1 (zh)
CA (1) CA2512845C (zh)
HK (1) HK1082591A1 (zh)
IL (1) IL169543A (zh)
WO (1) WO2004064120A2 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070175660A1 (en) * 2006-01-27 2007-08-02 Yeung Betty H Warpage-reducing packaging design
ATE397647T1 (de) * 2006-03-06 2008-06-15 Umicore Ag & Co Kg Zusammensetzung zur befestigung von hochleistungshalbleiter
US20080016684A1 (en) * 2006-07-06 2008-01-24 General Electric Company Corrosion resistant wafer processing apparatus and method for making thereof
US20080006204A1 (en) * 2006-07-06 2008-01-10 General Electric Company Corrosion resistant wafer processing apparatus and method for making thereof
US7961470B2 (en) * 2006-07-19 2011-06-14 Infineon Technologies Ag Power amplifier
US7952188B2 (en) * 2007-01-08 2011-05-31 Infineon Technologies Ag Semiconductor module with a dielectric layer including a fluorocarbon compound on a chip
CN101399237B (zh) * 2008-10-24 2010-06-02 江阴市赛英电子有限公司 全压接快速散热型陶瓷外壳
US20100139885A1 (en) * 2008-12-09 2010-06-10 Renewable Thermodynamics, Llc Sintered diamond heat exchanger apparatus
WO2011119891A2 (en) * 2010-03-25 2011-09-29 Anwar Abdul Mohammed High performance low cost open air cavity ceramic power packages for high temperature die attach processes
US8907467B2 (en) * 2012-03-28 2014-12-09 Infineon Technologies Ag PCB based RF-power package window frame
JP5885690B2 (ja) 2012-04-27 2016-03-15 キヤノン株式会社 電子部品および電子機器
JP6296687B2 (ja) 2012-04-27 2018-03-20 キヤノン株式会社 電子部品、電子モジュールおよびこれらの製造方法。
EP2757582A1 (en) * 2013-01-17 2014-07-23 Nxp B.V. Packaged electrical components
US9879722B2 (en) * 2013-03-11 2018-01-30 Bell Helicopter Textron Inc. Low shear modulus transition shim for elastomeric bearing bonding in torsional applications
WO2014156029A1 (ja) * 2013-03-28 2014-10-02 パナソニック株式会社 半導体パッケージおよび半導体デバイス
US10468399B2 (en) 2015-03-31 2019-11-05 Cree, Inc. Multi-cavity package having single metal flange
US9629246B2 (en) 2015-07-28 2017-04-18 Infineon Technologies Ag PCB based semiconductor package having integrated electrical functionality
US9997476B2 (en) 2015-10-30 2018-06-12 Infineon Technologies Ag Multi-die package having different types of semiconductor dies attached to the same thermally conductive flange
US10225922B2 (en) 2016-02-18 2019-03-05 Cree, Inc. PCB based semiconductor package with impedance matching network elements integrated therein
US10332847B2 (en) * 2017-06-01 2019-06-25 Infineon Technologies Ag Semiconductor package with integrated harmonic termination feature
CN109037161A (zh) * 2018-06-15 2018-12-18 华为技术有限公司 一种法兰和半导体功率器件
WO2020004566A1 (ja) * 2018-06-28 2020-01-02 京セラ株式会社 基体および半導体装置
CN114582826A (zh) * 2020-11-30 2022-06-03 上海华为技术有限公司 一种封装结构、封装方法

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767839A (en) * 1971-06-04 1973-10-23 Wells Plastics Of California I Plastic micro-electronic packages
US4385342A (en) * 1980-05-12 1983-05-24 Sprague Electric Company Flat electrolytic capacitor
US4784974A (en) * 1982-08-05 1988-11-15 Olin Corporation Method of making a hermetically sealed semiconductor casing
JPS59214243A (ja) * 1983-05-20 1984-12-04 Nec Corp 半導体装置
US4725347A (en) * 1986-05-02 1988-02-16 The Dow Chemical Company Reinforced bipolar electrolytic cell frame
JPS63109104A (ja) * 1986-10-28 1988-05-13 Nippon Steel Corp チタンの積層鋼板の製造方法
US4930857A (en) * 1989-05-19 1990-06-05 At&T Bell Laboratories Hybrid package arrangement
US5045972A (en) * 1990-08-27 1991-09-03 The Standard Oil Company High thermal conductivity metal matrix composite
US5650592A (en) * 1993-04-05 1997-07-22 Olin Corporation Graphite composites for electronic packaging
EP0681741A4 (en) * 1993-11-29 1996-06-05 Rogers Corp ENCLOSURE FOR AN ELECTRONIC CHIP CARRIER AND PRODUCTION METHOD.
JPH0831480A (ja) * 1994-07-15 1996-02-02 Fuji Denka:Kk 気密端子
US5686172A (en) * 1994-11-30 1997-11-11 Mitsubishi Gas Chemical Company, Inc. Metal-foil-clad composite ceramic board and process for the production thereof
WO1996027282A1 (en) * 1995-03-02 1996-09-06 Circuit Components Incorporated A low cost, high performance package for microwave circuits in the up to 90 ghz frequency range using bga i/o rf port format and ceramic substrate technology
WO1996037915A1 (en) * 1995-05-26 1996-11-28 Sheldahl, Inc. Adherent film with low thermal impedance and high electrical impedance used in an electronic assembly with a heat sink
US6056186A (en) * 1996-06-25 2000-05-02 Brush Wellman Inc. Method for bonding a ceramic to a metal with a copper-containing shim
US5792984A (en) * 1996-07-01 1998-08-11 Cts Corporation Molded aluminum nitride packages
AU4902897A (en) * 1996-11-08 1998-05-29 W.L. Gore & Associates, Inc. Method for improving reliability of thin circuit substrates by increasing the T of the substrate
JP3617232B2 (ja) * 1997-02-06 2005-02-02 住友電気工業株式会社 半導体用ヒートシンクおよびその製造方法ならびにそれを用いた半導体パッケージ
JP3500268B2 (ja) * 1997-02-27 2004-02-23 京セラ株式会社 高周波用入出力端子ならびにそれを用いた高周波用半導体素子収納用パッケージ
US5926372A (en) * 1997-12-23 1999-07-20 Ford Global Technologies, Inc. Power block assembly and method of making same
US6211463B1 (en) * 1998-01-26 2001-04-03 Saint-Gobain Industrial Ceramics, Inc. Electronic circuit package with diamond film heat conductor
JP2000077462A (ja) * 1998-08-28 2000-03-14 Nec Eng Ltd Tabテープ貼付装置
US6114048A (en) * 1998-09-04 2000-09-05 Brush Wellman, Inc. Functionally graded metal substrates and process for making same
JP3684305B2 (ja) * 1998-09-17 2005-08-17 日本オプネクスト株式会社 半導体レーザ結合装置および半導体受光装置
JP3457901B2 (ja) * 1998-11-18 2003-10-20 京セラ株式会社 光半導体素子収納用パッケージ
US6683325B2 (en) * 1999-01-26 2004-01-27 Patent-Treuhand-Gesellschaft-für Elektrische Glühlampen mbH Thermal expansion compensated opto-electronic semiconductor element, particularly ultraviolet (UV) light emitting diode, and method of its manufacture
JP3792445B2 (ja) * 1999-03-30 2006-07-05 日本特殊陶業株式会社 コンデンサ付属配線基板
US6261868B1 (en) * 1999-04-02 2001-07-17 Motorola, Inc. Semiconductor component and method for manufacturing the semiconductor component
US6373717B1 (en) * 1999-07-02 2002-04-16 International Business Machines Corporation Electronic package with high density interconnect layer
US6462413B1 (en) * 1999-07-22 2002-10-08 Polese Company, Inc. LDMOS transistor heatsink package assembly and manufacturing method
US6414389B1 (en) * 2000-01-28 2002-07-02 Ericsson Inc. Alignment pedestals in an LDMOS power package
JP2002252299A (ja) * 2001-02-26 2002-09-06 Kyocera Corp 半導体素子収納用パッケージおよび半導体装置
JP2002368168A (ja) * 2001-06-13 2002-12-20 Hitachi Ltd 半導体装置用複合部材、それを用いた絶縁型半導体装置、又は非絶縁型半導体装置
US6500529B1 (en) * 2001-09-14 2002-12-31 Tonoga, Ltd. Low signal loss bonding ply for multilayer circuit boards
US20030131476A1 (en) * 2001-09-28 2003-07-17 Vlad Ocher Heat conduits and terminal radiator for microcircuit packaging and manufacturing process
AT5972U1 (de) * 2002-03-22 2003-02-25 Plansee Ag Package mit substrat hoher wärmeleitfähigkeit
US6671449B1 (en) * 2002-06-13 2003-12-30 Agilent Technologies, Inc. Optical packaging assembly including a hermetically sealed optical device housing and method of making the same
US20040046247A1 (en) * 2002-09-09 2004-03-11 Olin Corporation, A Corporation Of The Commonwealth Of Virginia Hermetic semiconductor package
US6727117B1 (en) * 2002-11-07 2004-04-27 Kyocera America, Inc. Semiconductor substrate having copper/diamond composite material and method of making same
US7105931B2 (en) * 2003-01-07 2006-09-12 Abbas Ismail Attarwala Electronic package and method
SG157957A1 (en) * 2003-01-29 2010-01-29 Interplex Qlp Inc Package for integrated circuit die
US7095053B2 (en) * 2003-05-05 2006-08-22 Lamina Ceramics, Inc. Light emitting diodes packaged for high temperature operation
US6982483B2 (en) * 2003-05-30 2006-01-03 Freescale Semiconductor, Inc. High impedance radio frequency power plastic package
US20040246682A1 (en) * 2003-06-09 2004-12-09 Sumitomo Metal (Smi) Eectronics Devices Inc. Apparatus and package for high frequency usages and their manufacturing method

Also Published As

Publication number Publication date
KR20050105168A (ko) 2005-11-03
KR101015749B1 (ko) 2011-02-22
IL169543A0 (en) 2007-07-04
US20040195662A1 (en) 2004-10-07
US7298046B2 (en) 2007-11-20
EP1584101A4 (en) 2008-11-26
CN101080800A (zh) 2007-11-28
EP1584101A2 (en) 2005-10-12
CA2512845A1 (en) 2004-07-29
IL169543A (en) 2016-06-30
CA2512845C (en) 2012-07-03
ATE515053T1 (de) 2011-07-15
EP1584101B1 (en) 2011-06-29
JP4466645B2 (ja) 2010-05-26
WO2004064120A3 (en) 2005-09-01
JP2006516361A (ja) 2006-06-29
HK1082591A1 (en) 2006-06-09
US7582964B2 (en) 2009-09-01
US20080142963A1 (en) 2008-06-19
WO2004064120A2 (en) 2004-07-29

Similar Documents

Publication Publication Date Title
CN101080800B (zh) 具有基于非陶瓷的窗口框架的半导体封装
KR970010678B1 (ko) 리드 프레임 및 이를 이용한 반도체 패키지
CN104600054B (zh) 使用低温过程的高温半导体器件封装和结构的方法及装置
US5438021A (en) Method of manufacturing a multiple-chip semiconductor device with different leadframes
KR101843402B1 (ko) 표면 장착 가능한 광전자 소자 그리고 표면 장착 가능한 광전자 소자를 제조하기 위한 방법
US5218229A (en) Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead frame attachment
US20020109216A1 (en) Integrated electronic device and integration method
US4783428A (en) Method of producing a thermogenetic semiconductor device
CN106847781B (zh) 功率模块封装及其制造方法
JP5251791B2 (ja) 樹脂封止型半導体装置およびその製造方法
US20040061206A1 (en) Discrete package having insulated ceramic heat sink
CN106920781A (zh) 半导体封装体和用于形成半导体封装体的方法
CN101689538B (zh) 制造固定功率模块的方法
JP2020178003A (ja) パワー半導体モジュールおよびパワー半導体モジュールの製造方法
JP4515810B2 (ja) 半導体装置およびその製造方法
EP0740850A1 (en) Hermetically sealed hybrid ceramic integrated circuit package
JP2822989B2 (ja) リードフレーム及びその製造方法並びに樹脂封止型半導体装置
JPH11289040A (ja) リードフレーム及びこれを用いた半導体装置
JP4688647B2 (ja) 半導体装置とその製造方法
JP3686267B2 (ja) 半導体装置の製造方法
JP2000216306A (ja) 半導体装置
KR19990082573A (ko) 반도체 장치 및 이에 사용하는 다층 리드 프레임
JP2019087692A (ja) 半導体装置
JP2000133762A5 (zh)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161209

Address after: California, USA

Patentee after: Serra Keogh international Limited by Share Ltd.

Address before: California, USA

Patentee before: Kyocera America, Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120222

Termination date: 20220109