CN101107718A - 功率金氧半导体组件 - Google Patents
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Abstract
本发明提供一种功率金氧半导体组件,包含一漏极、一设置于该漏极上的基体,其具有一基体顶表面、内嵌于基体中之一源极,其从基体顶表面向下延伸至基体中、一栅极沟槽,其穿过源极及基体并延伸至漏极中,在栅极沟槽中设置有一栅极、连接沟槽的一源极基体,其具有一沟槽壁及沿着沟槽壁设置的一反穿透植入区域。一种制造半导体装置的方法,包括在基板上形成一具有顶层基本表面之硬屏蔽,在基板内形成一栅极沟槽,而在栅极沟槽中穿过硬屏蔽沉积有栅极材料,将硬屏蔽移除留下一栅极结构,形成一源极基体,其连接具有沟槽壁之沟槽,并形成一反穿透植入区域。
Description
技术领域
本发明是有关一种半导体装置,特别是指一种双倍扩散型金氧半导体(DMOS)功率组件及其制作流程。
背景技术
功率金氧半导体组件普遍应用于电子电路中,基于其应用,不同装置各有其特征。一普通应用为直流-直流转换器,其中包含了作为同步整流器的功率金氧半导体组件(也参考单结型场效晶体管的低电压端)及另一作为控制开关的功率金氧半导体组件(也参考单结型场效晶体管的高电压端)。单结型场效晶体管的低电压端需要一小型的开启电阻来达到良好的功率切换效能,而单结型场效晶体管的高电压端则需要一小型的栅极电容以得到快速的切换及良好的执行。
晶体管的开启电阻值(Rdson)是与通道长度(L)成正比,而与每单位区域的主动胞数量(W)成反比。为了降低开启电阻值,可利用较浅薄的源极与基体来减少通道长度,并利用降低主动胞的大小以增加每单位区域中主动胞的数量。然而,由于穿透现象使通道长度L有了极限,而由于制造技术及为使主动胞中源极和基体范围两者间具有良好的接触,使得每单位区域的主动胞数量受到局限。由于沟道长度及主动胞密度的增加,栅极电容数也随之增加,低组件电容可减少切换损失。在一些应用中,如同步整流器,基体二极管的储存电量与顺向压降也造成效能的流失,这些因素一同使双倍扩散型金氧半导体的执行效能受到限制。
双倍扩散型金氧半导体的功率组件中开启电阻与门极电容若可利用当前可达成的技术而减少,以改进功率切换的可靠度和功率消耗。其更可应用于发展实用流程提升双倍扩散型金氧半导体功率组件的产品可靠度。
附图说明
本发明的若干实施例将在随后的具体描述和相关附图中进一步说明:
图1为双倍扩散型金氧半导体(DMOS)组件之一实施例的剖视图;
图2为降压型转换器电路范例的示意图;
图3A至图3P为图1中一种制造组件100的流程剖视图;
图4为双倍扩散型金氧半导体组件的另一实施例的剖视图,其中的反穿透植入区域是沿着沟槽壁及沟槽底部连续植入;
图5为双倍扩散型金氧半导体组件的另一实施例的剖视图,在接触沟槽中包含一肖特基晶体管;
图6为双倍扩散型金氧半导体组件的另一实施例的剖视图,其中包含一肖特基晶体管;
图7为本发明中利用双倍接触蚀刻流程形成组件的剖视图;
图8为双倍扩散型金氧半导体的另一实施例的剖视图。
具体实施方式
本发明是提供一种功率金氧半导体组件,其可利用众多方法来实现,包括利用一流程、装置、系统、成分组成、以及计算机读取媒体,如计算机存取媒体或计算机网络,其中程序指令是透过光学或电力通讯连结来传送。在本说明书中所述的实施方式或本发明可达成的其它形式,皆为相关技术,一般来说,本发明所公开的步骤顺序在本发明的范畴中可进行更改。
本发明所提供的一个或多个实施例是由图式详细说明如下,本发明虽由这些实施例来描述,但并不以此些实施例局限本发明的范围,本发明的范畴仅以权利要求为限,并包含数种替代方案、修改及等价物。为了使本发明被详细了解,以下叙述是陈述数种具体描述,其是提供范例,并且依据权利要求所述者实行,不包含部分或所有的具体描述。为使目的明确,在本发明技术领域内所使用的技术材料不再详细叙述。
一种经改良的双倍扩散型金氧半导体组件及其制造流程是被公开。此组件中包含一漏极(drain)、一基体(body)及一源极(source),本组件的栅极(gate)是设置于一栅极沟槽(gate trench)中,穿过源极与基体而延伸至漏极内;邻近栅极沟槽且在源极附近设有一源极基体接触沟槽(source bodycontact trench),其中包含有一沿着沟槽壁设置的反穿透植入区域(anti-punchthrough implant);栅极的顶表面从基体的顶表面上方延伸而过,以确保栅极与源极有交迭(overlap),并使源极区域较浅。制造本组件的流程包括在基板上形成一硬屏蔽(hard mask),再穿过硬屏蔽于基板上形成一栅极沟槽,于栅极沟槽中置入栅极材料,接着移除硬屏蔽而留下一栅极结构,形成一具有沟槽壁的源极基体接触沟槽,最后形成一反穿透植入区域。
此部分所举范例的目的在于详细探讨利用N型材料制作源极和漏极,并用P型材料制作基体的N型沟道组件,此处所公开的技术与结构也可应用于P型沟道组件。图1所示为一双倍扩散型金氧半导体(DMOS)组件之一具体实施例的剖示图,在本例中,组件100包含一漏极,其形成于一N+型半导体基板103上,延伸至基板103上之一磊晶(epi)层104内,其为N-型半导体。复数栅极沟槽111、113、115是在磊晶层104中蚀刻而成,栅极氧化层121、123、125则形成于该栅极沟槽中。复数栅极131、133、135分别设置于栅极沟槽111、113、115中,并透过栅极氧化层而与磊晶层隔离。栅极是利用具传导性的材料所制作,如多晶硅,而氧化层则利用绝缘材料来制作,如热氧化层。
源极区域151、153、155是分别内嵌于基体区域141、143、145中,源极区域从基体的顶表面向下延伸至基体本身,如附图所示,栅极131具有一栅极顶表面,其是延伸在内嵌有源极的基体顶表面的上方,如此的架构配置可确保源极与栅极的交迭,使源极区域可比具有凹陷栅极的源极区域来的浅,增加组件效率及效能。在不同实施例中,从源极与基体交叉点上方延伸过的栅极顶表面总数可不同。当栅极并未从基体顶表面上方延伸时的架构也可应用于组件中。
在栅极之间形成一系列的源极基体接触沟槽112、114、116。举例如下,接触沟槽112穿透源极区域151形成两个与栅极相邻的区域151a及151b,而穿过基体区域141则形成与沟槽相邻的区域141a及141b。当操作时,漏极和基体区域如一个二极管般一同动作,就如同基体二极管。一介电材料层设置于栅极上方,用以隔离栅极与源极和基体的接触,适当的绝缘材料包括热氧化层、低温氧化层(LTO)及硼磷硅酸盐玻璃(BPSG)等,此绝缘材料在栅极、基体与源极区域顶端形成隔离区域132、134、136。
实施例中显示,场效晶体管FET通道是在源极与基体之间沿着栅极沟槽的侧壁成形,在一短沟道组件中,当源极和漏极间的电压增加时,空乏区扩大且最后可能影响到源极周遭,此现象归因于穿透,限制了通道长度,使其可能会变短。为防止穿透,沿着源极基体接触沟槽壁的区域161a、161b、163a、163b、165a、165b以P型材料进行重掺杂,以形成P+型区域,此P+型区域可防止空乏区侵蚀到源极区域。因此,这些植入有时与反穿透植入区域有关,在一些实施例中,为了达到所宣称的反穿透功效,将P+型区域尽可能的设置于沟道区域附近,且/或在制造校准可允许的范围及P+型区域侧壁的掺杂穿透控制内与沟道区域愈近愈好。而在一些实施例中,沟槽接触与栅极沟槽间的空间对准是利用对接触面自行对准来达到最小化,且沟槽接触是尽可能的设置于栅极沟槽与栅极沟槽的中间。基于结构上的提高,可将沟道缩短以使沟道中每单位区域的静电荷在理想无保护架构中防止穿透所需的最小电量的下。反穿透植入区域可制造相当浅的沟槽短沟道装置,因此而改良开启电阻Rdson及减小栅极体积,且反穿透植入区域也可增加基体接触电阻。
具有轻掺杂漏极(如钛、铂、釟、钨或其它任何适用的材料)、适用于制造肖特基接触的金属层是设置于源及基体接触沟槽112、114、116底部,以分别形成接触电极122、124、126。由于穿透植入是沿着沟槽壁设置但不沿着沟槽的底部,故接触电极与N-型漏极区域104连接。此接触电极与漏极一起形成与基体二极管平行的肖特基晶体管,此肖特基晶体管可减少基体二极管的顺向压降并将储存电量最小化,使金氧半场效晶体管具有更高的效率。金属层180设置于肖特基金属上方,与源极、基体接触。在一些实施例中,金属层180是由铝(Al)或钛/氮化钛/铝的堆栈所制成。
在部分实施例中,单一金属可同时形成N-型漏极的肖特基接触与P+型基体和N+型源极所用的良好欧姆接触,因此,肖特基金属不需以栓塞型态放置于源极基体接触沟槽的底部。换言的,将肖特基金属以栓塞型态放置于源极-基体沟槽中有利于阻止反穿透植入区域进入N-型漏极区域。
图2为降压型转换器的简单电路图,在此例中,电路200是利用高电压端场效晶体管组件201及低电压端场效晶体管组件207而组成。高电压端组件201包含一晶体管202及一基体二极管204,低电压端组件207的结构则与图1所示相似,包含一晶体管208、一基体二极管210及一肖特基晶体管212。加载端包括一诱导器214、一电容器216及一电阻218。在一般操作状态时,高电压端组件201是为开启的,以将电源由输入源传送到加载端,使诱导器中产生一电流。当高电压端组件201为关闭时,诱导器电流仍继续流动并使电流方向转换置低电压端组件207中的基体二极管210。经过一段短暂的延迟后,控制电流将低电压端组件207开启,其启动晶体管208的通道,并明显地减少组件208中漏极至源极端的顺向压降。若没有肖特基晶体管212,则基体二极管会传导遗失,而在移除组件207中基体二极管210的储存电量时所造成的遗失是相当重要的。然而,若肖特基晶体管212是建立在组件207中且具有低的顺向压降,则传导遗失将大幅降低。由于跨越肖特基晶体管的低顺向压降较基体二极管的交叉点压降为低,故当肖特基晶体管在传导时不投入储存电量,更可因二极管恢复而改进遗失。
图3A至图3P为一种制造图1中装置100的制造流程的剖视图。如图所示,一N型基板(即一N+型硅晶圆,其上具有一N-型磊晶层),作为组件的漏极。在图3A中,一二氧化硅层402在N型基板400上利用沉淀或热氧化所形成;在部分具体实施例中,氧化硅的厚度范围为500~30000,其它厚度则应用于其它的实施例中,此厚度是基于栅极的高度来做调整。光阻层404涂布于氧化层的顶部,利用沟槽屏蔽形成图案。
在图3B中,将无遮蔽处的二氧化硅移除,留下一二氧化硅硬屏蔽410以进行硅蚀刻。在图3C中,将硅非等向性蚀刻,留下复数沟槽,如沟槽420,并将栅极材料沉积于沟槽中,接着在沟槽中以与基板顶表面垂直的位置上形成栅极。在图3D中,二氧化硅硬屏蔽410适当地向后蚀刻,使沟槽壁在蚀刻步骤的后与硬屏蔽的边缘维持约略一直线。二氧化硅在本实施例中是作为屏蔽的材料,因为蚀刻时使用二氧化硅硬屏蔽可留下相对整齐的沟槽壁,使其与屏蔽边壁互相整齐排列,而其它的材料也可适当地使用。传统上,有其它材料使用于硬屏蔽蚀刻,如Si3N4,在蚀刻时可能产生弯曲的沟槽壁,降低后续的栅极产生步骤的满意度。
在图3E中,将基板等向蚀刻以形成沟槽底部,在一些实施例中,沟槽深度约为0.5-2.5μm,宽度约为0.2-1.5μm,其它尺寸也可使用。为提供一光滑表面给栅极介电材料成长,在沟槽中成长出一由二氧化硅所构成的牺牲层430,接着利用湿式蚀刻将这一层移除。在图3G中,由于二氧化硅为非导电性物质,将二氧化硅层432设置于沟槽中。
在图3H中,将多晶硅440沉积于沟槽中并将的填满,于本例中,多晶硅的掺杂可获得适当的栅极阻抗。在一些实施例中,掺杂沉积出多晶硅层,而在一些实施例中,则在沉积后掺杂多晶硅。在图3I中,二氧化硅顶端的多晶硅层往后蚀刻以形成如442的栅极,此时,栅极的顶表面444仍然与二氧化硅的顶表面448相应地嵌入,然而,栅极的顶表面444较硅的顶层446高。在一些实施例中,不使用多晶硅向后蚀刻,而在一些实施例中,将一屏蔽应用于多晶硅向后蚀刻中,不使用后续基体植入流程的附加屏蔽。于图3J中,将二氧化硅硬屏蔽移除,在一些实施例中是利用干式蚀刻来移除硬屏蔽,当遇到硅表面的顶端时即停止蚀刻,留下延伸至基板表面另一端的多晶硅栅极,其源极与基体掺杂将被植入。在一些实施例中,栅极延伸至基板表面另一端约300to 20000处,其它数值也可。这些实施例中皆使用一二氧化硅硬屏蔽,是由于在可操作的方式下,其可提供延伸至基板表面另一端所须求的栅极总数。接着可于晶圆上成长一屏蔽氧化硅层。
图3K中,利用一基体屏蔽在基体表面上设置一光阻层450,并在没有屏蔽的区域利用基体掺杂进行植入,掺杂的材料如硼离子可利用掺杂材料冲击基板表面以进行植入,或是其它适合地植入方法。接着移除光阻层并将晶圆加热,使植入的基体掺杂透过如基体驱动的程序进行热传导,形成基体区域460。在一些实施例中,进行基体掺杂的植入所需能源约在30-200Kev之间,剂量约在5E12-4E13离子数/平方公分之间,而造成的基体深度约为0.3-2.4μm,改变植入能量和剂量等变量可改变其深度。在一些实施例中,基体的植入并不使用屏蔽。
在图3L中设置有一光阻层610,使源极掺杂可植入到区域612中,在本例中,砷离子穿透未屏蔽处的硅而形成N+型源极。在一些实施例中,用来植入源极掺杂的能源约在5-80Kev之间,剂量约为1E15-1E16离子数/每平方公分之间,而造成的源极深度大约在0.05-0.5μm之间。改变一些变量更可减少深度,如掺杂能量及剂量。接着移除光阻层并加热晶圆,以透过一源极驱动程序对植入的源极掺杂进行热传导,其它植入流程也可适当地使用。第3M图中,在源极驱动后,于组件的顶表面沉积一介电层620(如BPSG),并视情况是否需要而使的更加密实。接着形成一蚀刻屏蔽614。
在图3N中,执行接触沟槽蚀刻以形成沟槽622、624、626,并将源极植入及基体植入的区段适当的蚀刻掉。图3Q中,穿透防护植入630、632是沿着沟槽622、624的垂直壁设置,在部分实施例中,植入的沉积方式为以一角度冲击离子到沟槽的侧壁上,而在一些实施例中,植入630、632则利用接触蚀刻流程所形成,此部份将陈述于下。在图3P中,沉积一金属堆栈,如钛+氮化钛+铝-硅-铜,以形成一接触点;一屏蔽蚀刻640将栅极金属接触及源极-基体接触分开,由于沟槽如624则可作为金属及半导体接触时的接触开口,故弯曲的角落区域可导致高电场及低组件损毁。在组件350中显示,沟槽是为圆滑面而不具有棱角,可避免高电场所带来的低损坏。
图4为另一双倍扩散型金氧半导体组件的实施例剖面图,其中沿着沟槽壁及沟槽底部是设置有连续的反穿透植入区域。在本实施例中,于组件490中沿着源极与基体的接触沟槽设置有一P+材料的P+层402,在一些实施例中,P+层是由P+型材料冲击沟槽表面所形成,而在一些实施例中,沟槽及P+层则在沟槽形成前,利用于基体区域中沉积P+型材料而成,接着将P+型材料适当的蚀刻掉。接触金属层404(如钛或氮化钛)是如栅极氧化层的顶端般沉积于沟槽中,沟槽中充满了材料,如钨。再沉积一接触金属层(如铝-硅-铜),在部分实施例中,沟槽的深度有多种变化,并可与栅极深度相同。较深的沟槽可提供较佳的沟道区域防护。虽然本组件中没有形成肖特基晶体管,但具有低Rdson且在部分电路中可作为高电压端场效晶体管使用。
图5为另一双倍扩散型金氧半导体组件的实施例剖面图,其中在接触沟槽中是包含一肖特基晶体管。于本实施例的组件500中显示,P+型材料是以一角度沉积,使反穿透植入区域502、504沿着沟槽壁而形成,而不是在沟槽底部。接触金属层506与漏极508形成一低顺向偏压的肖特基晶体管。
图6所示为另一双倍扩散型金氧半导体组件的实施例剖面图,其中是包含一肖特基晶体管。在本实施例中,组件600的接触沟槽中沉积有栓塞602、604,其可为聚合物、氧化物或颣似材料所制成,利用P+型材料沿着沟槽壁植入,以形成植入606、608;栓塞602、604可防止植入的P+离子向下延伸到栓塞的顶表面,使其可沿着沟槽壁植入,而不是沿着沟槽底部。肖特基晶体管由接触电极610及漏极612所组成。
图7为利用双倍接触蚀刻流程所形成组件的剖视图,如图所示,接触沟槽蚀刻流程是在与第3M图中组件340相似的结构上实施而形成组件700,当蚀刻屏蔽614在该结构上形成后,再利用接触沟槽蚀刻形成沟槽625,此沟槽的深度因不同植入物而有所变化。在本实施例中,将沟槽625的底部控制在与源极底部同一平面上,并将P+型材料植入到沟槽底部以形成P+区域607。执行一第二接触沟槽蚀刻,以在基体区域及N-漏极上蚀刻出沟槽,接着再沉积金属层,以形成最后结构,如图3P的350、图5的500及图6的600。在沟槽与N-漏极之间并设置一肖特基晶体管。
图8为另一双倍扩散型金氧半导体组件的实施例剖视图,如图所示,双倍接触蚀刻技术是用于沿着P+植入区域607上蚀刻出沟槽,剩余的P+植入区域在沟槽内侧沉积形成具有金属层的欧姆接触。与图4的组件490相似,双倍扩散型金氧半导体组件800不包含一完整的肖特基晶体管。此剩余的P+植入区域提供良好的穿透屏蔽,由于在底部没有P+区域,故此组件具有较低的注入效率使得基体二极管所储存的电量大幅减少。
双倍扩散型金氧半导体组件及其制作方法已于上述内容中公开,此项技术也可应用于其它半导体类型中,如绝缘栅极双载子晶体管(IGBT)和MOS控制晶闸管(MCT),以将沟道区域利用预防穿透植入理想地隔开。
上述内容,仅为本发明的较佳实施例而已,并非用来限定本发明的权利要求。故凡依本发明权利要求所述的特征及精神所作的均等变化或修饰,均应包括于本发明的权利要求内。
Claims (25)
1.一种金氧半导体组件,包括:
一漏极;
一基体,其是设置于该漏极上方,该基体具有一基体顶表面;
一源极,其是内嵌于该基体中,从该基体顶表面向下延伸至该基体中;
一栅极沟槽,其是穿过该源极及该基体而延伸至该漏极中;
一栅极,其是设置于该栅极沟槽中;以及
一源极基体接触沟槽,其具有一沟槽壁及一反穿透植入区域,该源极基体接触沟槽是沿着该沟槽壁设置。
2.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽是与该栅极沟槽邻近,并与该源极相邻。
3.如权利要求1所述的金氧半导体组件,其特征在于,其中该栅极是具有一栅极顶表面,实质上从该基体顶表面上方延伸。
4.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽是具有一沟槽底部,且该反穿透植入区域并不沿着该沟槽底部设置。
5.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽是具有一沟槽底部,且该反穿透植入区域是沿着该沟槽壁与该沟槽底部设置。
6.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽是由该基体延伸至该漏极。
7.如权利要求1所述的金氧半导体组件,其特征在于,更包括一接触电极,其是设置于该源极基体接触沟槽中。
8.如权利要求1所述的金氧半导体组件,其特征在于,更包括一接触电极,其是设置于该源极基体接触沟槽中,其中该接触电极包括一金属,其适合提供该源极和基体范围的欧姆接触。
9.如权利要求1所述的金氧半导体组件,其特征在于,更包括一接触电极,其是设置于该源极基体接触沟槽中,其中该接触电极是包括一金属,其适合提供该源极和基体范围的欧姆接触,且该接触电极包含一金属,其适用于在该漏极范围内形成一肖特基晶体管。
10.如权利要求1所述的金氧半导体组件,其特征在于,更包括一接触电极,其是设置于该源极基体接触沟槽中,其中该接触电极及该漏极可形成一肖特基晶体管。
11.如权利要求1所述的金氧半导体组件,其特征在于,更包括一接触电极,其是设置于该源极基体接触沟槽中,其中该接触电极及该漏极可在该组件之一基体二极管下方形成一肖特基晶体管。
12.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽的形成是用以拥有一平滑外型。
13.如权利要求1所述的金氧半导体组件,其特征在于,其中该反穿透植入区域中是包含以P型材料重掺杂之一范围。
14.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极的深度不超过0.5μm。
15.如权利要求1所述的金氧半导体组件,其特征在于,其中该源极基体接触沟槽是包含一栓塞。
16.一种制造半导体组件的方法,包括以下步骤:
于一基板上形成一硬屏蔽,其具有一顶基板表面;
在该基板中形成一栅极沟槽,其是穿过该硬屏蔽;
于该栅极沟槽中置入栅极材料;
移除该硬屏蔽以留下一栅极结构;
形成一源极基体接触沟槽,其具有一沟槽壁;以及
形成一反穿透植入区域。
17.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该反穿透植入区域是沿着该沟槽壁形成。
18.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该形成反穿透植入区域的步骤是包括在该沟槽壁上以一角度植入离子。
19.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该形成反穿透植入区域的步骤是包括在该沟槽壁上以一角度植入P型离子。
20.如权利要求16所述的制造半导体组件的方法,其特征在于,其中许多该栅极材料是沿着该顶基板表面设置于该沟槽中,且移除该硬屏蔽以留下在该顶基板表面上方延伸之一栅极结构。
21.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该硬屏蔽是为二氧化硅硬屏蔽。
22.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该源极基体接触沟槽具有一沟槽底部,且该方法更包括在该沟槽底部设置一接触电极。
23.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该源极基体接触沟槽具有一沟槽底部,且该方法更包括在该沟槽底部设置一接触电极,用以形成一肖特基晶体管。
24.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该形成该源极基体接触沟槽的步骤中包括执行一接触蚀刻流程。
25.如权利要求16所述的制造半导体组件的方法,其特征在于,其中该形成该源极基体接触沟槽的步骤中包括执行一第一接触蚀刻流程,并形成一包含植入材料的反穿透植入区域,再执行一第二接触蚀刻流程。
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2005
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- 2006-02-10 EP EP06720608A patent/EP1856743A4/en not_active Withdrawn
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- 2006-02-10 KR KR1020077017613A patent/KR100904378B1/ko active IP Right Grant
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Also Published As
Publication number | Publication date |
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US7285822B2 (en) | 2007-10-23 |
CN101107718B (zh) | 2012-03-28 |
US20090224316A1 (en) | 2009-09-10 |
WO2006086636A2 (en) | 2006-08-17 |
WO2006086636A3 (en) | 2007-03-01 |
US7605425B2 (en) | 2009-10-20 |
US7923774B2 (en) | 2011-04-12 |
US20120329225A1 (en) | 2012-12-27 |
US20060180855A1 (en) | 2006-08-17 |
TW200633208A (en) | 2006-09-16 |
US7800169B2 (en) | 2010-09-21 |
KR20070104578A (ko) | 2007-10-26 |
EP1856743A2 (en) | 2007-11-21 |
EP1856743A4 (en) | 2009-05-27 |
KR100904378B1 (ko) | 2009-06-25 |
US20080001219A1 (en) | 2008-01-03 |
US8597998B2 (en) | 2013-12-03 |
JP2008530800A (ja) | 2008-08-07 |
US20080001220A1 (en) | 2008-01-03 |
US8288229B2 (en) | 2012-10-16 |
US20110207276A1 (en) | 2011-08-25 |
TWI318454B (en) | 2009-12-11 |
JP5323359B2 (ja) | 2013-10-23 |
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