CN101145599B - 具有宽广相变化元素与小面积电极接点的存储器装置 - Google Patents
具有宽广相变化元素与小面积电极接点的存储器装置 Download PDFInfo
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Abstract
一种存储器单元装置,这种装置包括存储材料,可通过施加能量在第一与第二(顶部与底部)电极,改变电性;其中该顶部电极包括较大的主体部分与作用部。该存储材料以层状沉积在底部电极层之上,同时顶部电极的作用部基底与存储材料的表面小区域具有电接触。制作上述装置的方法也在其中描述。
Description
技术领域
本发明涉及高密度存储器装置,该装置采用相变化材料,包含硫属化物(chalcogenide)材料与其他材料,同时包括制造上述装置的方法。
背景技术
相变化存储器材料,已广泛运用于可读写光盘之中。这种材料至少具有两种固态相,例如,包含通常的非晶(generally amorphous)固态相与通常的结晶(crystalline)固态相。可读写光盘利用激光脉冲(laser-pulse)以改变相态,同时由此读取相变化后的材料光学性质。
采用硫属化物或其他相似材料的相变化存储器材料,也可通过集成电路施以适当强度的电流,来改变相位。通常的非晶态的电阻率高于通常的结晶态;这种电阻差异易于检测,即可代表不同数据内容。这种物质特性引发研究动机,希望利用可控制的电阻材料,制作非易失、并且可随机读写的存储器电路。
非晶态转换至结晶态的过程,通常采用较低的操作电压。由结晶态转换为非晶态的过程,则通常需要较高的操作电压;因为这一过程需要短时间且高密度的电流脉冲,以熔化或破坏结晶结构,随后快速冷却相变化材料,经淬火处理,将至少一部分的相变化结构稳定为非晶态。此后称此过程为“重置”(reset)。这一过程,通过重置电流将相变化材料由结晶态转变为非晶态,而人们希望尽量降低重置电流的强度。重置电流的强度可以通过降低存储器单元中的相变化材料元件尺寸,或者降低电极与相变化材料的接触区域大小来减少,因此较高的电流密度可以在较小的绝对电流值穿过相变化材料元件的情况下实现。
在集成电路结构中制作小孔洞(pores),为此项技术发展方向之一;同时,还采用少量的程序可控电阻材料填充该小孔洞。公开该小孔洞发展的专利包括:Ovshinsky,“Multibit Single Cell MemoryElement Having Tapered Contact”,U.S.Pat,No.5,687,112,专利发证日期1997年11月11日;Zahorik et al.,“Method of MakingChalogenide[sic]Memory Device”,U.S.Pat.No.5,789,277,专利发证日期1998年8月4日;Doan et al.,“ControllableOvonic Phase-Change Semiconductor Memory Device and Methods ofGabracting the Same,”U.S,Pat.No.6,150,253,专利发证日期2000年11月21日。
然而,为制造极小尺寸的上述装置,并促使工艺参数的变化能符合大型存储器装置所需的严谨规格,衍生出许多问题。因此必须发展具有小尺寸、与低重置电流的存储器结构,同时发展此种存储器结构的制作方法。
发明内容
一般而言,本发明的特征,包括一种可利用能量,促使可变存储器材料改变电的存储器单元装置,该材料位于第一与第二(“底部”与“顶部”)电极之间。本发明就存储器单元装置的实施例中,顶部电极包括较大的主体部分与一个作用部。存储器材料层沉积于底部电极层之上,同时顶部电极的一个作用部基底,与存储器材料表面的小区域产生电接触。电接触区域由靠近基底的电极作用大小所决定,而并非由尺寸显然较大的存储器材料大小所决定。电极顶部的作用部大小,以及作用底部与存储器材料接触区域的大小,得依据本发明变得非常小,且不需依赖掩模技术。
本发明的一个目的为提供一种存储器装置,包括:衬底;电极,其位于所述衬底之上;存储元素,其与所述电极有电接触;电介质填充层,其位于所述存储元素、所述电极与所述衬底之上,所述电介质填充层包括空洞,所述空洞延伸至所述存储元素,并具有一宽度;蚀刻停止层,其位于所述电介质填充层上,所述蚀刻停止层具有一开口,该开口位于空洞正上方,并且开口与空洞相邻且连通,所述开口具有一宽度,所述宽度小于所述电介质填充层空洞宽度,所以一开口边缘突出到所述电介质填充层中的空洞的正上方;以及第二电极,其位于所述电介质填充层空洞中,所述第二电极包括主体部分与作用部,其中所述作用部的基底与所述存储元素的表面的一小区域电接触。本发明的另一目的为提供一种形成存储器单元的电极的方法,包括:在存储元素上提供电介质填充层;在所述电介质填充层上提供蚀刻停止层;形成通孔穿越所述电介质填充层与开口穿越所述蚀刻停止层,其中所述蚀刻停止层开口的边缘,突出一刃边在所述电介质填充通孔之上;在所述通孔中沉积电介质种类材料,其中在所述电介质种类材料中形成空洞;各向异性蚀刻所述电介质种类材料以在所述种类材料中形成孔隙,且暴露所述存储元素的表面的一小区域;以及在所述孔隙中沉积电极材料。
本发明的另一目的为提供一种制造存储器单元装置的方法,包括:提供衬底;在所述衬底的表面上形成底部电极层;在所述底部电极层之上形成存储器材料层;将所述存储器材料层与所述底部电极层图案化以形成存储元素与底部电极;在所述存储元素、所述底部电极与所述衬底之上形成电介质填充层;在该电介质填充层上形成蚀刻停止层;形成通孔,所述通孔穿越所述蚀刻停止层与所述电介质填充层,以暴露所述存储元素的一区域,而所述通孔还包括在所述蚀刻停止层中的开口;从该通孔的内壁去除一定数量的所述电介质填充层以形成空洞,以及在所述蚀刻停止层的所述开口边缘下方生成下方侧削区;在所述空洞中的所述存储器材料层之上沉积绝热材料,其中在所述绝热材料之中形成空隙;各向异性蚀刻所述绝热材料以暴露所述存储元素的表面的一小区域,并形成孔隙在所述绝热材料中邻近所述存储元素处,以及较宽空洞在所述绝热材料中;以及在所述孔隙与所述较宽空洞中沉积电极材料以形成顶部电极。
依据本发明,掩模阶段可在存储器单元通孔上方的氮化硅层建立开口。其余的工艺即属自动对准,并具高度重复性。顶部电极与存储器材料之间的接触区域,由顶部电极的作用部宽度所决定,而该宽度又受到各向异性蚀刻的条件、以及绝热材料空隙的尺寸与形状所影响,前述条件均可轻易地重复控制。
附图说明
图1为依据本发明的一种实施例,显示一种存储器单元装置的示意图;
图2、图3、图4、图5、图6、图7、图8、图9、与图10,为依据本发明所的一种实施例,显示一种相变化存储器单元工艺步骤的剖面示意图;
图11A与图11B为依据本发明的一种实施例,显示一种存储器阵列的一部分的剖面图;图11B显示编程电流的流动路径;
图12为采用相变化存储元件的存储器阵列示意图;
图13显示存储器阵列的布局图或平面图,其显示采用相变化存储元件的存储器阵列的一部分。
具体实施方式
此处将依据附图,更详细说明本发明的内容,同时展示本发明的另一实施例。此附图仅为概略图,显示本发明的特征与这种特征和其他特征与结构的关系,故也未按比例制作。为使说明书的内容更加容易明了,显示本发明实施例的附图中,对应其他附图中特征的特征元件,即使可轻易在所有附图中辨别,均未加以重新编号。
请参阅图1,为根据本发明的一个实施例的存储器单元结构10的示意图。存储器单元结构10包括重叠在存储元素14之下的底部电极12、与内含主体部分19及作用部17的顶部电极18。顶部电极18的作用部17经由小面积接点13与存储器材料层14的表面15接触。此外还可选择在电极顶部加入一核心部分21与一内衬(加热)部分23。顶部电极18的周围由绝热材料16所包围。顶部电极与周边的绝热材料,形成在层间电介质填充层的通孔中,或形成在分隔层(separation layer)11中,而分隔层11,为电绝缘层20所覆盖。
存储器结构10形成在半导体衬底之上,包含存取晶体管、以及顶部电极18的电连结表面22,均由图案金属化制造,如下列参考图11A的例子。
存储器单元中的传导路径,由顶部电极18的表面22穿过顶部电极的主体部分19与顶部电极的作用部17,随后穿越作用部17底部的接触区域13,至存储元素14,再穿越该存储元件,达到底部电极12。
本发明的存储单元结构提供几种优势特征。顶部电极与周边电介质填充物的绝热良好,顶部电极与存储器材料的接触区域甚小,故可降低重置程序的电流。顶部电极与存储器材料的接触区域由顶部电极的作用部宽度决定,而该宽度乃受到各向异性蚀刻条件、与绝热层中的空隙尺寸及形状的影响。绝热层空隙的大小,由电绝缘层开口边缘的下方侧削区域320宽度决定,前述条件均可轻易地重复控制。
存储单元装置10的实施例,利用包括硫属化物在内的材料与其他的材料,作为存储器材料14。相变化合金可在两种结构状态间进行变换,第一结构状态通常为非晶固态相,而第二结构则通常为结晶固态相,并在存储器单元的主动通道区域,按其局部晶向排列。这种合金区域至少有两种稳定态;“非晶”指较之单晶而言,较无固定晶向的结构,例如较结晶相具有更高的电阻率等特性。“结晶”则指相对于非晶结构而言,较有固定晶向的结构,例如较非晶相具有更低的电阻率等特性。通常而言,可在完全非晶态与完全结晶态之间,利用电流变换相变化材料的相态。非晶态与结晶态转换所影响的其他材料性质,还包含原子排列、自由电子密度与活化能。这种材料可转换为两种相异的固态相,还可转换为两种固态相的组合,故可在大致非晶相与大致结晶相之间,形成灰色地带,材料的电子性质亦将随之转换。
相变化合金可利用电脉冲改变相态。就过去的观察,得知波长较短、振幅较大的脉冲,较倾向将相变化材料转为通常的非晶态。波长较长、而振幅较低的脉冲,则易将相变化材料转为通常的结晶态。波长短、振幅高的脉冲,能量较高,足以破坏结晶态的键合,同时短波长可防止原子重新排列为结晶态。无须大量实验,即可获得适当的脉冲参数,以应用于特定的相变化合金。就此公开的,相变化材料指GST等,同时应理解仍可采用其他相变化材料。在此,供存储器装置制作所用的材料,为Ge2Sb2Te5。
再度参照图1,可运用如图12所示的存取电路(accesscircuitry),将其与第一电极12和第二电极18连结,利用各种组态设定的变化,控制存储器单元的运作;由此即可利用电脑程序,控制相变化材料14,重复在存储器材料中进行两种固态相之间的转换。例如,利用硫属化物相变化存储器材料,可将存储器单元设定在相对高电阻的状态;其中,至少一部分的电流路径桥(bridge)属于结晶态。又例如,一种电脉冲的应用,具有适当的短波长高振幅特性,即可能造成相变化材料14局部改变(locally change)为通常非晶态,如图1的29所示。
存储器单元装置10的工艺说明,请参考图2至图10,其中说明示范工艺的各个阶段代表图。
参考图2,一种适于作为底部电极的材料层212形成在衬底210的表面211之上;底部电极材料层212之上,形成一层相变化存储器材料214;以及,相变化存储器材料层214之上,形成一层保护覆盖层材料226。
底部电极材料层212,可采用薄膜沉积等技术制作,例如,以溅射法或原子层沉积法,令其附着在衬底210的表面211上。适当的底部电极层212可能包括两层以上的材料,并依据其性质,选择附着在连接层的材料上。例如,底部电极层212可能包含一层钛薄膜,再在钛薄膜的表面形成一层氮化钛薄膜。钛与下方的半导体衬底(例如硅化物)具有良好的附着性,同时氮化钛与上方的GST相变化材料也具良好附着性。此外,氮化钛可作为优良的扩散屏障。底部电极可采用多种材料,例如,包含Ta、TaN、TiAIN、TaAIN;至于底部电极的材料,则可由Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、与Ru等元素族与合金中选择搭配,也可加入陶瓷。沉积工艺的条件,必须得以提供电极层材料所需的适当厚度与涵盖范围(coverage),同时提供良好的绝热性质。衬底表面的底部电极厚度范围约在200nm至400nm之间。
底部电极层212上的相变化存储器材料层214,可采用溅射法或原子沉积法等薄膜沉积工艺制作。沉积工艺的条件,需要提供底部电极上方相变化材料层足够的厚度。衬底上的底部电极表面的相变化材料层,厚度范围约在20-200nm之间。
保护覆盖层226在随后的工艺中保护下方的相变化存储器材料。适于保护覆盖层226的材料包含,例如氮化硅、SiO2、Al2O3、Ta2O5,而该覆盖层可能采用CVD或PVD工艺制作。保护覆盖层226的厚度范围约为5nm至50nm。底部电极层、相变化存储器层、与保护覆盖层的结构种类,即如图2。
随后,利用掩模与蚀刻工艺,在存储器单元30上制作如图3所示的结构,其中底部电极12的上方,还有相变化材料14与覆盖层326。覆盖层326的表面315,可在光刻胶与蚀刻工艺中保护相变化材料元件;此外,更可在某些实施例中,在除去(剥除)光刻胶步骤中保护相变化材料元件。
此时,层间电介质填充层形成在衬底表面之上,同时亦形成在图案化的底部电极、存储元件、与覆盖层之上,而层间电介质填充层之上又再形成蚀刻停止层。层间电介质填充层可能包括如低电介质常数的电介质材料,例如二氧化硅、氮氧化硅、氮化硅、Al2O3、或其他低电介质常数的电介质物质。此外,层间电介质填充层的材料亦可能包括Si、Ti、Al、Ta、N、O与C等族群中的一种或多种元素组合。蚀刻终止层的材料,则可能包含氮化硅等。通孔,则利用掩模与蚀刻工艺制作,穿越蚀刻停止层与电介质填充物。图4展示依此制作的存储器单元通孔200,其位于蚀刻停止层20与电介质填充物层211之上。该通孔直达覆盖层326的表面315,而该覆盖层位于相变化材料元件14之上。此时,可利用诸如氢氟酸浸渍等湿蚀刻技术,以在下方侧削电介质填充材料,同时在电介质填充物11中扩大空洞300,如图5所示。
完成存储器单元的尺寸,将受到存储器单元通孔尺寸的部分影响,尤其受到下方侧削程度的影响,诸如图6与图7所示。
层间电介质填充层的厚度可能约为100nm至300nm,而氮化硅层的厚度范围则约为10nm至40nm。通孔200的宽度范围约为30nm至300nm。穿越氮化硅层的开口220,则可能随通孔200所采用的特定光刻工艺设计方式,而有所变化(通常+/-20nm)。氮化硅层上的开口直径220通常为环状,例如直径220约为200nm+/-约20nm。蚀刻终止层20的材料,需选用相对于电介质填充材料具有蚀刻选择性的;亦即,用以去除电介质材料,以形成下方侧削区域320的湿蚀刻工艺,不可对蚀刻终止层20产生影响。其中二氧化硅为电介质填充材料,例如氮化硅即为适当的蚀刻终止层材料。下方削除的程度,可由湿蚀刻的时间控制,例如,其通常变化范围为+/-1.5nm。湿蚀刻的条件,必须能在氮化硅层的开口边缘下方,提供宽度321范围约为5nm至50nm的下方侧削区,造成宽度为311的空缺300,其宽度约为氮化硅层的开口宽度总值220加上下方侧削区320的宽度321的两倍。
保护覆盖层326,可在制作通孔200的蚀刻工艺与拓展电介质填充物空洞300所运用的湿蚀刻工艺中,保护下方的相变化存储元件14。
此时可在图5的结构上形成适合的绝热材料,并在通孔中利用如化学气相沉积(CVD)等顺形沉积工艺,形成如图6所示的结构。下方侧削的几何结构,以及沉积工艺的条件,均会影响绝热材料600中空洞610的种类。空洞610大概位于存储器单元通孔的中心位置。空洞的形状与宽度613(或直径,因空洞通常为圆形,例如环状)与下方侧削区域320的宽度相关;例如,若蚀刻终止层20的开口通常为环状,通常则可预期空洞亦为环状,同时可预测其直径613约为下方侧削区321宽度的两倍。
适当的绝热材料600,包括电介质材料,也可能为氧化物,如二氧化硅。可能有其他更佳的绝热材料,而绝热材料的选择,同时需将层间电介质填充层的材料纳入部分考量;尤其,较之层间电介质填充层11,绝热材料600为更佳的绝热材料,效能至少提升10%。因此,若层间电介质层包括二氧化硅,绝热层600的导热数“kappa”最好小于该二氧化硅的0.014J/cm*K*sec。低介电常数材料属于绝热层600所需的代表性材料之一,其中包括由硅(Si)、碳(C)、氧(O)、氟(F)、与氢(H)所构成的组合。其他适于绝热材料600的选择,包含SiCOH、聚亚酰胺(polyimide)、聚酰胺(polyamide)以及氟碳聚合物。至于其他可用在绝热层600的材料例子则为氟化SiO2、硅酸盐、芳香醚、聚对二甲苯(parylene)、聚合氟化物、非晶氟化碳、类金刚石碳、多孔二氧化硅、中孔二氧化硅(mesoporous silica)、多孔硅酸盐、多孔聚亚酰胺与多孔芳香醚。单一层或多层结构的组合,均可提供绝热功能。其他具体实施例中,绝热材料的导热系数均需小于非晶态的相变化材料GST,即小于0.003J/cm*K*sec。
稍后施以各向异性蚀刻(例如反应离子蚀刻),以去除部分的绝热材料。蚀刻工艺需持续至覆盖层316的表面暴露为止,并需暴露相变化元素14的表面15上的区域13,方可停止。某些具体实施例中,第一次蚀刻条件为去除绝热材料,而第二次蚀刻条件则为除去覆盖层部分(例如,可能利用不同的蚀刻化学品)。图7显示由此建立的结构。蚀刻停止层20上的所有绝热材料均遭去除;同时,部分存储器单元空隙的绝热材料亦遭去除,并在相变化材料表面附近形成孔隙712;该孔隙界定出顶部电极的作用部;此外,较宽的空缺710将划分顶部电极的主体部分。下方侧削区320保护其下的绝热材料,留下剩余部分720,邻近于空隙侧壁与空隙侧壁旁的相邻相变化材料。当相变化材料表面的小区域13暴露在孔隙712的底部时,蚀刻即停止;蚀刻停止后仍保留剩余部分722,而此部分将决定孔隙712的形状与大小。顶部电极作用部的大小,以及顶部电极与相变化材料接触面积的大小,均有部分受到空隙位置和尺寸的影响,以及受到绝热材料600的的沉积均匀程度影响。尤其,孔隙712底部的相变化材料14上,所露出的小区域13的宽度(例如,若为环状则为直径),即与蚀刻条件一样,也受到空隙形状和尺寸的影响。如前述,空隙的宽度(或直径)与下方侧削区的宽度有关,而并非受到通孔宽度的影响;通常空隙的宽度,大约为下方侧削区宽度的两倍。空隙的位置(以及孔隙712)大约位于通孔的中央,同时由在存储器材料元素具有一较大的区域,故无须将通孔精确对准于存储器材料元素。
暴露的小区域13不须为任何特定形状,例如,通常可能为圆形(如环状)、或其他形状、亦可能为不规则形状。若该小区域为环状,小区域13半径约可为10nm至100nm,例如20nm至50nm,或约30nm。利用此处所记载的条件,就下方侧削区的宽度的估计的尺寸大小约为5nm至50nm,例如10nm至25nm,或约15nm。
此时可在存储器单元空洞中,形成顶部电极。如图示的实施例中,顶部电极包含由内衬(加热)部分所包围的核心。就本实施例而言,该内衬在图7的构造上,沉积适当的内衬材料,形成如图8的构造。内衬材料可填充孔隙712,形成顶部电极的作用部17;同时也在其他结构表面上形成薄膜723。适当的内衬材料包含氮化钽、氮化钛、氮化钨、TiW。沉积工艺的条件必须能够提供电极层材料适当的厚度与足够的覆盖率。随后即可在图7的结构上,沉积适当的材料在空缺之中,形成顶部电极的核心,如图9中的900所示。该核心材料可采用化学器相沉积(CVD)等沉积方法。而顶部电极900,则可能为钨等材料。此外尚有其他适合作为顶部电极核心的材料,就金属而言,可采用铜、白金、钌、铱、以及其合金。
顶部电极可采用多种材料,例如包含Ta、TaN、TiAIN、TaAIN;或者,顶部电极材料亦可包括由Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni与Ru等族群中,选择一种或多种元素,制成合金,或加入陶瓷。
随后,以平坦化工艺去除上方材料,直达氮化硅层20的表面922,以形成完整的存储器单元结构如图10。
图11A显示本发明的二相变化随机存取存储器单元100、102的代表图。该单元100、102形成在半导体衬底110之上。诸如浅沟槽绝缘(STI)电介质沟槽112等绝缘结构,作为两行存储器单元存取晶体管的绝缘体。存取晶体管由衬底110上的共同源极区域116与衬底112上的漏极区域115与117所形成。多晶硅中布有字线113与114,此二者组成存取晶体管的栅极。共同源极线119形成在源极区域116之上,而第一电介质层111则沉积在衬底110之上,并覆盖前述多晶硅字线与共同源极线。接触拴塞103、104(例如钨)形成在填充层111的通孔中,而该通孔位于存储器单元100与102的漏极区域115、117之上。一般而言,存储器单元100与102的制作,通常可依据前述图2至图10的方法;同时存储器单元101与102的结构,通常会与第一图中的存储器单元10相同。随后,底部电极材料层沉积在第一电介质填充层之上,存储器材料层沉积在底部电极材料层之上,而保护覆盖材料层也沉积在底部电极材料层之上。上述各层均已图案化(patterned),以形成底部电极,用以连接底部电极上的接触插座、存储元件、和存储元件上的覆盖层。第二电介质填充层121则沉积在前述结构之上,而第二电介质填充层之上又沉积蚀刻停止层,蚀刻停止层与第二电介质填充层再经过掩模与蚀刻工艺,形成通孔,之后再利用湿蚀刻技术,制作空洞;该空洞位于蚀刻终止层的开口边缘处,并具有下方侧削区域。此时在空洞之中沉积绝热材料(形成空隙),并在该绝热材料与覆盖层之上施以各向异性蚀刻,形成空缺,并暴露存储元素表面的一块小区域,而顶部电极则形成在该空洞之中。该结构的上层表面经平坦化程序,同时位线(bit line)141形成在存储器单元之上,与顶部电极的上层表面产生接触。
图11B显示编程的电流路径(箭头129),如本发明的图1与图11A所述,穿越存储器单元。该电流由M1共同源极线119流向源极区域116,随后进入漏极区域115,再由漏极区域115穿越接触拴塞103,进入存储器单元110,并穿越存储器单元100至位线141。
图12为存储器阵列的代表图,其操作方法如下。依据图2所示,一共同源极线128、一字线123、与一字线124以通常的Y轴平行方向排列;位线141与142则以通常的X轴平行方向排列。因此,区块145中的一Y解码器(decoder)与一排线驱动器即与字线123和124耦合。区块146中的一X解码器与一组感应扩大器(sense amplifier)即与位线141和142耦合。共同源极导线128与存取晶体管150、151、152、和153的源极终端(source terminals)耦合,存取晶体管150的栅极与字线123耦合、存取晶体管151与字线124耦合、存取晶体管152与字线123耦合、而存取晶体管153则与字线124耦合。存取晶体管150的漏极与存储器单元135的底部电极单元(member)132耦合,而其顶部电极单元则为134,与位线141耦合。同样地,存取晶体管151的漏极与存储器单元136的底部电极单元133耦合,其顶部电极137则与位线141耦合。存取晶体管152与153的相对应存储器单元,同样地与位线142进行耦合。在此示意图中,共同源极线128由两排存储器单元所共享,其中一排的排列方式即如图所示,为Y轴方向。其他实施例中,可以二极体取代存取晶体管,而如有其他可在读写数据阵列之中控制电流流向的结构,亦可适用。
图13图13图13为依据图12存储器阵列示意图,所展示之一布局图或平面图,其内容显示图11A中,半导体衬底层110之下的结构。其中省略某些特征,或以空白代表。字线123与124与源极导线28平行排列,金属位线141与142则布置在其上,与字线垂直。存储器单元装置135的位置,位于所述金属位线之下,但未显示在本图之中。
存储器单元10的实施例,包含相变化存储器材料,该存储器材料14所采用的内容物包含硫属化物材料与其他材料。硫属化物可能包括氧(O)、硫(S)、硒(Se)、碲(Te)等四种元素,为元素周期表第六族的一部分。硫属化物包括硫族元素的化合物,以及一种正电性较强的元素或化合物基(radical);硫属化物合金则包括硫族元素与其他元素的组合,例如过渡金属。硫属化物合金通常包括一种以上的元素周期表第六族元素,例如锗(Ge)和锡(Sn)。通常,硫属化物合金中包括一种以上的锑(Sb)、镓(Ga)、铟(In)、与银(Ag)元素。文献中已有许多种类的相变化存储器材料,例如下列合金:Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te、以及Te/Ge/Sb/S。Ge/Sb/Te的合金家族中,许多合金组合均可作为相变化存储器材料,此类组合可特定为TeaGebSb100-(a+b)。已有研究人员指出,效能最佳的合金,其沉积材料中的Te平均浓度均低于70%,通常低于60%,而其范围多为23%至58%之间,最佳浓度又为48%至58%的Te。Ge的浓度则为5%以上,范围约为8%至30%之间,通常低于50%。最优选实施例中,Ge的浓度范围约为8%至40%。该组成中,最后一项主要组成元素为Sb。上述百分比,指原子百分比,而总原子百分比100%即为组成元素的总和。(Ovshinsky’112 patent,columns 10-11)。另一研究人员所评估的特定合金包括Ge2Sb2Te5、GeSb2Te4、与GeSb4Te7(NoboruTamada,“Potential of Ge-Sb-Te Phase-Change Optical Disks forHigh-Data-Rate-Recording”,SPIE v.3109,pp.28-37(1997))。就更为普遍的面向,过渡金属,例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt),与上述元素的合金,均可能与Ge/Sb/Te组成相变化合金,并使其具备程序可编程电阻的性质。可作为存储器材料的特定例子,见于Ovshinsky’112 at column 11-13,此处的所记载的例子即为参考上述文献所作出的组合。
本发明的说明如上,并附带说明相变化材料。然而,仍有其他可编程材料,可作为存储器材料。就本应用而言,存储器材料指可施加能量以改变电性(例如电阻)的材料,而此种改变可为阶梯状区间、或为连续变化、亦可为两者的组合。其他实施例中,还可采用他种可编程电阻存储器材料,包含掺杂N2的GST、GexSby、或其他利用晶相变化决定电阻的;也可采用PrxCayMnO3、PrSrMnO、ZrOx或其他以电脉冲改变电阻的材料;7,7,8,8-tetracyanoquinodimethane(TCNQ)、methanofullerene 6,、6-phenyl C61-butyric acid methyl ester(PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、TCNQ掺杂其他金属、或其他具有双重或多种稳定电阻状态,并可由电脉冲控制的高分子材料。其他可编程电阻存储器材料的例子,包含GeSbTe、GeSb、NiO、Nb-SrTiO3、Ag-GeTe、PrCaMnO、ZnO、Nb2O5、Cr-SrTiO3。
若需更多关在制造、组成材料、使用与操作相变化随机存取存储器装置的信息,请见美国专利申请号11/155,067,申请日2005年,专利申请名为“Thin film fuse phase change RAM andmanufacturing method”。
其他实施例也属于本发明的范畴。
Claims (24)
1.存储器装置,包括:
衬底;
电极,其位于所述衬底之上;
存储元素,其与所述电极有电接触;
电介质填充层,其位于所述存储元素、所述电极与所述衬底之上,所述电介质填充层包括空洞,所述空洞延伸至所述存储元素,并具有一宽度;
蚀刻停止层,其位于所述电介质填充层上,所述蚀刻停止层具有一开口,该开口位于空洞正上方,并且开口与空洞相邻且连通,所述开口具有一宽度,所述宽度小于所述电介质填充层空洞宽度,所以一开口边缘突出到所述电介质填充层中的空洞的正上方;以及
第二电极,其位于所述电介质填充层空洞中,所述第二电极包括主体部分与作用部,其中所述作用部的基底与所述存储元素的表面的一小区域电接触。
2.如权利要求1所述的存储器装置,其中所述小区域具有约为在所述蚀刻停止层中的所述开口边缘突出部分的宽度的两倍的宽度。
3.如权利要求1所述的存储器装置,其中所述第二电极位于所述电介质填充层空洞中,并为绝热材料所包围。
4.如权利要求3所述的存储器装置,其中所述第二电极的所述作用部位于所述绝热材料的孔隙之中。
5.如权利要求4所述的存储器装置,其中所述孔隙具有约为在所述蚀刻停止层中的所述开口边缘突出部分的宽度的两倍的宽度。
6.一种形成存储器单元的电极的方法,包括:
在存储元素上提供电介质填充层;
在所述电介质填充层上提供蚀刻停止层;
形成通孔穿越所述电介质填充层与开口穿越所述蚀刻停止层,其中所述蚀刻停止层开口的边缘,突出一刃边在所述电介质填充通孔之上;
在所述通孔中沉积电介质种类材料,其中在所述电介质种类材料中形成空洞;
各向异性蚀刻所述电介质种类材料以在所述种类材料中形成孔隙,且暴露所述存储元素的表面的一小区域;以及
在所述孔隙中沉积电极材料。
7.如权利要求6所述的方法,其中所述电介质种类材料包括绝热材料。
8.如权利要求6所述的方法,其中形成所述通孔的步骤,包括去除一部分位于所述蚀刻停止层开口边缘之下的所述电介质种类材料。
9.如权利要求6所述的方法,其中所述空洞的宽度约为突出的刃边的宽度的两倍。
10.如权利要求6所述的方法,其中所述存储元素的所述表面的所述小区域的宽度,约为突出的刃边的宽度的两倍。
11.一种制造存储器单元装置的方法,包括:
提供衬底;
在所述衬底的表面上形成底部电极层;
在所述底部电极层之上形成存储器材料层;
将所述存储器材料层与所述底部电极层图案化以形成存储元素与底部电极;
在所述存储元素、所述底部电极与所述衬底之上形成电介质填充层;
在该电介质填充层上形成蚀刻停止层;
形成通孔,所述通孔穿越所述蚀刻停止层与所述电介质填充层,以暴露所述存储元素的一区域,而所述通孔还包括在所述蚀刻停止层中的开口;
从该通孔的内壁去除一定数量的所述电介质填充层以形成空洞,以及在所述蚀刻停止层的所述开口边缘下方生成下方侧削区;
在所述空洞中的所述存储器材料层之上沉积绝热材料,其中在所述绝热材料之中形成空隙;
各向异性蚀刻所述绝热材料以暴露所述存储元素的表面的一小区域,并形成孔隙在所述绝热材料中邻近所述存储元素处,以及较宽空洞在所述绝热材料中;以及
在所述孔隙与所述较宽空洞中沉积电极材料以形成顶部电极。
12.如权利要求11所述的方法,其中形成所述存储器材料层的步骤,包括沉积至少具有两种固态相的材料。
13.如权利要求12所述的方法,其中形成所述存储器材料层的步骤,包括沉积至少具有两种固态相的材料,所述固态相可通过施加穿越所述底部电极与顶部电极的电压,可逆地改变相态。
14.如权利要求12所述的方法,其中形成所述存储器材料层的步骤,包括沉积至少具有两种固态相的材料,所述固态相包括通常的非晶态与通常的结晶态。
15.如权利要求12所述的方法,其中形成所述存储器材料层的步骤,包括沉积合金,所述合金的材料包括Ge、Sb、Te组成的组合。
16.如权利要求12所述的方法,其中形成所述存储器材料层的步骤,包括沉积合金,所述合金的材料包括由两种或以上Ge、Sb、Te、Se、In、Ti、Ga、Bi、Sn、Cu、Pd、Pb、Ag、S与Au元素组成的组合。
17.如权利要求11所述的方法,其中形成所述通孔穿越所述蚀刻停止层与所述电介质填充层的步骤,包括掩模与蚀刻步骤。
18.如权利要求11所述的方法,其中去除一定数量所述电介质填充层的步骤,包括湿蚀刻工艺。
19.如权利要求11所述的方法,其中形成所述顶部电极的步骤,包括在所述孔隙与所述较宽空洞中形成内衬,同时包括在所述内衬之上形成核心。
20.如权利要求11所述的方法,其中从所述通孔内壁去除一定数量所述电介质填充层的步骤,包括形成下方侧削区,其具有为5nm至50nm的宽度。
21.如权利要求11所述的方法,其中从所述通孔内壁去除一定数量所述电介质填充层的步骤,包括形成下方侧削区,其具有为10nm至25nm的宽度。
22.如权利要求11所述的方法,其中从所述通孔内壁去除一定数量所述电介质填充层的步骤,包括形成下方侧削区,其具有为15nm的宽度。
23.如权利要求11所述的方法,其中所述孔隙的宽度为所述下方侧削区宽度的两倍。
24.如权利要求11所述的方法,其中所述存储元素的所述表面的所述小区域的宽度,为所述下方侧削区的宽度的两倍。
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