CN101159312B - 具有向周围延伸的存储元件的存储单元器件 - Google Patents
具有向周围延伸的存储元件的存储单元器件 Download PDFInfo
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Abstract
本发明涉及一种具有可通过施加能量而在电性状态之间切换的存储材料的存储单元器件,其具有底电极构件、顶电极构件以及位于顶电极构件与底电极构件之间的电介质材料。此顶电极以及底电极构件具有彼此大致对准的环绕向外延伸的外表面。存储元件包含存储材料,至少部分环绕且与该底电极构件和该顶电极构件的该外表面电接触,以在该电介质材料中产生存储元件转换区域。在某些实施例中,底电极构件、该顶电极构件以及该电介质材料定义材料堆叠,该材料堆叠具有延伸于该底电极构件和该顶电极构件之间且通过该电介质材料的方向的长度,以及延伸垂直于该长度且具有亚光刻尺寸的宽度。
Description
技术领域
本发明涉及以可编程电阻材料为基础的高密度存储器件,例如以相变化为基础的存储材料,以及用以制造这种器件的方法。
背景技术
以相变化为基础的存储材料被广泛地运用于读写光盘中。这些材料包括有至少两种固态相,包括如大部分为非晶态的固态相,以及大体上为结晶态的固态相。激光脉冲用于读写光盘中,以在两种相中切换,并读取这种材料在相变化之后的光学性质。
如硫属化物及类似材料的这种相变化存储材料,可通过施加幅度适用于集成电路中的电流,而致使晶相变化。这种特性则引发使用可编程电阻材料以形成非易失性存储器电路等兴趣。
此领域发展的一种方法为致力于在集成电路结构上形成微小孔洞,并使用微量可编程的电阻材料填充这些微小孔洞。致力于这种微小孔洞的专利包括:于1997年11月11日公布的美国专利第5,687,112号“Multibit Single CellMemory Element Having Tapered Contact”、发明人为Ovshinky;于1998年8月4日公布的美国专利第5,789,277号“Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等;于2000年11月21日公布的美国专利第6,150,253号“Controllable Ovonic Phase-ChangeSemiconductor Memory Device and Methods of Fabricatingthe Same”、发明人为Doan等。
在相变化存储器中,数据通过使用电流而致使相变化材料在非晶态以及结晶态中的变化而储存。电流会加热此材料,并导致在此两种态之间的变化。从非晶态转变至结晶态一般为低电流步骤。从结晶态转变至非晶态(以下称为重置(reset))一般为较高电流步骤。理想状态下,致使相变化材料从结晶态转变至非晶态的重置电流幅值应越低越好。欲降低重置所需的重置电流幅值,可通过减低在存储器中的相变化材料器件的尺寸而达成。与相变化存储器件有关的问题之一在于,用以重置操作的电流幅值取决于相变化材料中需要进行相变化部分的体积。因此,使用标准集成电路工艺所制造的单元,将受限于工艺设备的最小特征尺寸。因此,需要一种可提供亚光刻尺寸给存储单元的技术,其可提供大规模、高密度存储器件所需要的一致性或可靠性。
一种用以在相变化单元中控制活性区域的尺寸的方法,为设计非常微小的电极,以导通电流至相变化材料本体。此微小电极结构将诱使在相变化材料中接点处如蘑菇顶端的一小部分发生相变化。请参见美国专利第6,429,064号、公布于2002/8/6、申请人为Wicker的“Reduced Contact Areasof Sidewall Conductor”;美国专利第6,462,253号、公布于2002/10/8、申请人为Gilgenr的“Method forFabricating a Small Area of Contact BetweenElectrodes”;美国专利第6,501,111号、公布于2002/12/31、申请人为Lowrey的“Three-Dimensional(3D)Programmable Device”;美国专利第6,563,156号、公布于2003/7/1、申请人为Harshfield的“Memory Elements andMethods for Making Same”。
因此,则有机会设计形成存储单元的方法与结构,此存储单元具有微小的可编程电阻材料活性区域,并使用可靠且可重复的制造技术。
发明内容
本发明涉及一种具有存储材料可通过施加能量而在电性状态之间切换的存储单元器件。此存储单元器件具有底电极构件、顶电极构件以及电介质材料位于顶电极构件与底电极构件之间。此顶电极构件具有环状向外延伸的外表面。而此顶电极构件在该底电极构件之上,该顶电极构件具有与该底电极构件的该外表面大致对准的环状向外延伸的外表面。存储元件包含存储材料,至少部分环绕且与该底电极构件和该顶电极构件的该外表面电接触,以在该存储元件的中央部分产生存储元件转换区域。在某些实施例中,底电极构件、该顶电极构件以及该电介质材料定义一材料堆叠,该材料堆叠具有延伸于该底电极构件和该顶电极构件之间且通过该电介质材料的方向的长度,以及延伸垂直于该长度且具有亚光刻尺寸的宽度。在某些实施例中,此存储元件为管状。
制造具有存储材料可通过施加能量而在电性状态之间切换的存储单元器件的方法的一个范例如下。存储单元存取层被形成,其包含底电极以及上表面,该底电极具有底电极表面于该上表面。具有环绕向外延伸的外表面的材料堆叠被形成于该底电极表面上,上导电材料层与下导电材料层之间包含电介质材料层。存储材料层被形成于该外表面,以至少部分环绕该材料堆叠。此存储材料被电介质材料所环绕。顶电极被形成且与该材料堆叠的该上层材料接触。在某些实施例中,此材料堆叠形成步骤包含下列步骤。由第一导电材料形成的第一层被沉积于该存储单元存取层的上表面之上。电介质材料层被沉积于该第一层之上。由第二导电材料形成的第二层被沉积于该电介质材料层之上。掩模被形成于该第二层之上,该掩模与该底电极表面对准。此掩模被图形化以产生亚光刻尺寸图形化掩模。而未被该图形化掩模覆盖的材料被去除,以产生亚光刻尺寸材料堆叠。
本发明还公开了一种包括有存储阵列的集成电路,其包 括多个具有存取晶体管的这种存储器件,其以高密度的行(column)、列(row)阵列方式安排。此存取晶体管在半导体衬底中包括有源极与漏极区域,且包括沿着存储单元的列方向耦合到字线的栅极。此存储单元形成于此集成电路的晶体管之上的一层中,且具有接触至相对应的存取晶体管的漏极的底电极。位线以一层位于存储单元上的金属层而形成,此存储单元在阵列中沿着存储单元的行方向而接触至此存储器件的顶电极。在一个实施例中,两列存储单元共用源极接点,且源极线耦合到源极接点,并在此阵列中大致上以与字线平行的方向延伸。
可靠的存储单元结构可利用低电流操作,并可利用标准光刻与沉积工艺制造的。此单元结构特别适用于制造大规模集成电路中的CMOS电路。
以下详细说明本发明的结构与方法。本发明说明书目的并非在于定义本发明。本发明由权利要求书所定义。本发明的所有实施例、特征、观点及优点等将可通过下列具体实施方式及附图获得充分了解。
附图说明
图1是根据本发明的一个实施例的存储单元器件的截面图,此存储元件包括环绕电介质材料的环状向外延伸的部分,以及顶电极和底电极延伸部分;
图2是沿着图1中2-2线的简化剖面图;
图3是包括有如图1中的存储单元的存储阵列的电路图;
图4是包括有如图1中的存储单元器件以及其他电路的集成电路器件的方块图;
图5是本发明的一个实施例中的两个单元阵列结构的剖面图;
图6-15示出用以制造如图5中的存储单元阵列结构时 的各对应工艺步骤;
图16和图17显示图1中存储单元器件的某些部分的替代实施例。
具体实施方式
以下参照附图进行详细说明。优选实施例仅用以说明本发明,而非用以限制其范围,本发明的范围以权利要求书界定。本领域技术人员应能依据下列说明而理解本发明的等效变化。在不同实施例中的相同或类似器件则使用相同或类似的参考标号来表示。
图1是存储单元器件10的简化截面图。此器件包括底电极或第一电极12,以及顶电极或第二电极14,两者间由环状向外延伸、或可称为管状的存储元件16连接。此存储元件16,在此实施例中,环绕此底电极以及顶电极构件或其延伸部分17和18以及电介质材料20,此电介质材料于两延伸部分17和18之间延伸。此存储元件16,亦被另一电介质材料26环绕。如此,此存储元件16具有依内部的底电极以及顶电极延伸部分17和18支撑,以及电介质材料26。
此存储元件16的中央部分22作为此存储元件的转换区域。假设此存储元件是如GST(会在之后详述)的相变化材料,这种在不同电性状态之间的转换通常会在中央部分22发生,至少因为较电极12,14更好的热绝缘。
在此实施例中,此存储元件16为管状,完全环状向外延伸的结构。请参阅图2。然而,在某些实施例以及某些工艺中,存储元件16并未完全环绕整个或一部分的一层或多层电介质材料20,底电极延伸17和顶电极延伸18。使用完全环状向外延伸的存储材料16可以通过减少在不同电性状态之间的转换区域相较于存储材料的整个圆柱状的体积,来增加此存储材料的效率。当此存储元件是相变化材料时,其可降低此相变化材料重置所需的电流及电能。此外,可以提 供在图形化之后(请参阅图9和图10)优选的工艺均匀度也可以通过使用环状向外延伸的存储材料16而实现。
电介质材料20和26可包括二氧化硅、氮氧化硅、氮化硅、氧化铝、或其他低介电常数(低K,permittivity)的电介质,或为ONO或SONO多层结构。或者,此填充物可包括电绝缘层,其包括选自下列群组的一个以上元素:硅、钛、铝、钽、氮、氧、以及碳。在优选器件中,此填充物具有低导热性,其低于约0.014J/cm*K*sec。在其他优选实施例中,此热绝缘层的导热性低于此相变化材料在非晶态时的导热性,或者低于包含有GST的相变化材料的导热性,亦即0.003J/cm*K*sec。代表性的热绝缘材料包括这些包括有下列元素的组合物材料:硅、碳、氧、氟、以及氢。可作为热绝缘盖帽层的热绝缘材料范例包括:二氧化硅、硅碳氧化物(SiCOH)、聚亚酰胺、聚酰胺、以及氟碳聚合物。其他可作为热绝缘盖帽层的例示材料包括:含氟二氧化硅、硅氧烷(silsesquioxane)、聚亚芳香醚(polyarylene ether)、聚对二甲苯(parylene)、含氟聚合物、含氟非晶碳、类金刚石碳、多孔性二氧化硅、中孔性二氧化硅、多孔性硅氧烷、多孔性聚亚酰胺、以及多孔性聚亚芳香醚。在其他实施例中,此热绝缘结构包括以气体填充的空洞以作为热绝缘。在此电介质材料20和26中的单层或复合层均可提供热绝缘与电绝缘效果。
图1的存储单元器件10的典型尺寸如下。管状存储元件16最好具有小于30纳米的壁厚,通常是大约10纳米。管状存储元件16最好具有3小于50纳米的内面表面直径,通常是大约30纳米。管状存储元件16最好具有小于100纳米的长度,通常是大约50纳米。直径2和4通常分别是大约40和90纳米。高度6和7通常分别是大约50和40纳米。直径4通常是光刻工艺的最小特征尺寸,而直径3通常是以下图8到图10所述光刻图形化工艺所能达到的亚光刻特征 尺寸。其它的尺寸和尺寸范围也可以被使用。
此处所描述的存储单元器件10可以使用标准的光刻以及薄膜沉积技术来制造,并不需要特别的步骤来形成亚光刻特征尺寸,而可以达到十分小尺寸的单元区域,其可在编程时真的改变其阻值。在本发明的实施例中,此存储材料包括相变化材料,例如以下所述的Ge2Sb2Te5或其他材料。单元10中进行相变化的区域非常小,因此相变化所需要的重置电流的幅值也相当小。
存储单元器件10的实例包括以相变化为基础的存储材料,包括以硫属化物(chalcogenide)为基础的材料以及其他材料。硫属化物包括下列四元素的任一者:氧(O)、硫(S)、硒(Se)、以及碲(Te),形成元素周期表上第VI族的部分。硫属化物包括将硫属元素与更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已经被描述于技术文件中,包括下列合金:镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中,可以尝试大范围的合金成分。此成分可以下列特征式表示:TeaGebSb100-(a+b),其中a与b代表在所有构成元素中的原子百分比。一位研究员描述了最有用的合金为,在沉积材料中所包含的平均碲浓度远低于70%,典型地低于60%,并在一般形态合金中的碲含量范围从最低23%至最高58%,且优选介于48%至58%的碲含量。锗的浓度约高于5%,且其在材料中的平均范围从最低8%至最高30%,一般低于50%。优选地,锗的浓度范围介于8%至40%。在此成分中所剩下的 主要成分则为锑。上述百分比为原子百分比,其为所有组成元素加总为100%。(Ovshinky‘112专利,栏10~11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada,“Potential of Ge-Sb-TePhase-change Optical Disks for High-Data-RateRecording”,SPIE v.3109,pp.28-37(1997))更一般地,过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成相变化合金,其包括有可编程的电阻性质。可使用的存储材料的特殊范例,如Ovshinsky ‘112专利中栏11-13所述,其范例在此列入参考。
相变化合金可在第一结构态与第二结构态之间切换,其中第一结构态指此材料大体上为非晶固相,而第二结构态指此材料大体上为结晶固相。这些合金至少为双稳态的。此词汇“非晶”用以指称相对较无次序的结构,其较之单晶更无次序性,而带有可检测的特征如比结晶态更高的电阻值。此词汇“结晶”用以指称相对较有次序的结构,其较的非晶态更有次序,因此包括有可检测的特征例如比非晶态更低的电阻值。典型地,相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特征包括,原子次序、自由电子密度、以及激活能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物,提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质亦可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出,较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量,够大因此足以破坏结晶结构的键合,同时够短因此可以防止原子再次排列成结晶态。在没 有不适当实验的情形下,可决定特别适用于特定相变化合金的适当脉冲量变曲线。
接着简单描述四种电阻存储材料。
1.硫属化物材料
GexSbyTez,其中x∶y∶z=2∶2∶5,
或其他成分为x:0~5;y:0~5;z:0~10。
以氮、硅、钛或其他元素掺杂的GeSbTe也可被使用。
用以形成硫属化物材料的例示方法,利用PVD溅射或磁电管(Magnetron)溅射方式,其反应气体为氩气、氮气、及/或氦气、压力为1mTorr至100mTorr。此沉积步骤一般在室温下进行。长宽比为1~5的准直器(collimater)可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压以及准直器亦是可行的。
可以选择性地在真空中或氮气环境中进行沉积后退火处理,以改良硫属化物材料的结晶态。此退火处理的温度典型地介于100℃至400℃,而退火时间则少于30分钟。
硫属化物材料的厚度随着单元结构的设计而定。一般而言,硫属化物的厚度大于8nm者可以具有相转换特性,使得此材料展现至少双稳态的电阻态。
2.超巨磁阻(CMR)材料
PrxCayMnO3,其中x∶y=0.5∶0.5,
或其他成分为x:0~1;y:0~1。包括有锰氧化物的超巨磁阻材料亦可被使用。
用以形成超巨磁阻材料的例示方法,利用PVD溅射或磁电管溅射方式,其反应气体为氩气、氮气、氧气及/或氦气、压力为1mTorr至100mTorr。此沉积步骤的温度可介于室温至600℃,视后处理条件而定。长宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。另一方面,同时合并使用直流偏压 以及准直器亦是可行的。可施加数十高斯至1特司拉(tesla,10,000高斯)之间的磁场,以改良其磁结晶态。
可以选择性地在真空中或氮气环境中或氧气/氮气混合环境中进行沉积后退火处理,以改良超巨磁阻材料的结晶态。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
超巨磁阻材料的厚度随着存储单元结构的设计而定。厚度介于10nm至200nm的超巨磁阻材料,可被用作核心材料。YBCO(YBACuO3,一种高温超导体材料)缓冲层通常被用以改良超巨磁阻材料的结晶态。此YBCO的沉积在沉积超巨磁阻材料之前进行。YBCO的厚度介于30nm至200nm。
3.双元素化合物
NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等,其中x∶y=0.5∶0.5,
或其他成分为x:0~1;y:0~1。
用以形成此存储材料的例示方法
1.沉积:利用PVD溅射或磁电管溅射方式,其反应气体为氩气、氮气、氧气、及/或氦气、压力为1mTorr至100mTorr,其标靶金属氧化物为如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等。此沉积步骤一般在室温下进行。长宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。若有需要时,同时合并使用直流偏压以及准直器亦是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行沉积后退火处理,以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
2.反应式沉积:利用PVD溅射或磁电管溅射方式,其反应气体为氩气/氧气、氩气/氮气/氧气、纯氧、氦气/氧气、氦气/氮气/氧气等,压力为1mTorr至100mTorr,其标靶 金属氧化物为如Ni、Ti、Al、W、Zn、Zr、Cu等。此沉积步骤一般在室温下进行。长宽比为1~5的准直器可用以改良其填入表现。为了改善其填入表现,亦可使用数十至数百伏特的直流偏压。若有需要时,同时合并使用直流偏压以及准直器亦是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行沉积后退火处理,以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃,而退火时间则少于2小时。
3.氧化:使用高温氧化统(例如高温炉管或快速热处理(RTP))进行氧化。此温度介于200℃至700℃、以纯氧或氮气/氧气混合气体,在压力为数mTorr至一大气压下进行。进行时间可从数分钟至数小时。另一氧化方法为等离子体氧化。无线射频或直流电压源等离子体与纯氧或氩气/氧气混合气体、或氩气/氮气/氧气混合气体,在压力为1mTorr至100mTorr下进行金属表面的氧化,例如Ni、Ti、Al、W、Zn、Zr、Cu等。此氧化时间从数秒钟至数分钟。氧化温度从室温至约300℃,视等离子体氧化的程度而定。
4.聚合物材料
掺杂有铜、碳六十、银等的TCNQ,或PCBM、TCNQ混合聚合物。
形成方法
1.蒸镀:利用热蒸发、电子束蒸发、或分子束外延(MBE)进行蒸发。固态TCNQ以及掺杂物丸在一单独室内进行共蒸发。此固态TCNQ以及掺杂物丸置于钨舟或钽舟或陶瓷舟中。接着施加大电流或电子束,以熔化反应物,使得这些材料混合并沉积于晶圆之上。此处并未使用反应性化学物质或气体。此沉积作用在压力为10-4Torr至10-10Torr下进行。晶圆温度介于室温至200℃。
可以选择性地在真空中或氮气环境中进行沉积后退火 处理,以改良聚合物材料的成分分布。此退火处理的温度典型地介于室温至300℃,而退火时间则少于1小时。
2.旋涂:使用旋转涂布机与经掺杂的TCNQ溶液,转速低于1000rpm。在旋转涂布之后,此晶圆静置(典型地在室温下,或低于200℃的温度)足够时间以利固态的形成。此静置时间可介于数分钟至数天,视温度以及形成条件而定。
如相变化材料等可编程的电阻材料,其有用的特征包括此材料具有可编程的电阻值,且优选以可逆方式进行编程,例如具有可由电流诱发而在可逆地切换的至少两种相态。此至少两种相态包括非晶态以及结晶态。然而,在操作中此可编程电阻材料不一定完全变化成非晶态或结晶态。中间相态或者混合相态可具有可检测的材料特征差异。这两种固态相一般应为双稳态,且具有不同的电性质。此可编程电阻材料可为硫属化物材料。硫属化物材料可包括GST。或者,其可为其他上述相变化材料。一种可使用为本发明的存储单元的材料在此可表示为Ge2Sb2Te5。
图3示出存储阵列,其可利用本文所述的方式形成。在图3中,共同源极线28、字线23、以及字线24安排为大致上平行于Y轴。位线41,42则安排为大致上平行于X轴。因此,在方块45中的Y解码器与字线驱动器,耦合到字线23,24。而在方块46中的X解码器与一组感测放大器,耦合到位线41,42。共同源极线28耦合到存取晶体管50,51,52,53的源极终端。存取晶体管50的栅极耦合到字线23。存取晶体管51的栅极耦合到字线24。存取晶体管52的栅极耦合到字线23。存取晶体管53的栅极耦合到字线24。存取晶体管50的漏极耦合到管状电极存储单元35的底电极构件32,此管状电极存储单元具有顶电极构件34。此顶电极构件34耦合到位线41。相同地,存取晶体管51的漏极耦合到管状电极存储单元36的底电极构件33,此管状电极存储单元具有顶电极构件37。此顶电极构件37耦合到位线41。 存取晶体管52,53耦合到位于位线42上相对应的管状电极存储单元。如图所示,共同源极线28被两列存储单元共用,其中一列在图中呈现Y轴方向排列。在其他实施例中,此存取晶体管可被二极管或其他用以在读取与写入数据阵列中控制电流至选定装置的结构所取代。
图4是根据本发明的一个实施例的集成电路的简化方块图。此集成电路75包括存储阵列60,其以管状电极相变化存储单元所形成于半导体衬底上。列解码器61耦合到多条字线62,且在存储阵列60中沿着各列排列。行解码器63耦合到多条位线64,其在存储阵列60中沿着各行排列并用以读取以及对从存储阵列60中的存储单元的侧壁所获得的数据进行编程。位址从总线65提供至行解码器63以及列解码器61。在方块66中的感测放大器以及数据读入(data-in)线路,经由数据总线67而耦合到行解码器63。数据从集成电路衬底75上的输入/输出端口、或从集成电路75的其他内部或外部数据来源,经由数据输入线路71而提供至方块66的数据输入结构。在所述实施例中,此集成电路也包括其他电路74,如通用处理器或专用应用电路、或以薄膜保险相变化存储单元阵列所支持而可提供芯片上系统功能的整合模块。数据从方块66中的感测放大器经由数据输出线路72,而传送至集成电路75的输入/输出端口,或传送至集成电路75内部或外部的其他数据目的。
在本实施例中使用偏压安排状态机制69的控制器,控制偏压安排供给电压68的应用,例如读取、编程、擦除、擦除确认与编程确认电压等。此控制器可使用公知的专用逻辑电路。在替代实施例中,此控制器包括通用处理器,其可应用于同一集成电路中,此集成电路执行电脑程序而控制此器件的操作。在另一实施例中,此控制器使用了专用逻辑电路以及通用处理器的组合。
图5示出了一对形成于半导体衬底上的存储单元器件10 的剖面图。图5中的结构包括存储单元存取层56,以及存储单元层58。存储单元层58包括上电极层(位线)59,其搭配顶电极延伸18,共同构成了图1中的顶电极14。隔离结构如浅沟槽隔离(STI)结构(位于图中显示)则分隔了一对存储单元存取存储列。存取晶体管包括了衬底内的共同源极线76,以及漏极区域78和80。多晶硅字线82和84分别作用为存取晶体管的栅极。电介质填充层86被形成于多晶硅字线82和84之上。而接触栓塞结构88和90则与个别存取晶体管的漏极接触,在此例示范例中,共同源极线92沿着此阵列的各列与源极区域接触。在其他的实施例中,共同源极线由衬底中的掺杂区域来构成,如在其表面可选择性地具有金属硅化物的n+掺杂区域。栓塞结构88作为终端,其接触此存储单元器件12的底电极的存取晶体管。而栓塞结构90作为终端,其接触此存储单元器件12的底电极的存取晶体管。
在代表性的实施例中,此顶与底电极14和12与存储元件16接触的整个或一部分最好包括电极材料,如氮化钛或是其他与相变化材料的存储元件16相容的导体。在图1的实施例中,顶电极14包含顶电极延伸部分18,以及底电极延伸部分17均是由氮化钛构成,而底电极12的其余部分则包含钨。其他可使用于这种结构中的导体类型,包括如铝及铝合金、氮化钛、氮化钽、氮化铝钛、或氮化铝钽。其他可使用的导体包括选自下列群组的一个以上:钛(Ti)、钨(W)、钼(Mo)、铝(Al)、钽(Ta)、铜(Cu)、铂(Pt)、铱(Ir)、镧(La)、镍(Ni)、钌(Ru)、以及氧(O)。在其他的实施例中,例如以下的图16和图17中所示,顶电极和底电极延伸部分18和17的全部或一部分可以包含存储材料,通常是与存储元件16相同的存储材料。
存储单元器件10及其工艺步骤会在之后的图6-15描述,然后再回到图5。请参阅图6,可以看出存储单元存取 层56具有大致平坦的上表面96。此上表面96的一部分由栓塞88和90的端点表面98所构成。之后,请参阅图7,电极材料层100被沉积于此上表面96之上,然后沉积电介质材料层102,之后再沉积另一电极材料层104。这些层100、102和104分别用来构成底电极延伸17、电介质材料20以及顶电极延伸18。图8则显示了在层104上方沉积与栓塞88和90的电极表面98对准的光刻掩模106之后的结果。栓塞88和90与光刻掩模106两者通常是圆柱截面形态,然而,其他截面形态,标准或非标准多边形以及具有曲面或直线部分的形态亦可适用于其他的实施例中。光刻掩模106的宽度最好是小于其所使用的光刻工艺所能达成的最小光刻尺寸。
图9显示掩模修整步骤之后的结果,其可减少光刻掩模106的宽度或直径至亚光刻尺寸。此图形化后掩模108的宽度或直径远小于用以产生掩模106的最小光刻特征尺寸。图形化通常是利用光刻胶氧气等离子体图形化工艺然而其他的工艺也可以被使用。举例而言,氧化硅硬式掩模工艺也可以被使用。请参阅,例如,美国专利第6869542号,其公开硬式掩模集成蚀刻工艺。
图10显示将未被图形化后光刻掩模108所保护的层100、102和104区域蚀刻后的结果,仅保留,在此实施例中,包含底电极延伸17、电介质材料20以及顶电极延伸18的大致为圆柱堆叠的材料。
图11显示沉积一层存储材料112之后的结果,此存储材料112如同之前所讨论过的,通常是GST,以构成存储元件16。存储材料层112环绕包覆住材料堆叠110的外表面113并向外延伸。图12显示沉积一层电介质材料114于存储材料112上之后的结果。电介质材料26由层114构成。电介质材料26作为热绝缘电介质材料。之后,如图13中所示,作为热绝缘电介质材料26之外的多余电介质材料114利用各向异性反应离子蚀刻除去以保留在侧壁的电介质材料26。
图14显示在图13结构上利用电介质材料116,通常是二氧化硅,介电层填充步骤之后的结果。两层或以上的电介质材料20、26(层114和116)可以是相同或不同的电介质材料。
图15显示在图14结构上利用化学机械研磨步骤之后的结果。之后,电极材料沉积于图15结构之上以构成图5结构中的顶电极层59。
在操作时,电流所流经的路径,包括与栓塞88接触的存取器件的端、经过底电极12、存储元件16和顶电极14。请参阅图1,一般是沿着存储元件16的中央部分22的活性区域120,是由于电流流动所产生的热量而发生的相变化的区域。此活性区域120位于此区域是因为其与作为热导的底电极12和顶电极14分离,同时也因为其与电介质材料20和26热绝缘分离。活性区域120相当微小,因此降低了重置所需要的电流幅值。
图16和图17显示图1中存储单元器件10的某些部分的替代实施例。图16和图1结构不同的部分是其存储元件16是直的圆柱,而不是在圆柱底部的底电极12有向外延伸的部分。每一个图16结构中的底电极延伸17和顶电极延伸18包括存储材料部分122和氮化钛部分124,以提供存储材料相对于电极部分的热绝缘。在图17中,存储材料部分122包含整个底电极延伸17和顶电极延伸18。在图16和图17的实施例中,一个或两者的存储材料部分122可以是与存储元件16相同的存储材料,但也可以是不同。此存储材料部分122的存储材料最好是具有较之使用于存储元件16侧壁的存储材料为低的热阻。
上述的叙述可能使用如之上、之下、顶、底、覆盖等词汇。这些词汇仅用以协助了解本发明,而非用以限制本发明。
虽然本发明已参照优选实施例来加以描述,将为我们所了解的是,本发明并未受限于其详细描述内容。替换方式及 修改样式已于先前描述中所建议,并且其他替换方式及修改样式将为本领域技术人员所想到。特别是,根据本发明的结构与方法,所有具有实质上等同于本发明的构件结合而达成与本发明实质上相同结果的皆不脱离本发明的精神范畴。因此,所有这种替换方式及修改样式将落在本发明在所附权利要求书及其等同物所界定的范畴之中。
任何在前文中提及的专利申请以及印刷文本,均列为本案的参考。
Claims (20)
1.一种具有可通过施加能量而在电性状态之间切换的存储材料的存储单元器件,所述存储单元器件包括:
底电极构件,其具有环状向外延伸的外表面;
在所述底电极构件之上的顶电极构件,所述顶电极构件具有与所述底电极构件的所述外表面大致对准的环状向外延伸的外表面;
电介质材料,其位于所述顶电极构件与所述底电极构件之间;以及
存储元件包含存储材料,所述存储元件至少部分环绕且与所述底电极构件和所述顶电极构件的所述外表面电接触,以在所述存储元件的中央部分产生存储元件转换区域;
其中能量通过所述底电极构件和所述顶电极构件时,会被集中在所述存储元件的所述转换区域中,以导致改变所述存储材料的电性状态。
2.如权利要求1所述的存储单元器件,还包含底电极,所述底电极构件为所述底电极的延伸。
3.如权利要求2所述的存储单元器件,其中所述底电极与所述底电极构件为相同材料。
4.如权利要求2所述的存储单元器件,其中所述底电极与所述底电极构件为不同材料。
5.如权利要求1所述的存储单元器件,其中所述底电极构件包含氮化钛以及Ge2Sb2Te5两者至少之一。
6.如权利要求1所述的存储单元器件,其中所述底电极构件和所述顶电极构件以及所述电介质材料定义材料堆叠,所述材料堆叠具有延伸于所述底电极构件和所述顶电极构件之间且通过所述电介质材料的方向的长度,以及延伸垂直于所述长度的宽度,所述宽度具有亚光刻尺寸宽度。
7.如权利要求1所述的存储单元器件,其中所述存储元件包含管状存储元件。
8.如权利要求7所述的存储单元器件,其中所述管状存储元件具有壁,所述壁具有小于30纳米的厚度。
9.如权利要求7所述的存储单元器件,其中所述管状存储元件的壁具有10纳米的厚度。
10.如权利要求7所述的存储单元器件,其中所述管状存储元件具有内表面,所述内表面具有小于50纳米的直径。
11.如权利要求7所述的存储单元器件,其中所述管状存储元件具有内表面,所述内表面具有约30纳米的直径。
12.如权利要求7所述的存储单元器件,其中所述管状存储元件具有一长度,所述长度小于100纳米。
13.如权利要求7所述的存储单元器件,其中所述管状存储元件具有一长度,所述长度为50纳米。
14.如权利要求1所述的存储单元器件,其中所述存储材料包含Ge2Sb2Te5。
15.一种制造具有可通过施加能量而在电性状态之间切换的存储材料的存储单元器件的方法,所述方法包括:
形成存储单元存取层,包含底电极以及上表面,所述底电极在所述上表面处具有底电极表面;
在所述底电极表面上形成材料堆叠,所述材料堆叠在上电极材料层与下电极材料层之间包含电介质材料层,所述下电极材料层与所述底电极表面接触,所述材料堆叠具有环状向外延伸的外表面;
在所述外表面上形成存储材料层,以至少部分环绕所述材料堆叠;
利用电介质材料来环绕所述存储材料层;以及形成顶电极,与所述材料堆叠的所述上电极材料层接触。
16.如权利要求15所述的方法,其中所述材料堆叠形成步骤包括形成包含顶电极构件的所述上电极材料层以及包含底电极构件的所述下电极材料层。
17.如权利要求16所述的方法,其中所述材料堆叠形成步骤利用所述底电极和所述底电极构件为不同材料来实现。
18.如权利要求16所述的方法,其中所述材料堆叠形成步骤利用所述底电极包含金属而所述底电极构件包含存储材料来实现。
19.如权利要求16所述的方法,其中所述材料堆叠形成步骤利用所述底电极构件包含邻近于所述电介质材料层的存储材料区域以及介于所述存储材料区域与所述底电极之间的金属材料区域来实现。
20.如权利要求15所述的方法,其中所述材料堆叠形成步骤包含:
沉积由上电极材料形成的所述上电极材料层于所述存储单元存取层的上表面之上;
沉积电介质材料层于所述上电极材料层之上;
沉积由下电极材料形成的所述下电极材料层于所述电介质材料层之上;
形成掩模于所述下电极材料层之上,所述掩模与所述底电极表面对准;
将所述掩模图形化以产生亚光刻尺寸图形化掩模;以及
去除未被所述图形化掩模覆盖的材料,以产生亚光刻尺寸材料堆叠。
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