CN101197336A - 包含金属覆盖的晶圆级封装结构与制备方法 - Google Patents

包含金属覆盖的晶圆级封装结构与制备方法 Download PDF

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CN101197336A
CN101197336A CNA2007101969968A CN200710196996A CN101197336A CN 101197336 A CN101197336 A CN 101197336A CN A2007101969968 A CNA2007101969968 A CN A2007101969968A CN 200710196996 A CN200710196996 A CN 200710196996A CN 101197336 A CN101197336 A CN 101197336A
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wafer
dielectric layer
level packaging
packaging structure
ditch
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杨文焜
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Yupei Science & Technology Co Ltd
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Abstract

本发明一晶圆级封装至少包含多数芯片形成于一晶圆上；以一粘性材料将一包含一孔洞的较薄金属覆盖于晶圆上，以改善封装热传导。一保护膜形成于金属覆盖背面并填入孔洞，以便于使用激光标记与得到较佳封装切割质量。

Description

包含金属覆盖的晶圆级封装结构与制备方法
技术领域
本发明涉及半导体封装，特别是于一包含一金属覆盖的晶圆级封装，且一保护膜形成于硅晶圆背面，以改善封装热传导与切割质量，因此可改善封装效能与可靠性测试的生命周期。
背景技术
近年，芯片内电路装置趋势为以高密度制造，且半导体装置趋势为小型化。集成电路设计者致力于缩小装置并增加单元区域芯片整合度。一般来说，半导体装置需要避免湿气与机械性损害。半导体装置结构与封装技术有关。于该技术，半导体芯片或芯片通常个别封装于塑料或陶瓷封装内。封装用以保护芯片与发散装置产生的热。  因此，散热对半导体装置，尤其对于装置效能与动力提供的提升，相当重要。
此外，传统封装也用于芯片全功能测试中。重要的是每一装置要尽量小。近来，发展可提供高量输入与输出的封装受到高度关注。一解决方案是发展包含球栅阵列(ball grid array，BGA)与组装的技术装置。因为大量电性连接与高数字是统频率频率的需求，对于高密度混成技术的需求也出现。
对任何一种封装，大部分封装均于封装前分割为个别芯片。但晶圆级封装为半导体封装的趋势。一般来说，晶圆级封装以整个晶圆，  而非单一芯片或芯片，为封装标的。因此进行切割工艺前，封装与测试必须完成。此为先进技术，因此打线接合工艺，压模(molding)，芯片粘结且组装、导线架与基材可省略；继而降低成本与制造时间。与该技术相比较，传统封装工艺包含芯片切割，芯片粘结，打线接合，压模，修整，标记，电镀与检测。
早期导线架封装技术不适合用于具高密度终端的半导体芯片。因此，新球栅阵列(Ball Grid Array)封装技术已发展用于封装半导体芯片。球栅阵列封装优点为，与导线架封装比较，球状终端具有较短间距，且球栅阵列终端较不易受到损害或变形。此外，较短信号传递路径有提高操作频率以得到较快效率的优点。大部分封装技术于晶圆切割芯片为单个芯片后，对个别芯片进行封装与测试。
另一封装技术，晶圆级封装(WLP)，可于晶圆切个为单个芯片前，封装芯片。晶圆级封装技术优点，包含较短生产期间，低成本，且不需要填胶与压模。
因此本发明揭露一晶圆级封装改善晶圆级封装芯片产率与可靠性。
发明内容
有鉴于现有技术的缺点，本发明提出一包含一保护膜的封装结构用以保护硅芯片免于受到损害，并改善封装效能与可靠性测试的生命周期。
本发明的目的为得到一具有较佳热传导与机械上防护性质(mechanical protection)的封装，本发明提出利用一金属，较佳材料为以合金42(42％镍与58％铁)作为一封装覆盖层，因为该金属热膨胀系数(coefficient of heat expansion，CTE)与硅晶圆相接近。
本发明的另一目的为提出一封装发明，关于制造一较薄封装；本发明目的为揭露一晶圆级封装与其工艺。
本发明另一目的为提供一封装适于晶圆级老化测试(burn-in test)与终测试(final test)。
本发明包含一晶圆级封装，至少包含一多数芯片形成于上的晶圆，其中该晶圆至少包含一形成于内的沟；一介质层形成于该多数芯片上且填充该沟，但该多数芯片的垫片仍暴露；一金属层以一粘性材料附着于晶圆；一保护膜形成于该金属层背面；一导体图案(conductive trace)形成该介质层上且与该垫片连接；一焊锡屏蔽覆盖于导线与介质层，但部分导线仍暴露于外；球下金属层(Under Bump Metallurgy，UBM)形成于该暴露部分并与导线连接。
于另一具体实施例，本发明揭露一晶圆级封装，至少包含多数芯片形成于上的一晶圆，其中该晶圆至少包含一形成于内的沟；一较厚基材包含一于切割在线位置形成的沟，以一粘性材料附着于晶圆(切割在线沟可于附着于晶圆后形成)；一保护膜形成于基材背面并填入该沟；一介质层形成该多数芯片上并填入该晶圆上沟，但该多数芯片的垫片仍暴露；一导线形成该介质层上且与该垫片连接；一焊锡屏蔽覆盖于导体图案与介质层，但仍暴露导线的部分；凸块底层金属、焊锡金属形成于暴露部分上且与导线连接。
附图说明
图1为关于本发明的金属层以一粘性材料粘于一晶圆的示意图；
图2为关于本发明于多数芯片上形成介质层并填入一沟的示意图；
图3为关于本发明于多数芯片上形成介质层并使该多数芯片的垫片暴露的示意图；
图4为关于本发明，其中焊锡屏蔽覆盖导体图案，且锡球形成于导体图案暴露部分的示意图；
图5为关于本发明，其中保护膜形成金属覆盖层背面的示意图；
图6为关于本发明，其中保护膜形成金属覆盖层背面的示意图。
【主要组件符号说明】
基材1
保护膜2
粘性材料层3
晶圆5
切割线7
沟9
介质层11
焊垫13
开口15
重分布导体图案层17
焊锡屏蔽介质层19
焊锡21
切割线22
沟23
具体实施方式
本发明的一些实施例详细描述如下。然而，除了详细描述的实施例外，本发明亦可广泛在其它的实施例中施行，并且本发明的保护范围并不受限于下述的实施例，其是以后述的申请专利范围为准。为提供更清楚的描述及更易理解本发明，图示中各部分并没有依照其相对尺寸绘图，不相关的细节部分也未完全绘出，以求图示的简洁。
本发明揭露一形成一晶圆级封装的方法以及结构。以下为关于本发明的详细叙述。以下叙述与图示仅用于说明关于本发明具体实施例，但本发明不限于下述具体实施例。第一，一经处理晶圆背面(第一面)先以研磨机打磨或研磨。较佳为，处理后，包含多数芯片形成于上的晶圆厚度为研磨至所要厚度，例如约2-6密耳(mil)。之后一粘性材料层3形成于晶圆5或一基材1背面。粘性材料层3形成方法，举例言之，为使用一印刷或涂布方法。粘性材料至少包含环氧树脂，密封胶，水溶性紫外光胶，可重复使用紫外光胶，硅树脂，硅橡胶，弹性聚氨酯(PU)，多孔性聚氨酯，丙烯酸橡胶，蓝胶带(blue tape)或紫外光胶带(UV tape)。于一较佳具体实施例，基材1材料至少包含金属，例如合金42(42％镍与58％铁)。接着，使用适当材料3接合经处理晶圆5与合金42基材1，该材料3包含但不限于图1所绘示的一粘性材料，之后烘烤该结构。合金42基材1可使用现有技术所揭露的一积层(laminating)或接合工艺接合。合金42基材1厚度较佳为约2-4密耳，但合金42基材1实际厚度与工艺参数有关。石英或陶瓷可用以替换合金42基材1。选定用于积层工艺材料的热膨胀系数(CTE)与硅相似，一般为3。合金42特性至少包含热膨胀系数约为4.0～4.7(ppm/℃)，热传导系数约为12(W/m-℃)，电阻约为70(μΩ-cm)与弯折疲劳强度(Yield bend fatigue strength)为约620(MPa)。特殊合金例如合金42有广泛的接受度，因为热膨胀系数与陶瓷相近，且具有高形塑性(formability)。如上述，上述材料热膨胀系数与硅及陶瓷基材相近，其中硅为2.3ppm/℃，陶瓷基材为3.4至7.4ppm/℃。合金42与大部分铜合金(380-550兆帕)相比较，具有高疲劳强度(620兆帕)。基材材料可具导电性以作为信号的导电导体。此外，材料应具有抗蚀性，因为腐蚀会增加材料电阻，并因而造成电性错误(electrical failure)与导致的机械性破坏(mechanical fracture)。本发明所揭露的材料至少包含铁镍合金，铁镍钴合金，铜铁合金，铜铬合金，铜镍硅合金或铜锡合金等等。
之后，一光阻层涂布于经处理晶圆5表面并欲暴露一切割线7。进行一光阻显影工艺后，晶圆(或硅)5使用一包含一特定图案光阻屏蔽进行蚀刻(未绘出)以分割芯片。较佳为，光阻屏蔽开口与切割线7对准，形成于晶圆5表面上，以暴露切割线。于一较佳具体实施例，硅晶圆5使用湿蚀刻以蚀刻出一包含斜度形状的沟9。如该技艺领域所熟知，通过控制蚀刻工艺可轻易得到上述结果。上述两阶段工艺可以芯片切割机械工艺替换。
参照图2，一介质层11，举例言之为苯环丁烯(BCB)，硅氧类高分子(Siloxanes polymer，SINR)，环氧树脂，聚酰亚胺，硅橡胶为基材材质或树脂材质，形成于晶圆5第二面(顶部)并填入切割线7，较佳为利用印刷，真空镀膜工艺。步骤与一般形成胶带(tape)工艺类似。真空镀膜介质层工艺可用于预防于介质层11内形成气泡。该介质层11会自动填入图1中的沟9。之后，于一烘烤步骤，使用紫外光(UV)硬化介质层11。也可选择使用热工艺烘烤该材料。可选择性使用一化学机械研磨(chemicalmechanical poli shing，CMP)工艺研磨晶圆电路上介质层11。
之后，一光阻层涂布于介质层11表面，之后使用光刻工艺，其中铝制焊垫13上光阻层暴露于外。一蚀刻工艺用以移除部分介质层11以产生开口，使该铝制焊垫13暴露，因此多数开口15形成于介质层11且与芯片上垫片13对齐，如图3所显示。其它使铝垫片暴露的方法包含，当介质层11为光敏感材料使用光刻工艺。最后，芯片上垫片13暴露于外。等离子蚀刻用以清洁铝垫13。需注意的是，对准标记可供对准工具用以后续对准。此外，介质层11可抗潮湿。
之后，于介质层11上表面安排一导体图案布线(conductive tracelayout)或又可称为垫片电路重分布(pad circuit redistribution)，如图4所显示。重分布导体图案层17可包含任何传导层例如金属，合金或类似物。于一般工艺，一阻障种子层(barrier seed)形成于图3显示的开口15内与铝垫13上，种子层，举例言之，是以钛/铜或钛/钨/铜合金材料溅镀形成。一光阻涂布于种子层顶部，之后光屏蔽定义出重分布层传导层图案。重分布层的图案形成于种子层上，例如通过使用铜/金或铜/镍/金合金原料材料进行电镀。之后剥除光阻并进行金属湿蚀刻，以形成重分布层金属图案。为使后续工艺中加入的焊锡凸块有适当放置位置与间距，可于障碍层以重分布方式形成重分布层(RDL)。如该技术领域所熟知，部分重分布导体图案17与垫片13接触以形成电性连接。
参照图4，沉积一焊锡屏蔽介质层19(顶部保护层)以覆盖介质层11与重分布层导体图案层17，用以绝缘之用，以保护重分布导体图案层17。焊锡屏蔽介质层19可以印刷或涂布形成，之后使用光刻工艺，以形成一光屏蔽，用以限定出焊锡垫片位置。一光刻工艺用以移除部分焊锡屏蔽介质层19以产生一第二开口，使重分布层图案使焊锡垫片暴露。之后，可以等离子清洁焊锡垫片。上述用以工艺形成重分布导体图案层17可重复进行以形成多层，金属重分布凸块底层金属结构。该方式，是以图案化焊锡屏蔽介质层19限定出凸块底层金属形状，且一可以光线限定形状的环氧树脂可选择性涂布于晶圆，以作为一应力补偿层(stress compensationlayer，SCL)。
焊锡屏蔽介质层19用以暴露重分布导体图案层17特定部分，该重分布导体图案层17暴露区域为预先决定，用以放置锡球作为导电端点。一焊锡粘胶印刷工艺用以使焊锡21印刷于预先决定区域，且焊锡21与重分布导体图案层17相连接(经由凸块底层金属；凸块底层金属部分，图示中未绘出)。之后，焊锡21为以本技术领域公知温度使用红外线回焊技术以形成圆球体状，作为终端接触体，如图5所绘示。半导体芯片5通过垫片电路或重分布导体图案层17与焊锡21耦合。焊锡21可以球栅阵列技术形成。较佳为，焊锡21是以矩阵方式规划形成。一般而言，焊锡21与电路连接，以建立电性连接。
之后，晶圆放置于测试装置以进行晶圆级测试与/或老化测试。参照图5，晶圆级封装(WLP)测试后进行切割工艺，依切割线22切割芯片，以得到芯片级封装(CSP)。于一具有较薄厚度基材1的封装结构，后续工艺包含印刷一保护膜2，其材质可为环氧树脂树脂，化合物，介质层，硅，硅橡胶，硅树脂，弹性聚氨酯，多孔性聚氨酯，丙烯酸橡胶，蓝胶带或紫外光胶带材料，如图5所绘示，于合金42基材1背面形成封装覆盖层，另尚可以使用激光标记以得到较佳切割质量。举例言之，金属层1厚度约为2.0密耳至4.0密耳。保护膜2可以激光或墨水加以标记。于较佳具体实施例，保护膜2材料至少包含树脂，化合物，介质层，硅，蓝胶带，紫外光胶带，硅橡胶，硅树脂，弹性聚氨酯，多孔性聚氨酯或丙烯酸橡胶。最终沿切割线22切割(激光)包含合金42基材1的经处理晶圆，以分离该封装。
此外，参照图6，于另一具体实施例，包含一具较厚基材1的封装结构，光阻为涂布于合金42基材1背面并使切割线22上光阻暴露，因此基材1形成一预先形成图案且一开口形成于该预先决定图案间与切割在线。之后，于较薄厚度的合金42基材1的切割线22上实施一湿蚀刻工艺，以于上形成一沟23便利切割，以得到较佳切割质量。之后，形成保护膜2，材质可为树脂，化合物，介质层，硅，硅橡胶，硅树脂，弹性聚氨酯，多孔性聚氨酯，丙烯酸橡胶，蓝胶带或紫外光胶带材料，以印刷、涂布、粘结(tapeing)或压模形成于合金42基材1背面，并填入沟23以形成封装覆盖层。举例言之，沟23深度约为2.0密耳至10.0密耳。于该具体实施例，较厚基材1于切割线区域，蚀刻为如先前具体实施例的较薄层且沟23以覆盖材料覆盖；此种结构利于使用激光标记以得到较佳封装切割质量。同样的，沿切割线22切割(激光)包含合金42基材1经处理晶圆，以分离该封装。
因此本发明揭露一结构与工艺，其优点包含：保护一硅芯片免于损害，不使用脆弱材料，具较佳热传导性，使用合金42，其热膨胀系数(～4.1)与硅基材(2.6)相近，完整封装芯片，可以较薄方式封装多层重分布层传导层。因此，本发明揭露一包含一金属覆盖的晶圆级尺度封装的结构与工艺，可改善封装效能与可靠性测试时的生命周期。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张的专利权利范围。其专利保护范围当视后附的申请专利范围及其等同领域而定。凡熟悉此领域的技艺者，在不脱离本专利精神或范围内，所作的更动或润饰，均属于本发明所揭示精神下所完成的等效改变或设计，且应包含在下述的申请专利范围内。

Claims (10)

1.一晶圆级封装结构，其特征在于至少包含：
一晶圆，包含多数芯片形成于上，其中该晶圆至少包含一沟形成于内；
一介质层形成于该多数芯片上并填入该沟，但使该多数芯片的垫片暴露；
一金属层以粘性材料粘于该晶圆；
一保护膜形成于该金属层背面；
一导体图案层形成于该介质层且与该垫片连接；
一焊锡屏蔽覆盖于该导体图案层与该介质层，但该导体图案层一部分暴露于外；与
焊锡球形成于该暴露部分且与该导体图案层连接。
2.如权利要求1的晶圆级封装结构，其特征在于，其中该金属基材至少包含合金42(42％镍与58％铁)。
3.如权利要求1的晶圆级封装结构，其特征在于，其中该保护膜材料至少包含环氧树脂树脂，化合物，介质层，硅，硅橡胶，硅树脂，弹性聚氨酯，多孔性聚氨酯，丙烯酸橡胶，蓝胶带或紫外光胶带材料。
4.如权利要求1的晶圆级封装结构，其特征在于，其中该保护膜以激光或墨水标记。
5.如权利要求1的晶圆级封装结构，其特征在于，其中该金属层厚度为2.0密耳至4.0密耳。
6.一晶圆级封装结构，其特征在于至少包含：
一晶圆包含多数芯片形成于上，其中该晶圆至少包含一沟形成于内；
一金属基材包含一沟形成于内，以一粘性材料粘于该晶圆；
一保护膜形成于该基材背面并填入该沟；
一介质层形成于该多数芯片上并填入该沟，但该多数芯片垫片暴露于外；
一导体图案层形成于该介质层上且与该垫片连接；
一焊锡屏蔽覆盖于该导体图案层与该介质层，但该导体图案层一部分暴露；与
焊锡球形成于该暴露部分上且与该导体图案层连接。
7.如权利要求6的晶圆级封装结构，其特征在于，其中该基材至少包含合金42。
8.如权利要求6的晶圆级封装结构，其特征在于，其中该保护膜材料至少包含环氧树脂树脂、化合物、介质层、硅、硅橡胶、硅树脂、弹性聚氨酯、多孔性聚氨酯、丙烯酸橡胶、蓝胶带或紫外光胶带材料。
9.如权利要求6的晶圆级封装结构，其特征在于，其中该保护膜以激光或墨水标记。
10.如权利要求6的晶圆级封装结构，其特征在于，其中该沟深度为2.0密耳至10.0密耳。
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