CN101203947B - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate - Google Patents

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate Download PDF

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CN101203947B
CN101203947B CN2006800221845A CN200680022184A CN101203947B CN 101203947 B CN101203947 B CN 101203947B CN 2006800221845 A CN2006800221845 A CN 2006800221845A CN 200680022184 A CN200680022184 A CN 200680022184A CN 101203947 B CN101203947 B CN 101203947B
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source drain
pmos
gate electrode
gate
method comprises
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CN101203947A (en
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J·卡瓦利洛斯
A·卡佩拉尼
J·布雷斯克
S·达塔
M·多奇
M·梅茨
C·巴恩斯
R·曹
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Google LLC
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

The present invention relates to a complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

Description

The source drain that employing is raised and the CMOS integrated circuit of replacement metal gate
Background technology
The present invention relates generally to the manufacturing of integrated circuit.
In the CMOS technology, in order to improve NMOS and the transistorized performance of PMOS deep-submicron, prior art is used compression in the transistorized raceway groove of PMOS, and pair nmos transistor then uses tension stress.
Use the prior art of strained-channel to be subjected to a lot of restrictions.For example in the PMOS device, may produce the depletion of polysilicon effect.In addition, in the PMOS device stretching strain may take place.Remaining stretching strain reduces the hole mobility of PMOS device.
Therefore, need a kind of manufacturing process of better CMOS (Complementary Metal Oxide Semiconductor), particularly a kind of process that can improve the PMOS device performance.
The accompanying drawing summary
Fig. 1 is the sectional view that is in the transistorized amplification of PMOS of making initial stage;
Fig. 2 is the sectional view that is in the transistorized amplification of PMOS of next fabrication stage;
Fig. 3 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 2 according to an embodiment of the invention;
Fig. 4 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 3 according to an embodiment of the invention;
Fig. 5 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 4 according to an embodiment of the invention;
Fig. 6 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 5 according to an embodiment of the invention;
Fig. 7 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 6 according to an embodiment of the invention;
Fig. 8 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 7 according to an embodiment of the invention;
Fig. 9 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 8 according to an embodiment of the invention;
Figure 10 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 9 according to an embodiment of the invention;
Figure 11 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 10 according to an embodiment of the invention;
Figure 12 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 11 according to an embodiment of the invention;
Figure 13 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 12 according to an embodiment of the invention;
Figure 14 has shown the embodiment of a nmos pass transistor, and this nmos pass transistor is used for using with PMOS transistor as shown in figure 13 according to an embodiment of the invention.
Describe in detail
The complementary transistorized manufacturing of a pair of PMOS is shown in Fig. 1-13 and carry out.In one embodiment, in NMOS side and PMOS side on these two, can deposition of silica gate oxide 105.This gate oxide 105 can by grid material 104 for example polysilicon cover, and then covered, to be used to generate pattern (patterning) by hard mask 130.Grid material 104 and gate dielectric (gate dielectric) 105 then, for example oxide is generated pattern, to produce the structure shown in Figure 1 on the PMOS side 10a.It is thick that gate dielectric may be about 15 dusts, and can carry out the heat growth in one embodiment.
Substrate 100 can comprise the minor structure of the silicon (Silicon-on-insulator) on piece silicon or the dielectric section.As alternative, substrate can comprise other material, these materials can with the silicon combination, the silicon combination of also can getting along well, described these materials for example comprise: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Can form the examples of material of substrate 100 although described some here,, any material that can be used as the semiconductor device substrate all drops in spirit of the present invention and the category.Shallow trench isolation region 20 can be formed the material that transistorized active area isolation comes by silicon dioxide or other.
Grid material 104 can comprise polysilicon, and can be in one embodiment for example about 100 to about 2000 dusts thick and about 500 to about 1600 dusts thick.Hard mask 130 can comprise silicon nitride, and can be in one embodiment for example about 100 to about 500 dusts thick and about 200 to about 350 dusts thick.
Most advanced and sophisticated that mix or a little impure source drain electrode (source drain) 60 can adopt grid structure to form as mask.Can use ion implantation to form source drain 60.
When grid material 104 comprises polysilicon, and hard mask 130 is when comprising silicon nitride, and the structure among Fig. 1 can be made by following method.On substrate 100, form the pseudo-dielectric layer (for example by traditional hot growth technique) that may comprise silicon dioxide, then on dielectric layer, form polysilicon layer (for example by traditional depositing operation).Utilize traditional deposition technique, silicon nitride layer is formed on the polysilicon layer.Silicon nitride, polysilicon and pseudo-dielectric layer (dummydielectric layer) are generated pattern, with the silicon nitride layer that forms patterning, the polysilicon layer of patterning, and the dielectric layer of patterning.When dielectric layer is made of silicon dioxide, can uses conventional engraving method and come polysilicon and pseudo-dielectric layer are carried out patterning.
Nitrogen insolated layer materials 134 can be deposited up (Fig. 2), and is anisotropically carried out etching, forms sidewall spacers (spacer) 108,109, sees Fig. 3.Separator 108,109 can reach the thickness of the 1000 dust orders of magnitude.
Raceway groove (trench) 24 is formed in the substrate 100, sees Fig. 4.Raceway groove 24 can form by the reactive ion etching that utilizes the SF6 chemical agent.Be etched on the side and suppressed, and in one embodiment, on opposite side, roughly isotropically grid structure is not carried out undercutting by dielectric layer 20.Therefore can on the inward flange of raceway groove 24, produce isotropic etching outline, see Fig. 4, and stay a part by impure source drain electrode 60 a little.In this step, NMOS side 10b may oxide mask (not shown) cover.
Then, can growing epitaxial SiGe source drain 40, it has been filled raceway groove 24 and has extended thereon as illustrated in fig. 5.Raceway groove 24 can be filled with the SiGe of the germanium that contains the 10-40 atomic percent.Can mix by the in-situ doped source drain that carries out that utilizes diborane source.40 growths in raceway groove 24 of this epitaxial source drain electrode are because all other material is all by masked or covered.This source drain 40 raises and continued growth is joined up to face (facet).In certain embodiments, can then use source drain to inject.
As shown in Figure 6, after the mask of NMOS side is removed, can cover the structure of Fig. 3 with dielectric layer 112, dielectric layer 112 for example is the etch stopper (NESL) 120 of the lower material of dielectric constant such as oxide and nitride.This layer 112 can mix phosphorus, boron or other material, and it can be formed by the plasma-deposited of high concentration.This dielectric layer 112 can flattened (planarize) be reduced to the upper surface of grid material 104 then, thereby hard mask 130 and NESL120 are removed, as shown in Figure 7.This layer 120 can be a nitride.It assists the NMOS side as etch stopper and shell of tension, but may PMOS side 10a performance be reduced owing to having produced strain.Therefore the NESL120 of PMOS side is removed, can improve performance.
As shown in Figure 8, can remove grid material 104 and on remaining gate oxide 105, form raceway groove 113.Remove grid material 104 and can realize that for example the grid material with respect to nmos pass transistor carries out optionally etching to grid material 104, perhaps shelters nmos pass transistor in technical process shown in Figure 8 by a lot of methods.
Remove grid material 104, produce the raceway groove 113 between sidewall spacers 108,109, thereby produce structure as shown in Figure 8.In one embodiment, wet etch process is optionally to the material 104 that is positioned on the corresponding N MOS transistor material (not shown), can remove material 104 by adopting said method, and can not remove the major part of NMOS material.
In certain embodiments, can selectively remove this layer 104.In one embodiment, layer 104 is exposed in the aqueous solution that has comprised the deionization of by volume calculating about Tetramethylammonium hydroxide of 20% to 30% (TMAH) with adequate time and sufficient temperature (for example being about 60 ℃ to 90 ℃), application of sonic energy is removed all layers 106, can not remove the major part of any nmos pass transistor structure (not shown) simultaneously.
As alternative, can use dry-etching method and optionally remove layer 104.When grid layer 104 is doped P-type (for example having boron), a kind of like this dry-etching method can comprise: the gate electrode layer 104 of sacrifice property is exposed to is derived from sulphur hexafluoride (" SF 6In the plasma of "), hydrogen bromide (" HBr "), hydrogen iodide (" HI "), chlorine, argon and/or helium.Optionally dry-etching method like this can carry out in parallel metal sheet reactor or electron cyclotron resonace etcher.
After removing material 104, remove dielectric layer 105.When dielectric layer 105 was made up of silicon dioxide, dielectric layer 105 can utilize etch process and remove, and this etch process can optionally produce structure shown in Figure 9 for silicon dioxide.Such etch process comprises: layer 105 is exposed in hydrofluoric acid (HF) aqueous solution that contains 1% the deionization of having an appointment, or uses the dry etching process that uses based on the plasma of fluorocarbon.Layer 105 may only expose the limited time, because remove the dielectric layer 112 that the etching process procedure of layer 105 also can be removed a part.Remove layer 105 if should be kept in mind that the solution that utilizes based on 1%HF, the time that this device is exposed in the solution can not surpass about 60 seconds, for example about 30 seconds or still less.If layer 105 is thick less than about 30 dusts when initial deposition, then can removes layer 105, and not remove the dielectric layer 112 of main amount.
Next, the parallel planesization of going forward side by side that new gate dielectric 114 depositions can be got on, to obtain the U-shaped shape, its opening 113 comes into line, as shown in figure 10.Although gate dielectric 114 can comprise any material (wherein gate dielectric is used to include the PMOS transistor of metal gate electrode) that can be used as gate dielectric, but gate dielectric 114 can comprise that dielectric constant is greater than 10 high dielectric constant (k) metal oxide dielectric section material.Some materials that can be used for making the gate dielectric 114 of high k value comprise: hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.Especially the metal oxide of Shi Yonging comprises hafnium oxide, zirconia and aluminium oxide.Although described the example that some can be used for forming the metal oxide of high-K gate utmost point dielectric layer 114 here,, this dielectric layer also can form by other metal oxide.
Utilize traditional deposition process, for example traditional chemical vapour deposition (CVD) (" CVD "), low pressure chemical vapor deposition or physical vapour deposition (PVD) (" PVD ") technology can be formed at high-K gate utmost point dielectric layer 114 on the substrate 100.Preferably utilize traditional atomic layer CVD technology.In this technology, metal oxide precursor (for example metal chloride) and steam are introduced in the CVD reactor with selected flow velocity, reactor moves under chosen temperature and pressure, to be created in (atomically) level and smooth interface on the atomic level between substrate 100 and high-K gate utmost point dielectric layer 114.The CVD reactor should move time enough, forms the layer with desired thickness.In most application scenario, high-K gate utmost point dielectric layer 114 can be for example thick less than about 60 dusts, and thickness is that about 5 dusts are to about 40 dusts in one embodiment.
When atomic layer CVD process quilt is used for forming the gate dielectric 114 of high k value, except in the bottom of raceway groove 113, this layer also will be formed on the vertical side of raceway groove.If high-K gate utmost point dielectric layer 114 comprises oxide, so it may be from the teeth outwards at random place oxide space (oxygen vacancy) and unwelcome impure degree (this depends on its manufacturing process) appear.May after layer 114 deposition, remove its impurity, and, have the metal of near idealization on the chemical equivalent with generation: the metal oxide layer of oxide ratio its oxidation.
In order to remove impurity and to improve its oxygen content, can carry out wet-chemical treatment to high-K gate utmost point dielectric layer 114 from this layer.This wet-chemical treatment can comprise: under enough temperature, the gate dielectric 114 of high k value is exposed to comprises in the solution that hydrogen peroxide forms and reach sufficient a period of time, with the impurity of removal high-K gate utmost point dielectric layer 114, and the oxygen content of raising high-K gate utmost point dielectric layer 114.High-K gate utmost point dielectric layer 114 is exposed to appropriate time and temperature wherein, can be decided by thickness and other character of desirable high-K gate utmost point dielectric layer 114.
When the solution that the gate dielectric 114 of high k value is exposed to based on hydrogen peroxide, can use by volume to calculate to contain about 2% to about 30% aqueous hydrogen peroxide solution.This exposing step can occur between about 15 ℃ to about 40 ℃, minimum about one minute of time.In a particularly preferred embodiment, the gate dielectric 114 of high k value being exposed to temperature is that about 25 ℃ calculating by volume contains 6.7%H approximately 2O 2The aqueous solution in reach about 10 minutes time.In this exposing step, wish frequency of utilization at about 10KHz to about 2000KHz and with about 1Watts/cm 2To about 10Watts/cm 2The acoustic energy that dissipates.In one embodiment, can applying frequency be the acoustic energy of about 1000KHz with the 5Watts/cm2 dissipation.
Gate metal 115 can deposit in the raceway groove 113, and is overlapping with dielectric material 112, sees Figure 11.Can carry out complanation to gate metal,, see Figure 12 to form metal gate electrode 115.
P type metal level 115 can produce by filling raceway groove 113.P type metal level 115 can comprise any P-type conduction material, can bear metal PMOS gate electrode by this P-type conduction material, and it makes raceway groove produce compressive strain for this purpose.The thermal coefficient of expansion of P type metal level may be greater than substrate 100 (for example silicon).The example of the metal that is fit to comprises the silicide of boron carbide, tungsten, molybdenum, rhodium, vanadium, platinum, ruthenium, beryllium, palladium, cobalt, titanium, nickel, copper, tin, aluminium, lead, zinc, alloy and these materials.In one embodiment, use the thermal coefficient of expansion (0.4x10 of thermal coefficient of expansion greater than tungsten -5In./in./℃) material be favourable.Higher relatively depositing temperature, can produce compressive strain with in certain embodiments, and improve animal migration by for example 400 ℃ in conduit.P type metal level 115 preferably has thermal stability property, so that it is suitable for making the metal PMOS gate electrode of semiconductor device.
The material that can be used for forming P type metal level 115 comprises: the metal oxide of ruthenium, palladium, platinum, cobalt, nickel and conduction, for example ruthenium-oxide.The metal of layer 115 can be identical or different with the metal ingredient of metal-oxide dielectric layer 105.P type metal level 115 can utilize well-known PVD or CVD technology, and for example traditional sputter or atomic layer CVD technology form on gate dielectric 105.Except the place of filling raceway groove 113, other P type metal level 115 parts all are removed.Layer 115 can be operated from the other parts of device and remove by wet etching or dry etching process or suitable CMP, and dielectric section 112 stops structure as etching or polishing simultaneously.
P type metal level 115 can compensate the threshold voltage shift that the source drain 40 raised by SiGe is brought.Can regulate or select the work function of this metal level 115, to compensate the threshold voltage shift that must cause owing to using the source drain of raising 40.In general, the source drain of raising 40 causes the rising of valence, and has reduced threshold voltage.Therefore, crack metal (mid-gap metal) is as layer 115 in wishing to use, and its work function can compensate the drift of threshold voltage.
P type metal level 115 can be that about 4.9eV arrives the metal PMOS gate electrode between about 5.2eV as work function, and can have for example about 10 dusts to the thickness between about 2000 dusts, and its thickness is that about 500 dusts are between about 1600 dusts in one embodiment.
Then, structure shown in Figure 13 can be finished by forming silicide contacts portion 46 and nitride etch stop layer 42.Can after forming, contact site 46 provide nitride etch stop layer 42.
In some embodiments of the invention, the source drain 40 that epitaxial sige is raised makes the PMOS raceway groove produce compressive strain, so that improve mobility and reduce outside impedance.This can be achieved like this in certain embodiments, and is promptly in-situ doped by with boron source drain 40 being carried out, and injects (hole injection) for the hole and reduce the superfine energy barrier of Xiao, thereby improves contact resistance.
During polysilicon opening polishing (Fig. 7) and/or being used to form the etching of nitride etch stop layer 42 of contact site, replacement metal gate process can reduce exhausting of polysilicon.And be released in stretching strain in the PMOS device simultaneously.Stretching strain by minimizing reduces hole mobility can help the PMOS device.
Can adjust and replace gate electrode 115, being used for PMOS transistor (when using or not using high dielectric constant (greater than 10) dielectric section or gate dielectric 114), to eliminate exhausting and reducing the grid leakage of polysilicon.Flow through in the journey in replacement metal gate, polishing on PMOS device 10a and/or the NESL120 that has removed stretching strain can improve the mobility of PMOS.
See Figure 14, the manufacturing of nmos pass transistor 10b is carried out according to traditional technology.
For example, nmos pass transistor 10b can have into the joint portion of gradient, and the joint portion of this one-tenth gradient comprises shallow tip/source/drain 39 and dark source drain 22, and it can inject by ion and make.Can introduce or not introduce strain in certain embodiments.In certain embodiments, grid 37 is replacement metal gate, and may adopt traditional polysilicon gate in further embodiments.Grid 37 can be covered by silicide contacts portion 38.NESL120 can be retained in NMOS side 10b.
Although invention has been described for the embodiment only by limited quantity, those skilled in the art can therefrom figure out a large amount of modifications and variations.Appended claim is intended to comprise that all these fall into the modifications and variations in the spirit and scope of the present invention.

Claims (9)

1. method that is used to make CMOS comprises:
On the PMOS of complementary structure side, form pseudo-gate electrode;
Utilize nitride etch stop layer to cover described pseudo-gate electrode;
Utilize nitride etch stop layer to cover gate electrode on the NMOS side of complementary structure;
Get on the denitrify etch stopper from the PMOS structure and keep nitride etch stop layer on the NMOS side;
Remove described pseudo electrode, and replace described pseudo electrode with metal gate electrode; And
On the PMOS side, form the P type source drain of extension.
2. method according to claim 1 is characterized in that, described method comprises the source drain that formation is raised.
3. method according to claim 1 is characterized in that, described method comprises and forms dielectric constant greater than 10 gate dielectric.
4. method according to claim 1 is characterized in that, described method comprises formation U type gate dielectric.
5. method according to claim 1 is characterized in that, described method comprises the described source drain of raising that forms P type doped silicon germanium.
6. method according to claim 1 is characterized in that, described method is included in and forms described nitride etch stop layer on the hard mask.
7. method according to claim 1 is characterized in that, described method comprises the described pseudo-gate electrode that forms polysilicon.
8. method according to claim 1 is characterized in that described method comprises the formation CMOS integrated circuit.
9. method according to claim 1 is characterized in that, described method comprises utilizes pseudo-gate electrode to make mask and etch in the Semiconductor substrate, and by dopant deposition the SiGe epitaxial material of boron form described P type source drain.
CN2006800221845A 2005-06-21 2006-06-21 Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate Active CN101203947B (en)

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