CN101211967B - Bjt及其制造方法 - Google Patents

Bjt及其制造方法 Download PDF

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CN101211967B
CN101211967B CN2007101873147A CN200710187314A CN101211967B CN 101211967 B CN101211967 B CN 101211967B CN 2007101873147 A CN2007101873147 A CN 2007101873147A CN 200710187314 A CN200710187314 A CN 200710187314A CN 101211967 B CN101211967 B CN 101211967B
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金南柱
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DB HiTek Co Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Abstract

本发明涉及一种双极晶体管及其制造方法。根据一个实施方案，将包括金属的集电极电极用于连接n+型埋层的下沉区，使得可以形成狭窄的下沉区。此外，可以降低基极区和集电极电极之间的间距，由此显著降低晶体管的尺寸。此外，集电极电阻降低，因而可以改进晶体管的性能。

Description

BJT及其制造方法
技术领域
实施方案涉及双极晶体管及其制造方法。
背景技术
通常，因为与MOS场效应晶体管相比较，BJT(双极结晶体管)具有高电流驱动性能和高运行速度，所以BJT已经广泛地用于各种产品的特定部分以代替MOS场效应晶体管。
另外，为了实现高速数据处理和高性能，已经使用互补双极晶体管，其中PNP BJT和NPN BJT二者都集成在硅衬底上。
图1A是显示双极晶体管的平面图，图1B是沿图1A中的线II-II显示双极晶体管的剖视图。
如图1A和1B所示，双极晶体管包括形成在硅衬底11表面中的n+型埋层12；形成在包括n+型埋层12的硅衬底11的整个表面上的外延层13；形成在外延层13表面中的n-型阱14；形成在外延层13表面中并且彼此间隔预定间距的基极和发射极区15和16；形成在外延层13的表面中且连接到n+型埋层12的n+型扩散区17；形成在包括外延层13的硅衬底11的整个表面上的层间介电层18；和通过层间介电层18分别连接到基极区15、发射极区16和n+型扩散区17的基极、发射极和集电极的电极19～21。
n+型埋层12用作集电极区。
然而，上述根据现有技术的NPN双极晶体管存在以下问题。
亦即，在形成集电极时，n+型埋层12和硅衬底11的表面连接到称为下沉(sink)的高密度n+型扩散区17。该下沉经过热处理和n-型高密度离子注入，而从硅衬底11的上部连接至外延层13下方的n+型埋层12。在这种情况下，结沿其侧向延伸相当于其下部深度。此外，所述下沉导致与基极结的内压力问题，所以必须保持预定距离。因此，当将下沉用于结时，晶体管的尺寸由于该问题而增加。
发明内容
本申请中公开的是一种提供双极晶体管及其制造方法的实施方案，其中在n+型埋层和硅衬底的表面之间形成沟槽和金属层，使得可以降低RC同时可以降低晶体管的尺寸。
为了实现所述实施方案的目的，提供一种双极晶体管，其包括：在硅衬底表面中的第一导电埋层；在包括所述第一导电埋层的硅衬底上的外延层；在所述外延层表面中的基极和发射极区，其中所述基极和发射极区彼此间隔预定的间距；通过选择性移除所述外延层以部分暴露出所述第一导电埋层表面而形成的开口；在对应于所述开口的所述第一导电埋层表面中的第一导电扩散区；形成在所述硅衬底整个表面上的层间介电层；通过选择性移除所述层间介电层以暴露出所述基极区、发射极区和第一导电扩散区的表面而形成的接触孔；和通过所述接触孔分别电连接到所述基极区、发射极区和第一导电扩散区的基极、发射极和集电极的电极。
为了实现所述实施方案的目的，提供一种制造双极晶体管的方法，所述方法包括以下步骤：在硅衬底表面中形成第一导电埋层；在包括所述第一导电埋层的所述硅衬底上形成外延层；在所述外延层表面中形成基极和发射极区，其中所述基极和发射极区彼此间隔预定的间距；通过选择性移除所述外延层从而部分暴露出所述第一导电埋层的表面而形成开口；在对应于所述开口的所述第一导电埋层表面中形成第一导电扩散区；在所述硅衬底整个表面上形成层间介电层；通过选择性移除所述层间介电层从而暴露出所述基极区、发射极区和第一导电扩散区的表面而形成接触孔。
附图说明
图1A是显示根据一个实施方案的双极晶体管的平面图；
图1B是显示沿图1A中线II-II的根据一个实施方案的双极晶体管的剖视图；
图2是显示根据一个实施方案的双极晶体管的剖视图；和
图3A～3G是顺序显示根据一个实施方案制造双极晶体管的步骤的剖视图。
具体实施方式
在本说明书中对“一个实施方案”、“实施方案”、“示例实施方案”等的任何引用都表示与所述实施方案相关的具体特征、结构、或性能包括在本发明的至少一个实施方案中。出现在说明书不同地方的这些术语不必都涉及相同的实施方案。另外，在描述与任何实施方案相关的具体特征、结构或性能时，这种特征、结构或性能与其它实施方案相关联是在本领域技术人员的理解范围之内的。
尽管已经参考其多个示例性实施方案描述了实施方案，但是应该理解本领域技术人员可以知道很多的其它改变和实施方案，这些也在本公开原理的精神和范围内。更具体地，在公开内容、附图和所附权利要求的范围内，在本发明的组合排列的构件和/或结构中可能存在许多变化和改变。除构件和/或结构的变化和改变之外，对本领域技术人员而言，替代用途是显而易见的。
以下，将参考附图描述根据一个实施方案的双极晶体管及其制造方法。
图2是显示根据一个实施方案的双极晶体管的剖视图。
如图2所示，所述双极晶体管包括形成在硅衬底101表面中的n+型埋层102；形成在包括n+型埋层102的硅衬底101上的外延层103；形成在外延层103表面中的n-型阱104；形成在外延层103表面并且彼此间隔预定间距的基极和发射极区105和106；通过选择性移除外延层103以部分暴露出n+型埋层102的表面而形成的开口110；在对应于开口110的n+型埋层102中形成的n+型扩散区111；形成在硅衬底101整个表面上的层间介电层112；通过选择性移除层间介电层112以暴露出基极区105、发射极区106和n+型扩散区111的表面而形成的接触孔114，和通过接触孔114分别电连接到基极区105、发射极区106和n+型扩散区111的基极、发射极和集电极的电极115～117。
图3A～3G是顺序显示根据一个实施方案制造双极晶体管的步骤的剖视图。
如图3A所示，将n+型杂质离子选择性注入硅衬底101以在硅衬底101的表面中形成具有预定宽度的n+型埋层102。
然后，外延生长硅衬底101以在其上形成外延层103。
接着，将低密度n-型杂质离子选择性注入外延层103，以在外延层103的表面中形成具有预定宽度的n-型阱104。
其后，将n和p型杂质离子选择性注入外延层103，以形成彼此间隔预定间距的n+型基极和p+型发射极区105和106。
如图3B所示，在硅衬底101的整个表面上顺序形成氧化物和氮化物层107和108，并在氮化物层108上涂覆第一光刻胶109。
然后，通过曝光和显影过程选择性地图案化第一光刻胶109，以限定集电极下沉区。
接着，使用图案化的光刻胶109作为掩模选择性移除氮化物和氧化物层108和107，然后选择性移除外延层103以部分暴露出n+型埋层102的表面，由此形成开口110。
如图3C所示，利用包括第一光刻胶109的氮化物和氧化物层108和107作为掩模，将高密度n型杂质离子注入硅衬底101的整个表面，由此在开口110内的n+型埋层102的表面中形成具有预定深度的n+型扩散区111。
如图3D所示，移除第一光刻胶109以及氮化物和氧化物层108和107，并清洁硅衬底101，以移除在工艺期间产生的颗粒。
然后，在硅衬底101的整个表面上形成层间介电层112。
如图3E所示，在层间介电层112上涂覆第二光刻胶113，并通过曝光和显影过程选择性地图案化以限定各个电极区域。
如图3F所示，使用图案化的光刻胶113作为掩模，选择性移除层间介电层112，以暴露出基极区105、发射极区106和n+型扩散区111的表面，由此形成接触孔114。
暴露n+型扩散区111表面的接触孔114具有比对应于开口110的宽度更宽的宽度。
如图3G所示，移除第二光刻胶113，并在硅衬底101的整个表面上沉积金属层。然后，通过光和蚀刻过程选择性移除金属层，以形成通过接触孔114电连接到基极区105、发射极区106和n+型扩散区111的基极、发射极和集电极的电极115～117。
根据上述实施方案的双极晶体管及其制造方法，可以实现以下效果。
第一，使用金属代替结，形成用于连接n+型埋层的下沉区，使得可以形成狭窄的下沉区。
第二，可以降低与基极的间距，因而可以显著降低晶体管的尺寸。
最后，降低集电极电阻，因而可以改进晶体管的性能。
尽管已经参考其多个示例性实施方案描述了实施方案，但是应该理解本领域技术人员可以知道很多的其它改变和实施方案，这些也在本公开原理的精神和范围内。

Claims (6)

1.一种双极晶体管，包括：
在硅衬底表面中的第一导电埋层；
在包括所述第一导电埋层的硅衬底上的外延层；
在所述外延层表面中的基极和发射极区，其中所述基极和发射极区彼此间隔预定的间距；
通过选择性移除所述外延层以部分暴露出所述第一导电埋层表面而形成的开口；
在对应于所述开口的所述第一导电埋层表面中的第一导电扩散区；
形成在所述硅衬底整个表面上的层间介电层；
通过选择性移除所述层间介电层以暴露出所述基极区、所述发射极区和所述第一导电扩散区的表面而形成的接触孔；和
通过所述接触孔分别电连接到所述基极区、所述发射极区和所述第一导电扩散区的基极、发射极和集电极的金属电极。
2.权利要求1的双极晶体管，其中暴露出所述第一导电扩散区的表面的所述接触孔的宽度比所述开口的宽度更宽。
3.权利要求1的双极晶体管，其中所述接触孔中的集电极电极宽度比所述开口中的集电极电极宽度更宽。
4.一种制造双极晶体管的方法，所述方法包括以下步骤：
在硅衬底表面中形成第一导电埋层；
在包括所述第一导电埋层的所述硅衬底上形成外延层；
在所述外延层表面中形成基极和发射极区，其中所述基极和发射极区彼此间隔预定的间距；
通过选择性移除所述外延层从而部分暴露出所述第一导电埋层的表面而形成开口；
在对应于所述开口的所述第一导电埋层表面中形成第一导电扩散区；
在所述硅衬底整个表面上形成层间介电层；
通过选择性移除所述层间介电层从而暴露出所述基极区、所述发射极区和所述第一导电扩散区的表面形成接触孔；和
形成通过所述接触孔分别电连接到所述基极区、所述发射极区和所述第一导电扩散区的基极、发射极和集电极的金属电极。
5.权利要求4的方法，其中在所述开口中的集电极电极宽度比在所述接触孔中的集电极电极宽度更窄。
6.权利要求4的方法，其中暴露出所述第一导电扩散区的表面的所述接触孔的宽度比所述开口的宽度更宽。
CN2007101873147A 2006-12-27 2007-11-19 Bjt及其制造方法 Expired - Fee Related CN101211967B (zh)

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KR1020060134635A KR100832716B1 (ko) 2006-12-27 2006-12-27 바이폴라 트랜지스터 및 그 제조방법

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US9099489B2 (en) * 2012-07-10 2015-08-04 Freescale Semiconductor Inc. Bipolar transistor with high breakdown voltage
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