CN101303988B - Ic芯片安装方法 - Google Patents

Ic芯片安装方法 Download PDF

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Publication number
CN101303988B
CN101303988B CN2008100992976A CN200810099297A CN101303988B CN 101303988 B CN101303988 B CN 101303988B CN 2008100992976 A CN2008100992976 A CN 2008100992976A CN 200810099297 A CN200810099297 A CN 200810099297A CN 101303988 B CN101303988 B CN 101303988B
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China
Prior art keywords
chip
substrate
wafer
belt
base
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Expired - Fee Related
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CN2008100992976A
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CN101303988A (zh
Inventor
石川直树
马场俊二
吉良秀彦
小林弘
菊池俊一
常野达朗
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Fujitsu Ltd
Fujitsu Frontech Ltd
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Fujitsu Ltd
Fujitsu Frontech Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

一种将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：制备晶片，即将带子安装在该晶片的一面，其相反面为待连至基底的安装表面，然后切割该晶片但保留该带子，将该晶片分割成多个IC芯片；并且通过折叠来收缩待安装IC芯片的基底，使IC芯片在该基底上的安装位置之间的间隔可以与IC芯片在该基底上的安装位置之间的规定间隔一致，其中该规定间隔是指将位于该晶片上的IC芯片安装到该基底上并展开该基底后所规定的间隔；使安装有带子的晶片面对收缩的基底放置，其方向为待连至基底的安装表面面对该基底；将该晶片上的IC芯片安装到收缩的基底上；以及展开该基底。本发明提高了IC芯片安装的生产率。

Description

IC芯片安装方法
本申请是申请日为2006年1月9日，申请号为200610003614.0，发明名称为“IC芯片安装方法”一案的分案申请。
技术领域
本发明涉及一种IC芯片安装方法，用于将两个或更多个IC芯片安装到基底上。
背景技术
近年来，已提出各种类型的RFID标签，它们通过电波以非接触方式与以读卡器或写卡器为典型的外部设备交换信息。作为RFID标签的一个类型，已提出这样一种结构，其中，用于进行无线电通信的天线图案和IC芯片安装在由塑料或纸制成的基片上。对于这种类型的RFID标签，已经创建了一些使用方式，例如物品识别，通过将标签附着到物品等上面并与外部设备交换关于物品的信息来识别物品。
图1为示出RFID标签实例的正视图(A)和侧视截面图(B)。
图1所示的RFID标签1的构成为：天线12，其安装到由片状PET膜等形成的基底13上；IC芯片11，其通过凸块16连接至天线12；以及盖片14，其使用粘合剂15接合至基底13，并覆盖天线12和IC芯片11。
构成RFID标签1的IC芯片11能够通过天线12与外部设备进行无线电通信，用于交换信息。
对于这种RFID标签，已经创建了包括上述使用方式的大范围的使用方式。然而，在各种使用方式中使用RFID标签在其制造成本方面具有严重的问题，因而为减少制造成本已进行了多种努力。
图2为示出用于RFID标签的传统方法之一的一般IC芯片安装方法的示意图。
如图2的(A)部分所示，由各种类型的IC芯片构成的晶片10的背侧的整个表面(具有待连至基片的安装表面的晶片的另一面)安装有带子(tape)30，并通过切割分割成多个IC芯片11，但保留带子30。
如图2的(B)部分所示，使用拾取夹具32将晶片10上的大量IC芯片11之一从带子30拉起并将其从带子30上取下和夹持。
如图2的(C)部分所示，将吸有IC芯片11的拾取夹具32上下颠倒。
如图2的(D)部分所示，将IC芯片11转移至接合头33。
进一步，如图2的(E)部分所示，接合头33将IC芯片11携带至基底13上，将该芯片置于与形成在基底13上的天线12连接的适当位置上，并且如图2的(F)部分所示，通过加压和加热将IC芯片11焊接到基底13上。然后，如图2的(G)部分所示，当从IC芯片11移去接合头33时，IC芯片11的安装即告完成。
对于晶片10上的大量的IC芯片11，依次重复图2(B)至图2(G)所示的各步骤。
然而，这种安装方法要求对每个IC芯片都依次执行一个复杂的工艺，即：晶片10上的IC芯片11被一个接一个地拾取、翻转、传递至另一个夹具(接合头)，然后安装在接合头上，因此削弱了生产率并增加了制造成本。
日本专利待审公开No.2003-242472已提出一种减少制造成本的方法，即：在行进的网材料(traveling web material)(基底)上间隔地形成用于嵌入IC芯片的多个凹部，将IC芯片安装在这些凹部中，并且通过喷墨法印制天线图案，以与安装在凹部中的IC芯片连接。
然而，日本专利待审公开No.2003-242472提出的方法在将IC芯片安装在网材料(基底)的凹部内的过程中包括：在储液池中充满液体以使IC芯片漂浮在液体中，使该网材料(基底)行进通过储液池内部，以将IC芯片安装在网材料(基底)的凹部内。这种传统方法的弊端是将IC芯片安装在凹部中的工艺可靠性较低，这是因为IC芯片并不总是能以适当的方向精确地安装在凹部中，并且不具有IC芯片的凹部可能会穿过储液池内部。即使IC芯片已适当地安装在凹部中，还需将天线图案相对于安装在凹部中的IC芯片高精度地定位。而且，如果在将IC芯片安装在凹部中的位置处发生了可忽略掉的错误，则还需对应于该错误改变天线图案的印制位置，而这可能导致生产率降低。
发明内容
鉴于上述现状而提出本发明，即提供一种能够获得高生产率的IC芯片安装方法。
本发明的IC芯片安装方法的第一方案是一种用于将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：
制备晶片，即将带子(tape)安装在该晶片的一面，其相反面为待连至基底的安装表面，然后切割该晶片但保留该带子，将该晶片分割成多个IC芯片；
将该晶片面对该基底放置，其方向为该待连至基底的安装表面面对该基底；
当该基底沿着该晶片在规定的一维方向上进给并且当该晶片沿着该基底二维地移动时，将该晶片上的IC芯片依次抵压在该基底上而暂时固定IC芯片；以及
以批处理方式通过加热和加压将暂时固定在该基底上的IC芯片固定在该基底上。
本发明的IC芯片安装方法的第二方案是一种用于将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：
制备晶片，即将带子安装在该晶片的一面，其相反面为待连至基底的安装表面，然后切割该晶片但保留该带子，将该晶片分割成多个IC芯片；
将该晶片面对该基底放置，其方向为该待连至基底的安装表面面对该基底；以及
当该基底沿着该晶片在规定的一维方向上进给并且当该晶片沿着该基底二维地移动时，使用用于执行加热和加压的加热加压头将该晶片上的IC芯片抵压在该基底上进行加热和加压，来将IC芯片依次固定在该基底上。本发明的IC芯片安装方法的第三方案是一种用于将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：在通过切割将晶片分割成多个IC芯片之前，将带子安装在该晶片的一面，其相反面为待连至基底的安装表面，然后通过折叠收缩该带子，从而在切割后通过展开该带子，使IC芯片之间的间隔可以与IC芯片在该基底上的安装位置之间的间隔相匹配；通过切割但保留该带子，将安装有收缩的带子的晶片分割成多个IC芯片；以及在带子展开的状态下，使安装有该带子的IC芯片面对该基底放置，其方向为IC芯片到该基底的安装表面面对该基底；以及将IC芯片安装到该基底上。本发明的IC芯片安装方法的第四方案是一种用于将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：制备晶片，即将带子安装在该晶片的一面，其相反面为待连至基底的安装表面，然后切割该晶片但保留该带子，将该晶片分割成多个IC芯片；并且通过折叠来收缩待安装IC芯片的基底，使IC芯片在该基底上的安装位置之间的间隔可以与IC芯片在该基底上的安装位置之间的规定间隔一致，其中该规定间隔是指将位于该晶片上的IC芯片安装到该基底上并展开该基底后所规定的间隔；使安装有带子的晶片面对收缩的基底放置，其方向为待连至基底的安装表面面对该基底；将该晶片上的IC芯片安装到收缩的基底上；以及展开该基底。
在本发明的第一至第四种IC芯片安装方法的任一种中，优选的是，以规定间隔设置的用于通信的两个或更多个天线形成在该基底上；以及每个IC芯片安装有电路，该电路通过位于该基底上的每个天线进行无线电通信。换句话说，优选的是，本发明应用于RFID标签。
在本发明的第一至第四种IC芯片安装方法的任一种中，优选的是，使用相机拍摄IC芯片在该基底上的安装位置和/或IC芯片本身，将IC芯片安装到该基底上，同时通过图像识别进行位置调整。
本发明的第一种和第二种IC芯片安装方法分别使IC芯片以高速度依次安装到基底上，由此提高了IC芯片安装的生产率。
而且，由于是在IC芯片的间隔与IC芯片在基底上的安装位置的间隔匹配的情况下将IC芯片安装到基底上的，所以第三种和第四种IC芯片安装方法分别使两个或更多个IC芯片一次性或以高速度依次安装到基底上，由此提高了IC芯片安装的生产率。
附图说明
图1为示出RFID标签实例的正视图(A)和侧视截面图(B)；
图2为示出用于RFID标签的传统方法之一的一般IC芯片安装方法的示意图；
图3为示出晶片和基底之间的关系的示意图；
图4为示出根据本发明第一实施例的IC芯片安装方法的工艺示意图；
图5为示出IC芯片安装在基底上的场景的示意图；
图6为示出根据本发明第二实施例的IC芯片安装方法的工艺示意图；
图7为示出加热头的结构的示意图；
图8为示出本发明第三实施例的工艺示意图；
图9为示出本发明第四实施例的工艺示意图；以及
图10为示出IC芯片安装在基底上的场景的示意图。
具体实施方式
下面将描述本发明的实施例。
图3为示出晶片和基底之间的关系的示意图。
在下面描述的第一实施例中，制备晶片10和基底13，并将晶片10和基底13设置在使它们相互面对的位置上，如图3所示。通过将带子安装在晶片10的一个面(图3中晶片10的顶面)上并且通过切割而保留带子30，将晶片10分割成多个IC芯片11，其中该面是具有待连至基底13的安装表面(图3中晶片10的底面)的晶片的反面。如图3所示，晶片10设置在面对基底13的位置，其方向为待连至基底13的安装表面面对基底13。晶片10沿着基底13在X和Y方向上二维地移动。
在基底13面对晶片10一侧的面(图3中基底13的顶面)上以所设置的规定间隔形成有两个或更多个天线12，并且基底13在天线12排列(align)的方向(图3中箭头X所示)上进给固定量。
在本发明的第一实施例中，晶片10和基底13如图3所示放置，而晶片10上的IC芯片11以如下方式安装在基底13上。
图4为示出根据本发明第一实施例的IC芯片安装方法的工艺示意图。
参考图3所述，首先，制备安装有带子30并被分割成多个IC芯片11的晶片10，将其面对基底13放置，并且方向为到基底13的安装表面面对基底13。另一方面，天线12设置在基底13上(图4的(A)部分)。
在基底13沿箭头X的方向(参照图3)进给固定量的条件下，通过在X和Y方向(参照图3)上二维地移动晶片10，使用抵压夹具51从带子30的顶部抵压排列在晶片10上的大量IC芯片11之一(IC芯片11a)，从而使IC芯片11a暂时固定在位于基底13上的一个天线12a上(图4的(B)部分)。
图5为示出IC芯片11位于基底13上的场景的示意图。
在使用抵压夹具51抵压每个IC芯片11来将IC芯片11暂时固定在基底13上时，有必要将待暂时固定的IC芯片11定位在基底13的规定位置上。使用两个相机71a、71b拍摄待安装的IC芯片11本身和该IC芯片11在基底13上的安装位置，由各图像识别部分72a、72b识别它们的图像，由各偏移量计算部分73a、73b计算各偏移量。XY校正部分74通过总计它们的偏移量，而将待安装的IC芯片准确地定位在基底13上的规定位置处。这使IC芯片11相对于基底13上的天线12准确地安装在规定位置处。
现返回图4继续描述此实施例。
接下来，在以固定量进给基底13期间通过X-Y移动而定位晶片10(图4的(C)部分)，然后通过抵压夹具51抵压下一个IC芯片11b(图4的(D)部分)，而将其暂时固定在位于基底13上的下一个天线12b上(图4的(E)部分)。
接下来，以相同的方式，使用抵压夹具51抵靠位于基底13上的天线12c而抵压IC芯片11c(图4的(F)部分)，而将其暂时固定在天线12c上。
在以此方式分别将IC芯片11暂时固定在位于基底13上的天线12上之后，将批处理(batch)加热头52置于IC芯片11上，从而IC芯片11以批处理方式被加热、加压并焊接安装在位于基底13上的各天线12上(图4的(G)部分)。
该第一实施例使两个或更多个IC芯片11以高速依次暂时固定在基底13上，且暂时固定在基底13上的IC芯片11通过批处理加热头52以批处理方式焊接固定，由此加速了IC芯片11在基底13上的安装，以实现高的生产率。
图6为示出根据本发明第二实施例的IC芯片安装方法的工艺示意图。
该第二实施例使用参照图3所述的设置和移动的形式，因而保留其原貌。换句话说，如图3所示，首先，制备安装有带子30并被分割成多个IC芯片11的晶片10，将其面对基底13放置，并且方向为待连至基底13的安装表面面对基底13。另一方面，天线12设置在基底13上(图6的(A)部分)。
在沿箭头X的方向(参照图3)以固定量进给基底13的条件下，通过在X和Y方向(参照图3)上二维地移动晶片10，使用用于加热和加压的加热头61从带子30的顶部抵压排列在晶片10上的大量IC芯片11之一(IC芯片11a)，从而使IC芯片11a被焊接在位于基底13上的一个天线12a上(图6的(B)部分)。
图7为示出加热头61的结构的示意图。
加热头61的中央部分包含安装头611。安装头611内具有加热器(未示出)，并且构成为可由头保持器612保持而进行垂直移动。围绕安装头611设置吸附部613。如图7的(B)部分所示，当使用安装头611从带子30顶部向下抵压IC芯片11时，吸附部613吸到下压的IC芯片11的周边上，以防止安装头611向下抵压待下压的IC芯片11的作用施加到与带子30相邻的IC芯片部分。这是因为施加到相邻IC芯片部分的作用会导致拉长相邻IC芯片部分的带子，而在安装IC芯片时出现安装位置误差。
现返回图6继续描述此实施例。
接下来，在以固定量进给基底13期间，通过X-Y的移动定位晶片10侧面(图6的(C)部分)，然后通过加热头61抵压下一个IC芯片11b(图6的(D)部分)，而将其焊接到位于基底13上的下一个天线12b上(图6的(E)部分)。
接下来，以相同的方式，为了通过加热头61加热和加压，抵靠位于基底13上的天线12c而抵压IC芯片11c(图6的(F)部分)，而将其焊接到天线12c上。
以此方式，第二实施例使得在基底13被递送固定量且晶片10做X-Y移动时，能够依次和高速地将两个或更多个IC芯片11分别焊接到位于基底13上的两个或更多个天线12上，由此加速了IC芯片11的安装，以实现高的生产率。
图8为示出本发明第三实施例的工艺示意图。
在晶片10被分割成两个或更多个IC芯片11之前，晶片10的一个面(图8的(A)部分中的顶面)安装有带子30(图8的(A)部分)，其中该面为具有待连至基底13(参照图8的(C)部分)的安装表面(图8的(A)部分中的底面)的晶片10的反面。带子30通过折叠处于收缩状态，使得在切割后，通过展开带子，IC芯片11之间的间隔可以与IC芯片在基底13上的安装位置之间的间隔相匹配。
对IC芯片安装收缩晶片10的带子30，在进行定位之后安装完成，以使作为带子30的折叠部分的隆起部(ridge)的每个顶部可以匹配每个IC芯片11。
随后，晶片10被切割而分割成多个IC芯片11(图8的(B)部分)。
使安装有带子30的IC芯片11面对基底13，其方向为IC芯片11到基底13的安装表面(图8的(C)部分的底面)在带子30展开的状态下面对基底13(图8的(C)部分)。
在此状态下，IC芯片11之间的间隔与基底13上的天线12之间的间隔互相匹配，因而不必单独定位。另外，即使在如图5所示的单独定位的情况下，也可以稍微调整定位，并且可以将IC芯片11以批处理方式或以高速度依次固定到基底13上的各天线12上。
图9为示出本发明第四实施例的工艺示意图。
基底13通过折叠被收缩，如图9的(B)部分所示，该基底13上形成有等间隔设置的天线12，如图9的(A)部分所示。通过折叠工艺来展开基底13，使位于基底13上方的晶片10上的IC芯片11安装到基底13上，从而基底13被以如下方式收缩，即：位于基底13上的IC芯片之间的间隔可以与基底13上的IC芯片11的安装位置之间的规定间隔、即天线12之间的间隔相等。
除了基底之外，还制备晶片10，以使晶片10的一个面安装带子30，其中该面是具有待连至基底13的安装表面的晶片10的另一侧；并且通过切割将该晶片分割成多个IC芯片11，但保留带子30。使晶片10面对以上述方式收缩的基底13，其方向为待连至基底13的安装表面面对基底13(图9的(C)部分)，再将IC芯片11安装在位于基底13上的各天线12上(图9的(D)部分)。然后，当将基底13展开时，IC芯片11一个接一个地安装在以规定间隔形成在基底13上的每个天线12上(图9的(E)部分)。
图10为示出IC芯片11安装在基底13上的场景的示意图。
在将IC芯片11安装到基底13上时，使用相机81拍摄每个IC芯片的安装部分，由图像识别部分82识别其图像，由偏移计算部分83计算IC芯片11从基底13上的天线12的偏移，然后通过XY校正部分84调整对IC芯片11的定位。这使IC芯片11相对于基底13上的天线12准确地安装在规定位置处。
第四实施例将两个或更多个IC芯片11以批处理方式或以高速度依次安装到基底13上，由此加速了IC芯片的安装，以减少安装成本。

Claims (3)

1.一种将两个或更多个IC芯片安装到基底上的IC芯片安装方法，包括步骤：
制备晶片，即将带子安装在该晶片的一面，其相反面为待连至基底的安装表面，然后切割该晶片但保留该带子，将该晶片分割成多个IC芯片；并且通过折叠来收缩待安装IC芯片的基底，使IC芯片在该基底上的安装位置之间的间隔与IC芯片在该基底上的安装位置之间的规定间隔一致，其中该规定间隔是指将位于该晶片上的IC芯片安装到该基底上并展开该基底后所规定的间隔；
使安装有带子的晶片面对收缩的基底放置，其方向为待连至基底的安装表面面对该基底；
将该晶片上的IC芯片安装到收缩的基底上；以及
展开该基底。
2.如权利要求1所述的IC芯片安装方法，其中，以规定间隔设置的用于通信的两个或更多个天线形成在该基底上；以及
每个IC芯片安装有电路，该电路通过位于该基底上的每个天线进行无线电通信。
3.如权利要求1所述的IC芯片安装方法，其中，在将面对基底的IC芯片安装到该基底上时，使用相机拍摄IC芯片在该基底上的安装位置和/或IC芯片本身，将IC芯片安装到该基底上，同时通过图像识别进行位置调整。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011222639A (ja) * 2010-04-07 2011-11-04 Disco Abrasive Syst Ltd ボンディング方法
JP2012156473A (ja) * 2011-01-28 2012-08-16 Adwelds:Kk 部品移載装置および部品移載方法
KR101801264B1 (ko) 2011-06-13 2017-11-27 삼성전자주식회사 반도체 제조 장치 및 이를 이용한 반도체 패키지 방법
KR101288165B1 (ko) * 2011-08-29 2013-07-18 삼성전기주식회사 바이오칩 스탬핑 장치 및 스탬핑 방법
JP2014033100A (ja) * 2012-08-03 2014-02-20 Panasonic Corp 実装方法
KR101488609B1 (ko) * 2013-07-22 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법
JP6367084B2 (ja) 2014-10-30 2018-08-01 株式会社東芝 半導体チップの接合方法及び半導体チップの接合装置
JP6582975B2 (ja) * 2015-12-28 2019-10-02 富士通株式会社 半導体実装装置、半導体実装装置のヘッド及び積層チップの製造方法
US10672638B2 (en) * 2017-01-27 2020-06-02 International Business Machines Corporation Picking up irregular semiconductor chips
US10694651B2 (en) * 2017-06-20 2020-06-23 Saul Tech Technology Co., Ltd. Chip-placing method performing an image alignment for chip placement and chip-placing apparatus thereof
KR102077049B1 (ko) * 2017-12-21 2020-02-13 한국기계연구원 마이크로 소자 전사방법 및 마이크로 소자 전사장치
KR102031603B1 (ko) * 2018-03-12 2019-11-08 ㈜큐엠씨 발광다이오드 칩을 전사하는 전사 장치 및 방법
KR102139571B1 (ko) * 2018-03-12 2020-07-29 ㈜큐엠씨 발광다이오드 칩을 전사하는 전사 장치 및 방법
WO2019177337A1 (ko) 2018-03-12 2019-09-19 (주)큐엠씨 발광다이오드 칩을 전사하는 전사 장치 및 방법
JP6906586B2 (ja) * 2018-06-21 2021-07-21 株式会社東芝 半導体チップの接合方法及び半導体チップの接合装置
US11069555B2 (en) 2018-09-03 2021-07-20 Assembleon B.V. Die attach systems, and methods of attaching a die to a substrate
KR20200109493A (ko) * 2019-03-13 2020-09-23 (주)큐엠씨 반도체 칩을 전사하는 전사 장치 및 방법
CN109830453B (zh) * 2019-03-21 2023-10-03 深圳中科四合科技有限公司 一种芯片巨量转移的方法和装置
US11136202B2 (en) * 2020-01-06 2021-10-05 Asm Technology Singapore Pte Ltd Direct transfer apparatus for electronic components
KR102391169B1 (ko) * 2020-03-11 2022-05-03 넥스타테크놀로지 주식회사 실장 헤드 및 이를 포함하는 부품 실장 장치
KR102436955B1 (ko) * 2020-03-11 2022-08-26 넥스타테크놀로지 주식회사 실장 헤드 및 이를 포함하는 부품 실장 장치
KR102271499B1 (ko) * 2020-10-16 2021-07-01 넥스타테크놀로지 주식회사 실장 헤드 및 이를 포함하는 부품 실장 장치
FR3118514B1 (fr) * 2020-12-31 2023-03-03 Axem Tech Procédé de fabrication d’un identifiant RFID

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0232548A (ja) * 1988-07-22 1990-02-02 Hitachi Ltd フィルムパッケージ形半導体装置のペレットボンディング方法
JPH06204267A (ja) * 1993-01-08 1994-07-22 Nec Yamagata Ltd 半導体装置の製造方法
JP3955659B2 (ja) * 1997-06-12 2007-08-08 リンテック株式会社 電子部品のダイボンディング方法およびそれに使用されるダイボンディング装置
JP3994498B2 (ja) * 1998-01-30 2007-10-17 日立化成工業株式会社 半導体装置の製造方法
US6313522B1 (en) * 1998-08-28 2001-11-06 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
JP4137351B2 (ja) * 2000-06-29 2008-08-20 芝浦メカトロニクス株式会社 部品実装装置
JP2002026071A (ja) * 2000-07-05 2002-01-25 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
CN1149650C (zh) * 2001-04-16 2004-05-12 华瑞股份有限公司 充电电池保护电路用功率场效应晶体管的覆晶安装方法
DE10121578C2 (de) * 2001-05-03 2003-04-10 Infineon Technologies Ag Verfahren und Bestückungssystem zum Bestücken eines Substrats mit elektronischen Bauteilen
JP4000791B2 (ja) * 2001-06-15 2007-10-31 株式会社日立製作所 半導体装置の製造方法
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
JP3998993B2 (ja) * 2002-02-14 2007-10-31 大日本印刷株式会社 ウェブに実装されたｉｃチップへのアンテナパターン形成方法と印刷回路形成方法、およびｉｃタグ付き包装体
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US7246431B2 (en) * 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7575955B2 (en) * 2004-01-06 2009-08-18 Ismat Corporation Method for making electronic packages
JP2006196526A (ja) * 2005-01-11 2006-07-27 Omron Corp 半導体チップの実装方法、配線回路基板の構造、及び配線回路基板の製造方法

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