CN101355067A - 多芯片模块的改进的电连接 - Google Patents

多芯片模块的改进的电连接 Download PDF

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Publication number
CN101355067A
CN101355067A CNA2008101300084A CN200810130008A CN101355067A CN 101355067 A CN101355067 A CN 101355067A CN A2008101300084 A CNA2008101300084 A CN A2008101300084A CN 200810130008 A CN200810130008 A CN 200810130008A CN 101355067 A CN101355067 A CN 101355067A
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chip
lead
semiconductor chip
semiconductor
forms
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CN101355067B (zh
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李硕灿
金玟佑
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种多芯片模块的改进的电连接。一种半导体封装包括安装在基底上的第一半导体芯片和安装在第一半导体芯片的顶部的第二半导体芯片。在第一半导体芯片的顶部布置多个金属线，金属线与第一半导体芯片中的电路隔离。引线键合将第二半导体芯片上的焊盘连接到第一半导体芯片上的金属线。另外的引线键合将第一半导体芯片上的金属线连接到基底上的端子。导电的硅通孔或焊料凸点可代替金属键合，另外的芯片可包括在所述封装中。

Description

多芯片模块的改进的电连接
本发明要求于2007年7月23日在韩国知识产权局提交的第10-2007-0073476号韩国专利申请以及于2008年2月15日提交的第12/032,430号美国专利申请的优先权，其全部内容通过引用包含于此。
技术领域
本发明总体涉及多芯片模块，更具体地讲，涉及电连接到模块或在模块中的芯片之间进行电连接的方式。
背景技术
随着电子产品发展为更小的尺寸和更高的密度和性能，半导体相应地变得更小且其组件和连接变得更密。这又导致了多个半导体芯片堆叠在基底(例如，印刷电路板)上的多芯片封装(MCP)的发展。这样制造的封装不但尺寸小而且密度高、性能高。
然而，随着密度的增加和尺寸的减小，多芯片模块会出现问题。例如，在图1中，MCP包括安装在基底12上的第一半导体芯片10。第二半导体芯片14安装在半导体芯片10上，从而形成包括半导体芯片10和14的MCP。比芯片14大的芯片10包括端子，例如，端子16和18。芯片14也包括端子，例如，端子20和22。可看出，在芯片14上的端子的间隔比芯片10上的端子的间隔更紧密。在两个芯片上的端子通过引线键合(例如，引线键合28和30)电连接到导电焊盘，例如，形成在基底12上的焊盘24和26。
芯片14上的端子(例如，端子20和22)比芯片10上的端子(例如，端子16和18)进一步远离并更高于基底12。结果，与将芯片10上的端子连接到基底焊盘的引线键合相比，将芯片14上的端子连接到基底12的引线键合更长，并相对基底形成更大的角度。并且芯片14上的端子更紧密地靠近。所有的这些因素可能结合从而导致引线变形(wire sweeping)，其中，将芯片14上的端子连接到基底焊盘的引线键合彼此电短路。此外，每个引线键合越长，在制造中(例如，当包封引线时)引线越可能断掉。
除了这些问题之外，当(如在芯片14上的)端子紧密地靠近时，限制了相邻的端子可被引线键合到基底的数量。如图1中所示，因为键合的密度和长度限制相邻引线键合连接的数量，所以存在必须被包括的32通常表示的间隙。
期望在MCP的上面的芯片上提供更短并具有更小的相对于基底的键合角度的引线键合或其它的电连接。一个方法是使用重新分配网络，但因为芯片设计必须包括特定的电特性，所以该方法不能用于一些类型的芯片，这使得芯片设计复杂。
另一方法使用内插器，但这增加了制造成本，并且没有完全解决与长引线、相对基底高仰角处的端子和大键合角度相关的问题。
发明内容
一种半导体装置，包括：第一半导体芯片，具有内部电路区域，所述半导体芯片包括：第一侧；第二侧，与第一侧相对，第二侧具有在其上形成的多个端子，所述多个端子电连接到第一半导体芯片；至少一个导线，在所述侧之一上形成，导线与所述端子和所述内部电路区域电隔离。
一种半导体装置，包括：半导体芯片，具有在半导体芯片的一侧上形成的多个芯片焊盘；至少一个导电图案，在所述一侧上形成，所述图案与所述芯片焊盘实质上共面并电隔离，并在相同的沉积和蚀刻步骤期间形成所述图案作为芯片焊盘。
一种半导体封装，包括：基底；第一半导体芯片，安装在所述基底上；第二半导体芯片，安装在所述第一半导体芯片上；多个芯片焊盘，在第二半导体芯片的至少一侧上形成，以提供与第二半导体芯片的电连接；至少一个导线，在其上安装有第二半导体芯片的第一半导体芯片的所述侧上形成，所述导线与安装有第二半导体芯片的第一半导体芯片内的电路电隔离；第一电连接，在所述芯片焊盘之一和导线之间形成；第二电连接，在导线和基底之间形成。
一种存储卡，包括：基底；存储器芯片，安装在基底上；控制器芯片，安装在所述存储器芯片上；多个芯片焊盘，在控制器芯片的至少一侧上形成，以提供与控制器芯片的电连接；至少一个导线，在安装有控制器芯片的存储器芯片的所述侧上形成，所述导线与芯片焊盘电隔离；第一电连接，在所述芯片焊盘之一和导线之间形成；第二电连接，在导线和基底之间形成。
一种电子系统，包括：基底；存储器芯片，安装在基底上；处理器芯片，安装在所述存储器芯片上；多个芯片焊盘，在处理器芯片的至少一侧上形成，以提供与处理器芯片的电连接；至少一个导线，在安装有处理器芯片的存储器芯片的所述侧上形成，所述导线与芯片焊盘电隔离；第一电连接，在所述处理器芯片上的芯片焊盘之一和导线之间形成；第二电连接，在导线和基底之间形成；输入/输出装置，将信息传送给所述系统，以及从所述系统传送出信息。
一种制造半导体装置的方法，所述方法包括：在半导体芯片上形成多个端子，所述多个端子电结合到内部电路区域；在半导体芯片上形成至少一个导线，所述导线与所述多个端子和所述内部电路区域电隔离。
一种形成半导体封装的方法，包括：在基底上安装第一半导体芯片；在第一半导体芯片上安装第二半导体芯片，第二半导体芯片具有在第二半导体芯片的至少一侧上形成的多个芯片焊盘以提供与第二半导体芯片的电连接，并具有在安装有第二半导体芯片的第一半导体芯片的一侧上形成的至少一个导线，所述导线与第一半导体芯片内的电路电隔离；在芯片焊盘之一和导线之间形成第一电连接；在导线和基底之间形成第二电连接。
所述形成半导体封装的方法还可包括以下步骤：用环氧模制化合物来模制基底、第一半导体芯片和第二半导体芯片。
附图说明
图1是现有技术的MCP的局部放大图。
图2是根据本发明构造的半导体芯片的俯视图。
图3是沿图2中的线3-3截取的放大剖视图。
图4是按与图3和图4类似的示图描述的本发明的第二实施例。
图5是本发明的第三实施例的俯视图。
图6是本发明的第四实施例的俯视图。
图7是按与图3类似的示图描述的本发明的第五实施例。
图8是本发明的第六实施例的俯视图。
图9是根据本发明构造的第一MCP的透视示意图。
图10是根据本发明构造的第二MCP的透视示意图。
图11是根据本发明构造的第三MCP的透视示意图。
图12是根据本发明构造的第四MCP的透视示意图。
图13是根据本发明构造的第五MCP的透视示意图。
图14是本发明第五实施例的剖视图。
图15是根据本发明构造的第六MCP的透视示意图。
图16是本发明的第六实施例的剖视图。
图17是根据本发明构造的第七MCP的透视示意图。
图18是根据本发明构造的第八MCP的俯视示意图。
图19是根据本发明构造的卡的示意图。
图20是根据本发明构造的系统的示意图。
具体实施方式
再次参照附图，图2至图8示出在MCP中可被放置在另一芯片的顶部的各种半导体芯片。图9至图18示出在MCP中的包括图2至图8中描述的芯片的半导体芯片。
首先参照图2和图3，32通常表示的是半导体装置。装置32包括多个导线，例如，导线34和36。导线形成在介电层40的表面38上，介电层40又形成在半导体基底42上。如图所示，导线可形成线和间隔交替的图案。内部电路区域44形成在介电层40中。导电芯片焊盘(例如，焊盘46和48)形成在介电层40上，并连接到半导体装置32的内部电路部分(未描述)。钝化层50形成在介电层40上。
开口(例如，开口52和54)形成在钝化层50中，开口52暴露芯片焊盘46的一部分，开口54暴露导线34的一部分。每个芯片焊盘(例如，芯片焊盘46和48)包括相应的开口以暴露芯片焊盘，用于与外部电路连接。另外的开口(例如，开口54)以这里将更充分描述的方式形成在至少一些金属线上。
可以以与导线(例如线34和36)的形成相同的工艺步骤或不同的步骤形成芯片焊盘(例如，芯片焊盘46和48)。导线与芯片焊盘电隔离。在MCP中提供电源或对地连接的导线可比其它导线宽。
在图4中，56通常表示的是根据本发明的另一半导体芯片。与先前标识的结构相应的结构没有进行标号或具有相同的标号。在芯片56中，导线(例如，导线34和36)形成在钝化层50的顶部，而不是如图3中形成在介电层40的顶部。树脂层58形成在钝化层50的顶部，并包括开口(例如开口60和62)，以如图3中的开口52和54相同的方式暴露芯片焊盘和导线的部分。树脂层58包括包含聚酰亚胺的聚合物层。
在芯片56中，可在不同的平面中以不同的工艺步骤形成芯片焊盘和导线。为了增加引线键合效率并防止在引线键合期间由芯片焊盘和导线之间的高度差所引起的困难，在进一步的工艺步骤中，芯片焊盘(例如芯片焊盘46)的高度可被延伸到虚线64的水平，从而使导线和芯片焊盘的上表面位于基本相同的平面。
可以以形成导线的相同工艺步骤实现芯片焊盘(例如，芯片焊盘46)到虚线64的水平的延伸，从而使导线和芯片焊盘的上表面位于基本相同的平面。例如，在形成如图3中所示的开口52之后，覆盖导电层(未示出)可形成在钝化层50和芯片焊盘46上。可通过覆盖导电层的传统图案化工艺形成导线和芯片焊盘的延伸部分(未示出)。树脂层58形成在钝化层50的顶部，并包括开口(例如，开口62和开口60的上部)，以与图3中的开口52和54相同的方式暴露芯片焊盘的延伸部分和导线的部分。
在图5中，66通常表示的是根据本发明的另一半导体芯片。与先前标识的结构相应的结构没有进行标号或具有相同的标号。在芯片66中，导线(例如，导线34和36)相对于普通矩形形状的芯片66成角度。线34和36可以以任意角度布置，并且不是必须为线性(例如，一条或多条线可以为曲线)只要线与芯片焊盘(例如，焊盘46和48)电隔离。
在图6中，68通常表示的是根据本发明的另一半导体芯片。与先前标识的结构相应的结构没有进行标号或具有相同的标号。在芯片56中，导线(例如，导线34和36)被分为两组70和72，所述组被74通常表示的间隔分开。结果，线34和36分别与在同一直线上的线76和78电隔离。将看到，因为每组中的线(例如，线34和36)彼此电隔离，所以这允许这些线传播不同的信号。
在图7中，80通常表示的是根据本发明的另一半导体芯片。与先前标识的结构相应的结构没有进行标号或具有相同的标号。在芯片80中，尽管在图7中芯片焊盘的连接不可见，但与其他几个导线和芯片焊盘一样，导线中的至少一个(例如，82)和芯片焊盘46的每个分别连接到导电的硅通孔(TSV)83和84。每个导电TSV被连接到导电焊盘(例如，焊盘86和88)。
通过介电层40和半导体基底42形成每个TSV，从而将信号从金属线和芯片焊盘传送到半导体芯片80的下侧的导电焊盘(例如，焊盘86和88)。将看到，在MCP中，这种布置便于连接。还在图4的实施例中使用该方法。
在图8中，90通常表示的是根据本发明的另一半导体芯片。与先前标识的结构相应的结构没有进行标号或具有相同的标号。半导体芯片90以与图6中的半导体芯片68类似的方式布置导线。然而，芯片90包括中心芯片焊盘(例如，芯片焊盘92和94)。与其他实施例中的芯片焊盘相同，芯片90中的芯片焊盘将电路内部电连接到芯片90。然而，与其他实施例不同，被电连接到单个相应的导线的芯片90上的每个芯片焊盘(例如，芯片焊盘92和94)分别连接到线76和34。可看出，存在不与芯片焊盘连接的另外的导线。这另外未连接的线与内部芯片电路和芯片焊盘电隔离。这种布置提供了经连接到每个焊盘的导线重新分配芯片焊盘上信号，将结合图18对此进行进一步描述。
图9中的96通常表示的是MCP。MCP包括第一半导体芯片98和第二半导体芯片100。与先前标识的结构相应的结构没有进行标号或具有相同的标号。以与图2和图3中的芯片32类似的方式构成芯片98。通过粘合剂将芯片100安装在芯片98上，并且仍然通过使用粘合剂将芯片98安装在基底102上。芯片98的第一侧(不可见)安装在基底102上。芯片100安装在芯片98的第二侧99上。
芯片100包括被显示为通过引线键合(例如，引线键合104)连接到导线34的导电焊盘。以图3中所示的方式通过蚀刻到钝化层50中的开口106暴露导线34的一部分。这允许通过键合工艺将引线键合104电连接到导线。结果，通过芯片100上的芯片焊盘和引线键合104将芯片100上的内部电路电连接到导线34。这对芯片100的内部电路的连接点进行了重新分配。
导线34之上的另一开口108提供到导线的访问，用于将另一线110的一个端子键合到导线34。将线110的另一端子键合到基底102上的端子112。如图所示，通过引线键合(例如，引线键合104)将芯片100上的其他端子键合到其他导线，并通过引线键合(例如，引线键合110)将这些其他端子又键合到诸如基底102上的端子112的端子。以这种方式，重新分配了到芯片100中的电路的连接，以便于以消除与传统方法的长度、高度和键合角度有关的问题的方式进行引线键合。通过引线键合(例如，引线键合116)将第一半导体芯片98上的芯片焊盘或端子连接到诸如基底102上的端子114的端子。这里，将将诸如端子114的端子称为电触点。
该方法提供了用这样的引线键合电连接芯片100和基底102，所述引线键合具有与将芯片98上的焊盘连接到基底的引线键合类似的长度、高度和键合角度。
图10中的118通常表示的是MCP。MCP包括第一半导体芯片120、第二半导体芯片122和第三半导体芯片124。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图9中的芯片98类似地来构成芯片120。以与在图9中将芯片100安装到芯片98上的方式类似的方式将芯片122和124安装在芯片120上。
芯片124包括以与将芯片122上的焊盘连接到金属线的方式类似的方式被连接到金属线的焊盘。例如，在芯片124上，引线键合126将芯片122上的焊盘之一连接到导线128。通过蚀刻的开口132将另一引线键合130连接到导线128。将引线键合130的另一端子连接到基底102上的一个端子。
因为每个导线与其他每个导线和内部半导体电路隔离，所以相邻导线(例如，线34和128)可分别用于给定芯片122和124上的焊盘的连接的路线。在MCP 118，每隔一个导线与芯片122和124的每一个的连接相关。换句话讲，如果对导线连续编号，则奇数导线连接到一个芯片的焊盘，偶数导线连接到另一芯片的焊盘。
图11的134通常表示的是MCP。MCP包括第一半导体芯片136和第二半导体芯片138。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图6中的芯片68类似地构成芯片136。以与在图9中将芯片100安装在芯片98上的方式类似的方式将芯片138安装在芯片136上。
可看出，通过如先前所述的引线键合将芯片138的一侧上的焊盘连接到线组70中的相邻线，通过引线键合将另一侧上的焊盘连接到线组72中的相邻线。通过另一引线键合将芯片138上的焊盘连接到的每一线依次连接到基底102上的端子。结果，因为芯片136的至少两侧可通过金属线组70和72用作信号路径，所以可增加沿第二芯片的边缘焊盘的引脚(即，焊盘的数量)。
图12中的140通常表示的是MCP。MCP包括第一半导体芯片142、第二半导体芯片144和第三半导体芯片146。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图11中的芯片136类似地构成芯片142。以与前面描述的将芯片安装在第一半导体芯片上的方式类似的方式将芯片142和144安装在芯片140上。
在MCP 140中，以前面描述的方式通过引线键合将芯片144上的焊盘连接到组70中的导线，将芯片146上的焊盘连接到组72中的导线。还是如前面所描述的，通过引线键合将两组导线依次连接到基底102上的端子。提供该方法用于高密度MCP。
图13中的148通常表示的是MCP。MCP包括第一半导体芯片150和第二半导体芯片152。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图9中的芯片98类似地构成芯片150。使用焊料凸点154和156(最好参看图14)来将芯片152安装在芯片150上。将焊料凸点154安装在连接到芯片152的内部电路的芯片焊盘158上。但是，焊料凸点156只对芯片152提供结构支撑；焊料凸点156不连接到任何内部芯片电路。传送焊盘158上出现的任何电压的金属线34支撑焊料凸点154和156。芯片152上的凸点的间距实质上与芯片150上的导线(例如，导线34)的间距相同。该方法便于与芯片152上形成的凸点键合的倒装芯片键合的使用。结果，不存在连接到第二芯片的引线键合，因此，消除了与使用引线键合有关的缺点。
在可选择的方法(未示出)中，可在钝化层50上支撑的芯片152的下侧的导线34上的钝化层中的开口内完全容纳导电凸点154。这可能需要比图14中描述的更厚的钝化层，但因为芯片安置在钝化层50上并由钝化层50支撑，所以不需要支撑凸点(例如，凸点156)。
在另一可选择的方法中，可用朝向基底102包括芯片焊盘的有源(active)表面将第一半导体芯片150安装在基底102上。在所述结构中，在与第一半导体芯片150的有源表面相对的表面(即，半导体基底42的暴露表面)上形成绝缘层(未示出)。可在绝缘层(未示出)上形成导线。可通过倒装芯片键合将第一半导体芯片150结合到基底102，可使用导线在第二半导体芯片120和基底102之间形成电连接。可以以这里描述的任何方式将第二半导体芯片连接到导线。
图15和图16中的159通常表示的是MCP。MCP包括第一半导体芯片160和第二半导体芯片162。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图7中的芯片80类似地构成第一半导体芯片160和第二半导体芯片162，第一半导体芯片160和第二半导体芯片162中的每一个具有导电TSV(例如，芯片160中的TSV 166和芯片162中的TSV 164)。
将TSV 164的一端连接到在芯片162上形成的导电焊盘168。将焊盘168连接到芯片162的内部电路。将TSV 164的另一端连接到重新分配的焊盘170，所述焊盘170又安装在导线34上。可选择地，可不需要重新分配的焊盘170而直接将TSV 164连接到导线34。
将TSV 166(在芯片160中)的上端连接到导线34的下侧，将TSV 166的下端连接到基底102上形成的端子172。结果，通过焊盘168、TSV 164、导线34和TSV 166将芯片162中的内部电路连接重新分配给基底102上的端子172。该方法不需要任何引线键合。换句话讲，所述方法不需任何引线键合地来提供MCP。用粘合剂层173将第一半导体芯片160稳固到基底102。
图17中的174通常表示的是MCP。MCP包括第一半导体芯片176、第二半导体芯片178和第三半导体芯片180。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图9中的芯片98类似地构成芯片176和178。芯片176和178彼此实质上相同，并可包括例如存储器芯片。可看出，以芯片176和178的中心彼此偏移的方式将芯片178安装在芯片176上。这导致芯片178的两侧与芯片176的两边缘重叠，从芯片176的其他两边缘的背面设置芯片176的其他两侧的实质部分。结果，可在芯片176的导线和基底102的端子之间产生引线键合连接(例如，引线键合110)，还可在芯片178上的导线和芯片176上的导线之间产生引线键合连接(例如，引线键合186)。当然，优选地，可以以较大芯片在较小芯片之下的方式来堆叠不同大小的芯片。
通过使用粘合剂将芯片180(可以是例如诸如处理器的LSI电路)安装在芯片178上。通过使用引线键合(例如，引线键合188)将芯片180上的焊盘连接到芯片178上的导线。结果，可通过引线键合(例如，引线键合188)将芯片180内部的电路连接到芯片178上的导线。通过引线键合(例如，引线键合186)将这些导线连接到芯片176上的导线，通过引线键合(例如，引线键合110)将又芯片176上的导线连接到基底102上的端子(例如，端子112)。
通过引线键合(例如，分别通过引线键合190和192)将芯片176和178上的端子连接到基底102上的端子。在可选择的实施例(未示出)中，可使用TSV(例如，图7、图15和图16中示出的TSV)提供如图17中引线键合显示的一些或者甚至所有连接。
图18中194通常表示的是MCP。MCP包括第一半导体芯片196和第二半导体芯片198。与先前标识的结构相应的结构没有进行标号或具有相同的标号。与图8中的芯片90类似地构成芯片196。芯片196包括多个导电芯片焊盘(例如，在芯片198之下的芯片196的上表面上布置的焊盘200和202)。在芯片198之下两个实质上平行的行中布置芯片196上的这些焊盘，焊盘200位于一行，焊盘202位于另一行。
将组70和72中的每一个中的每隔一个导线连接到焊盘(例如，焊盘200和202)中的一个。通过引线键合(例如，分别通过引线键合210和212)将组70和72中的每一个中的每隔一个导线连接到芯片198的上表面上的导电焊盘(例如，焊盘206和208)。换句话讲，将每个偶数导线连接到芯片196的上表面上的焊盘(例如，焊盘200和202)，将每个奇数导线连接到芯片198的上表面上的焊盘(例如，焊盘206和208)，用引线键合(例如，引线键合210和212)来形成后面的连接。
另外的引线键合(例如，引线键合214和216)分别将导线连接到基底102上的端子(例如，端子218和220)。在可选择的实施例(未示出)中，在芯片196上的两行焊盘之间将比芯片198小的芯片安装在芯片196上。换句话讲，第二芯片没有覆盖第一芯片上的焊盘。
现在参看图19，222通常表示的是根据本发明构成的卡的示意图。例如，卡222可以是多媒体卡(MMC)或安全数字(SD)卡。卡222包括控制器224和存储器226，所述存储器226可以是闪存、PRAM或其他类型的非易失性存储器。228通常表示的通信信道允许控制器将命令提供给存储器，并将数据传送给存储器226，并从存储器226传送出数据。控制器224和存储器226可包括根据先前描述的实施例的MCP。卡222可具有比传统类型大的密度。在本发明中，可移除内插芯片，从而可相对于具有内插芯片的传统卡减小卡厚度。另外，本发明可减小由引线断掉所引起的卡的缺陷，从而可增加卡的可靠性。
现在考虑图20，230通常表示的是根据本发明的系统。例如，系统230可以是计算机系统、移动电话、MP3播放器、GPS导航装置、固态盘(SSD)、家电等。系统230包括：处理器232；存储器234，可以是DRAM、闪存、PRAM或其他类型的存储器；和输入/输出装置236。通信信道238允许处理器将命令提供给存储器，以通过信道238将数据传送给存储器234和从存储器234传送出数据。可通过输入/输出装置236将数据和命令传输给230以及从系统230传送出数据和命令。处理器232和存储器234可包括根据先前描述的任何实施例的MCP。因为本发明可减小由引线断掉所引起的缺陷，所以本发明可制造稳定的系统。

Claims (51)

1、一种半导体装置，包括：
第一半导体芯片，具有内部电路区域，所述半导体芯片包括：
第一侧；
第二侧，与第一侧相对，第二侧具有在其上形成的多个端子，所述多个端子电连接到第一半导体芯片；
至少一个导线，在所述侧之一上形成，导线与所述端子和所述内部电路区域电隔离。
2、如权利要求1所述的半导体装置，还包括：
绝缘层，覆盖内部电路区域和所述端子，所述导线布置在所述绝缘层上。
3、如权利要求2所述的半导体装置，还包括：
钝化层，覆盖所述绝缘层。
4、如权利要求3所述的半导体装置，还包括：
多个开口，在所述钝化层中形成，所述多个开口暴露所述端子和所述导线。
5、如权利要求3所述的半导体装置，还包括：
树脂层，覆盖所述钝化层，所述端子布置在所述钝化层中，所述导线布置在所述树脂层中。
6、如权利要求5所述的半导体装置，还包括：
在所述钝化层中形成的多个开口，所述多个开口暴露所述端子和所述导线。
7、如权利要求5所述的半导体装置，其中，树脂层包含聚酰亚胺。
8、如权利要求1所述的半导体装置，其中，导线形成线和间隔交替的图案。
9、如权利要求1所述的半导体装置，还包括：
第二半导体芯片，安装在第一半导体芯片上；
电连接，在第二半导体芯片上的导线和端子之间形成。
10、如权利要求9所述的半导体装置，还包括：
基底，所述第一侧稳固到所述基底；
电触点，在所述基底上形成；
电连接，在导线和电触点之间。
11、如权利要求10所述的半导体装置，其中，所述至少一个电连接是引线键合。
12、如权利要求10所述的半导体装置，其中，在第一半导体芯片的第二侧上形成所述导线。
13、如权利要求10所述的半导体装置，其中，在第一半导体芯片的第一侧上形成所述导线。
14、如权利要求1所述的半导体装置，其中，所述半导体还包括在所述侧之一上形成的多个导线。
15、如权利要求14所述的半导体装置，其中，所述多个导线形成分离的两组实质上平行的导体。
16、一种半导体装置，包括：
半导体芯片，具有在半导体芯片的一侧上形成的多个芯片焊盘；
至少一个导电图案，在所述一侧上形成，所述图案与所述芯片焊盘实质上共面并电隔离，并在相同的沉积和蚀刻步骤期间形成所述图案作为芯片焊盘。
17、如权利要求16所述的半导体装置，还包括：
非导电材料层，在所述一侧上的半导体芯片上形成；
多个开口，在非导电材料中，在芯片焊盘之上形成；
一对开口，在导电图案之上形成。
18、如权利要求16所述的半导体装置，其中，所述导电图案包括多个实质上平行的线。
19、如权利要求18所述的半导体装置，其中，所述导电图案包括实质上分离的两组实质上平行的线。
20、一种半导体封装，包括：
基底；
第一半导体芯片，安装在所述基底上；
第二半导体芯片，安装在所述第一半导体芯片上；
多个芯片焊盘，在第二半导体芯片的至少一侧上形成，以提供与第二半导体芯片的电连接；
至少一个导线，在其上安装有第二半导体芯片的第一半导体芯片的所述侧上形成，所述导线与安装有第二半导体芯片的第一半导体芯片内的电路电隔离；
第一电连接，在所述芯片焊盘之一和导线之间形成；
第二电连接，在导线和基底之间形成。
21、如权利要求20所述的半导体封装，其中，第二半导体芯片具有与第一半导体芯片相邻的侧，并在所述第二半导体芯片上形成芯片焊盘。
22、如权利要求20所述的半导体封装，其中，第二半导体芯片具有远离第一半导体芯片的第一侧和与第一半导体芯片相邻的第二侧，在第一侧上形成所述芯片焊盘。
23、如权利要求20所述的半导体封装，其中，第一电连接和第二电连接中的至少一个是引线键合。
24、如权利要求20所述的半导体封装，其中，第一电连接包括在所述芯片焊盘之一和导线之间形成的焊料凸点。
25、如权利要求24所述的半导体封装，还包括：第二焊料凸点，在第二半导体芯片和第一半导体芯片之间形成，第二焊料凸点与第一半导体芯片和第二半导体芯片内的电路电隔离。
26、如权利要求20所述的半导体封装，其中，所述电连接中的至少一个包括硅通孔。
27、如权利要求20所述的半导体封装，其中，第一电连接包括焊料凸点，第二电连接包括硅通孔。
28、如权利要求20所述的半导体封装，其中，半导体封装还包括：在安装有第二半导体芯片的第一半导体芯片的侧上形成的多个导线。
29、如权利要求28所述的半导体封装，其中，导线中的至少一个不具有与基底的电连接。
30、一种存储卡，包括：
基底；
存储器芯片，安装在基底上；
控制器芯片，安装在所述存储器芯片上；
多个芯片焊盘，在控制器芯片的至少一侧上形成，以提供与控制器芯片的电连接；
至少一个导线，在安装有控制器芯片的存储器芯片的所述侧上形成，所述导线与芯片焊盘电隔离；
第一电连接，在所述芯片焊盘之一和导线之间形成；
第二电连接，在导线和基底之间形成。
31、一种电子系统，包括：
基底；
存储器芯片，安装在基底上；
处理器芯片，安装在所述存储器芯片上；
多个芯片焊盘，在处理器芯片的至少一侧上形成，以提供与处理器芯片的电连接；
至少一个导线，在安装有处理器芯片的存储器芯片的所述侧上形成，所述导线与芯片焊盘电隔离；
第一电连接，在所述处理器芯片上的芯片焊盘之一和导线之间形成；
第二电连接，在导线和基底之间形成；
输入/输出装置，将信息传送给所述系统，以及从所述系统传送出信息。
32、一种制造半导体装置的方法，所述方法包括：
在半导体芯片上形成多个端子，所述多个端子电结合到内部电路区域；
在半导体芯片上形成至少一个导线，所述导线与所述多个端子和所述内部电路区域电隔离。
33、如权利要求32所述的方法，还包括以下步骤：
在半导体芯片上形成绝缘层，所述绝缘层上布置端子和导线。
34、如权利要求33所述的方法，还包括以下步骤：
在所述绝缘层上形成钝化层。
35、如权利要求34所述的方法，其中，形成端子和形成至少一个导线的步骤包括：
在绝缘层上布置导电层；
将导电层图案化，以形成端子和导线，
其中，在相同的图案化处理中形成所述端子和导线，
钝化层覆盖所述端子和导线。
36、如权利要求35所述的方法，还包括以下步骤：
在钝化层中形成多个开口，以暴露端子和导线。
37、如权利要求34所述的方法，其中，形成端子和形成导线的步骤包括：
在绝缘层上布置第一导电层；
图案化第一导电层，以形成端子；
在绝缘层和端子上布置钝化层；
在钝化层上布置第二导电层；
图案化第二导电层，以形成导线；
在导线上布置树脂层。
38、如权利要求37所述的方法，还包括以下步骤：
在布置第二导电层之前形成多个开口，以暴露端子的一部分。
39、如权利要求37所述的方法，还包括以下步骤：
在树脂中形成多个开口，以暴露端子和导线。
40、如权利要求32所述的方法，其中，半导体芯片包括第一半导体芯片，所述方法还包括以下步骤：
在第一半导体芯片上安装第二半导体芯片；
在第二半导体芯片上的导线和端子之间形成电连接。
41、一种形成半导体封装的方法，包括：
在基底上安装第一半导体芯片；
在第一半导体芯片上安装第二半导体芯片，第二半导体芯片具有在第二半导体芯片的至少一侧上形成的多个芯片焊盘以提供与第二半导体芯片的电连接，并具有在安装有第二半导体芯片的第一半导体芯片的一侧上形成的至少一个导线，所述导线与第一半导体芯片内的电路电隔离；
在芯片焊盘之一和导线之间形成第一电连接；
在导线和基底之间形成第二电连接。
42、如权利要求41所述的方法，还包括以下步骤：
用环氧模制化合物来模制基底、第一半导体芯片和第二半导体芯片。
43、如权利要求41所述的方法，其中，第二半导体芯片具有与第一半导体芯片相邻的侧，并在所述侧上形成芯片焊盘。
44、如权利要求41所述的半导体封装，其中，第二半导体芯片具有背离第一半导体芯片的第一侧和与第一半导体芯片相邻的第二侧，在第一侧上形成芯片焊盘。
45、如权利要求41所述的半导体封装，其中，第一电连接和第二电连接中的至少一个是引线键合。
46、如权利要求41所述的半导体封装，其中，第一电连接包括在所述芯片焊盘之一和导线之间形成的焊料凸点。
47、如权利要求46所述的半导体封装，还包括以下步骤：在第二半导体芯片和第一半导体芯片之间形成第二焊料凸点，第二焊料凸点与第一半导体芯片和第二半导体芯片内的电路电隔离。
48、如权利要求41所述的半导体装置，其中，所述电连接中的至少一个包括硅通孔。
49、如权利要求41所述的半导体装置，其中，第一电连接包括焊料凸点，第二电连接包括硅通孔。
50、如权利要求41所述的半导体装置，其中，半导体封装还包括：在安装有第二半导体芯片的第一半导体芯片的侧上形成的多个导线。
51、如权利要求50所述的半导体装置，其中，导线中的至少一个不具有与基底的电连接。
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