CN101359657A - 多芯片直流-直流升压功率变换器的有效力封装结构 - Google Patents

多芯片直流-直流升压功率变换器的有效力封装结构 Download PDF

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Publication number
CN101359657A
CN101359657A CNA2008101078987A CN200810107898A CN101359657A CN 101359657 A CN101359657 A CN 101359657A CN A2008101078987 A CNA2008101078987 A CN A2008101078987A CN 200810107898 A CN200810107898 A CN 200810107898A CN 101359657 A CN101359657 A CN 101359657A
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chip
schottky diode
vertical mosfet
pedestal
encapsulation
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CN101359657B (zh
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弗兰茨娃·赫尔伯特
郑伟强
张艾伦
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Alpha and Omega Semiconductor Inc
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

一种直流－直流升压变换器的多芯片半导体封装具有输出功率肖特基二极管和受功率调节控制器(PRC)控制的低压侧垂直MOSFET。该多芯片封装包括一个有肖特基二极管和垂直MOSFET并排于其上的单芯片基座。该功率调节控制器芯片通过绝缘芯片粘结材料装在该单芯片基座上。作为替换，该单芯片基座接地，垂直MOSFET是一顶部为漏极的垂直N沟道场效应晶体管，肖特基二极管芯片的衬底是其阳极，肖特基二极管和垂直MOSFET以堆叠的方式而位于单芯片基座的上部。功率调节控制器通过标准导电芯片粘结材料装于单芯片基座的上部。肖特基二极管芯片可以使用倒装结构，并以其阴极作为其衬底；或者，肖特基二极管芯片还可以以其阳极作为垫板不使用倒装芯片结构。本发明具有高效力的封装优点。

Description

多芯片直流-直流升压功率变换器的有效力封装结构
技术领域
本发明涉及电力供给和转换领域，尤其涉及交换式电源供应器和直流-直流电压转换器的物理层封装。
背景技术
由于其体积小、轻薄和高效，交换式电源供应器和转换器曾经日益扩大其在消费电子产业的市场份额。对于体积小、低成本、轻薄和较长的电池使用寿命为其重要考虑因素的便携设备来说尤其如此。而且由于便携设备越来越复杂，新的特点越来越多，因此，在一个便携设备中越来越需要不同的电压等级。例如，显示器和接口设备相比需要不同的操作电压，而接口设备和微处理器比起来又需要不同的操作电压。便携设备的不同组建模块所需要的不同电压由不同的直流—直流电压转换器来提供。
一个交换式电源供应和转换的典型例子是图1所示的简化了的升压转换器电路1。非稳压直流输入电压(VIN)2，通过由肖特基二极管5，垂直MOSFET4和一电感器组成的储能装置和转换电路被升为稳压直流输出电压(VOUT)3。对于熟知本领域的技术人员来说，垂直的MOSFT的物理芯片的源极和漏极置于芯片的不同表面，因此元件电流以垂直芯片表面的方向流动，这是为什么称其为垂直元件。内部结构仅仅简单描述的功率调节控制器13控制着垂直MOSFET 4的栅极10，其接地源极8和漏极9同肖特基二极管5的阳极6和电感器11相连。和肖特基二极管5的阴极7连接在一起的稳定输出电压3，通过充电或者放电的输出电容器12和接地点14连接。如图所示，垂直MOSFET 4是垂直N沟道场效应晶体管，其元件电流流向是从非稳定输入电压2到接地点14。举个实际例子，锂电池非稳定直流输入电压2的范围是从+2.7到+5.5伏，并且升压的稳定输出电压3可以达到+32伏。对于熟知本领域的技术人员来说，简单地将垂直MOSFET 4换成垂直P沟道场效应晶体管并且变换肖特基二极管5的极性，升压转换器电路1将会将不稳定的负的输入电压(比如-3.3+/-10％伏)升为更高级别的稳定的输出负电压(比如-28伏)。
为了形成产品，肖特基二极管5、垂直MOSFET 4和功率调节控制器13所需的各种集成电路芯片需要被安装在不同的芯片基座来将电路的半导体元件放在一个封装包里。在包装水平上，重要的是将不同的集成电路芯片高效封装在较少的芯片基座上并使用标准引线框架。其优点是产品尺寸减少，成本低，市场化时间短(通过使用标准引线框架)，在很多情况下还能减少多种电路寄生干扰。
图2A展示了现有技术封装的例子FAIRCHILD AN5606，它是一种具有电流调节升压直流—直流转换器的系列LED驱动。注意到有两个芯片基座，芯片基座20a和20b，他们被装在一个引线框架22上。由于芯片基座20a和20b之间必须有芯片基座间距21，结果导致了引线框架22的尺寸比只有单芯片基座时的尺寸要大。另外，虽然这里不能直接显示，芯片间连接线的间距的最小几何学限制导致了一个更大的芯片间距空间，因此，进一步增大了引线框架22的尺寸，下面将描述。
图2B展示了升压转换器电路1的现有技术多芯片封装35。肖特基二极管30芯片一般来说其阴极30b作为底部衬底，阳极30a置于顶部。垂直MOSFET31芯片一般是其漏极31b作为衬底，它的源极和栅极31a在顶部。因此，引线框架需要两个绝缘芯片基座，即肖特基二极管芯片基座30c和MOSFET芯片基座31c，用以安装肖特基二极管30芯片和垂直MOSFET 31芯片，将其用模塑料(未显示)包起来形成一个封装包，在最后和其他电路元件(例如电感器和电容器)安装于印刷电路板33上形成电路。另外，封装包内需要连接线34a将肖特基二极管30的阳极30a和垂直MOSFET 31的漏极电连接起来。作为现有技术多芯片封装35的另外一个说明部分，虽然对理解现有技术不是很重要，需要连接线34b来将MOSFET源极和接地引线电连接起来。
由于两个绝缘芯片基座(肖特基二极管芯片基座30c和MOSFET芯片基座31c)之间必须有足够的最小间距来维持其绝缘性和生产的可行性，因此，需要较大的封装包且需要使用非标准引线框架，结果导致了生产成本的提高。所需的连接线34a进一步增加了封装包的成本。另外，由于连接线34a和寄生电容和电感互联，导致升压转换器电压转换效率的降低。本质上，需要减少现有技术多芯片封装35的复杂性和所需空间。
发明内容
本发明的目的在于提供一种直流-直流升压转换装置的高效力多芯片半导体封装结构，有效地缩小了芯片基座的面积，达到一种高效的封装结构。
为达上述目的，本发明提供一种直流-直流升压转换装置的高效力多芯片半导体封装结构，其中，升压变换器将一个不稳定的直流输入电压转换为稳定的直流输出电压。其包含一输出功率肖特基二极管和一其栅极被一功率调节控制器(PRC)控制的低压侧垂直MOSFET。这个多芯片半导体封装包含一个单芯片基座引线框架，垂直MOSFET装在芯片基座的上部，肖特基二极管的阳极和垂直MOSFET的漏极相连的。
在本发明的一个实施例中，肖特基二极管和垂直MOSFET并排置于芯片基座上，且肖特基二极管的阳极通过该芯片基座和垂直MOSFET的漏极电连接。因此，功率调节控制器芯片通过一绝缘芯片粘结材料装在单芯片基座之上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
本发明的另外一个实施例中，单芯片基座接地。因此，垂直MOSFET是一垂直N沟道场效应晶体管，肖特基二极管芯片的衬底是其阳极，垂直MOSFET的顶部是其漏极。肖特基二极管芯片和垂直MOSFET芯片以肖特基二极管芯片装于垂直MOSFET芯片的上部这种堆栈的方式共同封装于单芯片基座的上部，达到最小化垂直MOSFET的源极电感并且容易散热。由于单芯片基座接地，功率调节控制器芯片通过一个标准导电芯片粘结材料装于单芯片基座的上部，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
在更详细的实施例里，肖特基二极管芯片以其阴极为其衬底并且肖特基二极管芯片以倒装配置的方式封装。或者，肖特基二极管以其阳极作为衬底且肖特基二极管芯片不以倒装配置的方式封装。
应用中，不稳定的直流输入电压和稳定的直流输出电压都是负电压，因此垂直MOSFET是垂直P沟道FET，肖特基二极管芯片以其衬底作为其阳极而垂直MOSFET的衬底作为其漏极。肖特基二极管芯片和垂直MOSFET芯片并列共同封装于单芯片基座之上。因此，PRC芯片通过绝缘芯片粘结材料装于单芯片基座的上面，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
应用中，不稳定的直流输入电压和稳定的直流输出电压都是负电压，因此，垂直MOSFET是一垂直P沟道FET，单芯片基座接地。肖特基二极管芯片以其衬底作为阴极而垂直MOSFET的顶部作为其漏极，因此，肖特基二极管芯片和垂直MOSFET芯片以肖特基二极管的芯片位于垂直MOSFET芯片之上这种堆栈的方式共同封装置于单芯片基座之上，减少垂直MOSFET源极电感并且容易散热。由于单芯片基座接地，PRC芯片可通过一标准导电芯片粘结材料附贴于单芯片基座之上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
本发明所提供的多芯片直流-直流升压转换器的有效力封装结构有效地缩小了芯片基座的面积，达到一种高效的封装结构。
本发明的以上说明和其各种具体实施例，将使熟知本领域的技术人员更易于进一步了解本发明。
附图的简要说明
为了更详细的描述本发明的各种实施例，标号的目的是为了说明附图；然而，这些附图的目的仅仅是为了说明而不能被理解为对本发明的限制。
图1是升压转换器电路示意图。
图2A是现有技术封装示意图。
图2B是现有技术升压转换器封装示意图。
图3A，图3B和图3C是本发明多芯片半导体封装的第一个实施例的示意图。
图4A，图4B和图4C是本发明多芯片半导体封装的第二个实施例的示意图。
图5A，图5B，图5C和图5D是本发明多芯片半导体封装的第三个实施例的示意图。
图6A，图6B和图6C是本发明多芯片半导体封装的第四个实施例的示意图。
具体实施方式
上文和下文的描述及包含的附图仅仅针对本发明的一个或者多个优选实施例，并且描述了一些可选择的特征或者可选择的实施方式。描述和给出的附图的目的是为了说明本发明，而不是用来对本发明的限制。因此，熟知本领域的技术人员也会认识到存在各种备选物、改进产品和对等物。这些备选物、改进产品和对等物应该被理解为也在本发明的范围之内。
图3A(侧视图)，图3B(俯视图)，图3C(俯视图)是本发明其肖特基二极管40和垂直MOSFET 41封装在一个模塑料49内的多芯片封装45和45a的第一个实施例。和使用两个芯片基座(肖特基二极管芯片基座30c和MOSFET芯片基座31c)的现有技术图2B所示的多芯片封装35相比较，本发明仅仅需要一个具有单芯片基座40c的引线框架来将肖特基二极管40和垂直MOSFET 41放在一个封装包中固定在印刷电路板43上。而图2B和图3A的垂直MOSFET芯片间水平元件终端配置是相同的，(底部衬底为MOSFET漏极31b和41b，上表面为MOSFET源极和栅极31a和41a)，图2B和图3A之间的肖特基二极管的芯片水平元件终端配置是相反的：
图2B：底部衬底为阴极30b，上表面为阳极31a
图3A：底部衬底为阳极40a，上表面为阴极40b
如图2B所示，肖特基二极管30芯片通常以其阴极30b作为衬底而其阳极30a在其上部。因此，注意到本发明的各种实施例中其肖特基二极管的底部衬底是其阳极，因此，肖特基二极管必须依此定制。这种衬底为阳极的肖特基二极管在2007年7月19日申请的名称为“底部阳极肖特基二极管结构和方法”的申请专利中公开过，并且在此作为参考引用。这样，本发明通过一个单芯片基座40c实现了肖特基二极管阳极40a和MOSFET漏极之间的连接，由此去掉了其间的连接线的复杂性(如图2B所示的连接线34a)。因此，与图2B现有技术多芯片封装35相比，本发明单芯片基座40c使用标准单芯片基座引线框架而实现了较小的封装包。不使用连接线34a，减少了封装的复杂性，因此降低了生产成本。另外，还除去了不合要求的和连接线34a相连的寄生电容和电感。一方面，现有技术中MOSFET源极31a和接地点引线32之间的连接线34b在本技术多芯片封装45中同样需要，并且他们被标注成连接线44b在相应的接地点引线42a处终止。另一方面，现有技术多芯片封装35也需要肖特基二极管阴极44b和本发明输出电压引线42b之间的连接线44c，他们只是为了避免混淆细节而在现有技术多芯片封装35中略去而已。另外，图3B本发明中MOSFET栅极41a和栅极引线10a之间的连接线44d在现有技术多芯片封装35中也是需要的，在现有技术多芯片封装35中没有显示出来的原因和上述一样是为了避免混淆细节。
图3C显示了在封装中还包含一个功率调节控制器46芯片。为了保持未接地单芯片基座40c的众多优点，功率调节控制器46芯片通过绝缘芯片粘结材料47(如绝缘环氧层)安装于单芯片基座上。如图所示，功率调节控制器46芯片和引线通过连接线44e电连接。因此，肖特基二极管40，垂直MOSFET41和功率调节控制器46共同封装于单芯片电路基座40c的上部。
图4A(侧视图)，图4B(俯视图)和图4C(俯视图)是本发明肖特基二极管40和垂直MOSFET 51位于一个模塑料49内共同封装的多芯片封装50和50a的第二个实施例。与图3A所示的本发明的上一个实施例相比，图3A和图4A的肖特基二极管40的芯片水平元件终端配置是相同的，(底部衬底为阳极40a，上表面为阴极40b)。然而，图3A和图4A的芯片水平设备终端配置的垂直MOSFET的是相反的：
图3A：底部衬底为MOSFET漏极41b，上表面为MOSFET源极和栅极41a
图4A：底部衬底为MOSFET源极51a，上表面为MOSFET栅极和漏极51b
如图2B所示，垂直MOSFET 31芯片一般是其MOSFET漏极31b作为其底部衬底而其源极和栅极位于顶部。由于本发明的各种实施例中MOSFET的底部衬底是其源极，因此，MOOSFET必须是定制的。这样的底部衬底MOSFET在专利申请号为11/495,803，专利申请日为2006年7月28的申请文件中公开过，并且在本发明中引用。这样，本发明多芯片封装50还实现了肖特基二极管40a和垂直MOSFET 41通过单芯片基座40c之间的连接，而去掉了它们之间的连接线的复杂性(图2B所示的连接线34a)。但是，与图3A将肖特基二极管40和垂直MOSFET 41并列排列不同，多芯片封装50以肖特基二极管40芯片位于垂直MOSFET 51芯片之上的这种堆栈的方式，将肖特基二极管40和垂直MOSFET 51共同封装于单芯片基座上，结果是进一步缩小了将放于更小的印刷电路板43上的封装包。另外，由于MOSFET源极51a通过单芯片基座40c接地，图3A所示的连接线44b也就可以去掉，由此可以进一步缩小芯片基座的大小，减少垂直MOSFET源极电感。一方面，本发明多芯片封装50的MOSFET漏极和肖特基阳极引线框架52之间的连接线44f在现有技术中也是需要的，他们只是在图2B中省略掉以避免模糊细节。同样，本发明肖特基二极管阴极40b和输出电压引线42b之间的连接线44c在现有技术多芯片封装35中也省略了，类似地，本发明MOSFET栅极51b和栅极引线10a之间的连接线44d在现有技术多芯片封装35中也省略掉了。
图4C展示了包含功率调节控制器芯片的封装包。由于单芯片基座40c已经接地，功率调节控制器46芯片仅仅通过一个标准传导芯片粘结材料53，如导电环氧层或者焊接物装于单芯片基座40c上。如图所示，功率调节控制器46芯片和引线之间通过连接线44e达到电连接。因此，肖特基二极管40，垂直MOSFET 51和功率调节控制器46共同封装于单芯片基座40c的上部。
图5A，图5B，图5D是本发明多芯片半导体封装的第三个实施例。如上图2B所示，肖特基二极管30芯片一般其阴极30b作为其底部衬底，其阳极30a位于上部。因此，认识到本发明的各种实施例中肖特基二极管的底部衬底是其阳极，因此肖特基二极管必须定制。然而，如图5A所示的替换物，肖特基二极管也能按照传统工艺制造，虽然变成倒装BGA(环栅阵列)型号肖特基二极管60，因此，其阴极衬底60b位于上部且其阳极焊接球61位于底部。图5B，图5C，和图5D展示了使用图3A，图3B，和图3C所示的封装从而得到变型的多芯片封装65和65a。同样，使用倒装结构的肖特基二极管60的图6A，图6B和图6C展示了使用图4A图4B图4C所示封装同样得到变型的封装结构70和70a。
现在熟知本领域的技术人员应该明白本说明书描述的各种实施例能够经过改变以适应其他特定的应用。例如，应用中，不稳定的直流输出电压2和稳定的直流输出电压3都是负电压，因此，垂直MOSFET 4是一个垂直P沟道FET，肖特基二极管5的衬底应该是阳极且垂直MOSFET 4的底部是漏极并排置于单芯片基座上。功率调节控制器46芯片通过一个绝缘芯片粘结材料装于单芯片基座上。或者，单芯片基座接地，肖特基二极管芯片的衬底是其阴极，垂直MOSFET 4的上部是其漏极，因此，肖特基二极管5芯片和垂直MOSFET 4芯片以肖特基二极管芯片位于垂直MOSFET 4之上这种堆栈方式共同封装于单芯片基座的上部，降低了垂直MOSFET源极电感并且容易散热。功率调节控制器46芯片通过标准传导芯片粘结材料装于单芯片基座上。
虽然以上的描述包含很多细节，但是，这些细节不能被理解为对本发明范围的限制，其仅仅是为提供了本发明的优选实施例描述。例如，本发明可以应用于有或者没有功率调节控制器46芯片的电路配置。
通过附图和说明，给出了特定配置的各种实施例。熟知本领域的技术人员明白本发明可体现于各种其他特定形式且熟知本领域的技术人员通过合理的试验能够实现本发明。本发明的范围，不局限于前面描述的实施例，任何给予变形都包含在本发明的精神和范围之内。

Claims (12)

1.一种用于直流-直流升压转换器设备的高效力封装的多芯片半导体封装，其升压变换器将一个不稳定的直流输入电压转换为稳定的直流输出电压，其特征在于，所述的多芯片半导体封装包括：具有单芯片基座的一引线框架；安装在该单芯片基座上的一垂直MOSFET；其阳极和所述的垂直MOSFET的漏极连接。
2.如权利要求1所述的多芯片半导体封装，其特征在于，还包括一功率调节控制器来控制该垂直MOSFET的栅极。
3.如权利要求1所述的多芯片半导体封装，其特征在于，所述的垂直MOSFET的漏极位于该多芯片半导体封装的底面，所述的肖特基二极管和该垂直MOSFET并排设置在该单芯片基座上，且肖特基二极管的阳极在底面上的肖特基二极管的阳极通过该单芯片基座同该垂直MOSFET的漏极电连接。
4.如权利要求3所述的多芯片半导体封装，其特征在于，所述的肖特基二极管芯片的衬底是其阴极，且肖特基二极管芯片以倒装接法封装。
5.如权利要求2所述的多芯片半导体封装，其特征在于，所述的功率调节控制器芯片通过绝缘芯片粘结材料装在该单芯片基座上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少了单芯片基座的面积。
6.如权利要求5所述的多芯片半导体封装，其特征在于，其肖特基二极管芯片的衬底是其阴极，且该肖特基二极管芯片以倒装组态封装。
7.如权利要求1所述的多芯片半导体封装，其特征在于，所述的单芯片基座接地，所述的垂直MOSFET是一垂直N沟道场效应晶体管，所述的肖特基二极管芯片的衬底是其阳极且垂直MOSFET的顶部是其漏极，从而该肖特基二极管芯片和垂直MOSFET芯片以肖特基二极管芯片位于垂直MOSFET芯片上部这种堆叠方式而共同封装于该单芯片基座的上部，用以降低垂直MOSFET源极的电感并且易于散热。
8.如权利要求7所述的多芯片半导体封装，其特征在于，所述的功率调节控制器芯片通过一标准导电芯片粘结材料安装在该单芯片基座上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
9.如权利要求2所述的多芯片半导体封装，其特征在于，所述的不稳定的直流输入电压和稳定的直流输出电压是负电压，因此，垂直MOSFET是一垂直P沟道场效应晶体管，肖特基二极管的衬底是其阴极，所述的垂直MOSFET的底部是其漏极，该肖特基二极管芯片和垂直MOSFET芯片并列共同封装于该单芯片基座的上部。
10.如权利要求9所述的多芯片半导体封装，其特征在于，所述的功率调节控制器芯片进一步通过绝缘芯片粘结材料装安装在该单芯片基座上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少单芯片基座的面积。
11.如权利要求2说述的多芯片半导体封装，其特征在于，所述的不稳定的直流输入电压和稳定的直流输出电压是负电压，因此，该垂直MOSFET是一垂直P沟道场效应晶体管，所述的单芯片基座接地，所述的肖特基二极管芯片的衬底是其阴极，且垂直MOSFET的上部是其漏极，该肖特基二极管芯片和垂直MOSFET芯片以肖特基二极管芯片位于垂直MOSFET芯片上部这种堆叠的方式共同封装于单芯片基座的上部，降低了垂直MOSFET源极的电感并且易于散热。
12.如权利要求11所述的多芯片半导体封装，其特征在于，所述的功率调节控制器芯片进一步通过标准导电芯片粘结材料进一步安装在该单芯片基座上，使得所述的垂直MOSFET，肖特基二极管和功率调节控制器共同封装于该单芯片基座的上部，以进一步减少该单芯片基座的面积。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760724A (zh) * 2011-04-29 2012-10-31 万国半导体股份有限公司 一种联合封装的功率半导体器件
CN103296866A (zh) * 2012-02-28 2013-09-11 株式会社电装 具有开关元件的半导体模块
CN103579154A (zh) * 2012-07-30 2014-02-12 英飞凌科技股份有限公司 包括叠层的电气器件封装以及其制造方法
CN104218008A (zh) * 2013-06-04 2014-12-17 英飞凌科技奥地利有限公司 被包装半导体器件
CN107534031A (zh) * 2015-03-16 2018-01-02 克利公司 高速、高效sic功率模块
CN109346405A (zh) * 2018-11-23 2019-02-15 江苏新广联半导体有限公司 一种GaN基SBD倒装芯片的制备方法

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825508B2 (en) * 2006-07-28 2010-11-02 Alpha Omega Semiconductor, Inc. Multi-die DC-DC buck power converter with efficient packaging
US20080238252A1 (en) * 2007-03-27 2008-10-02 Barnard Jason J Piezoelectric resonant power generator
US8854019B1 (en) 2008-09-25 2014-10-07 Rf Micro Devices, Inc. Hybrid DC/DC power converter with charge-pump and buck converter
US8148815B2 (en) * 2008-10-13 2012-04-03 Intersil Americas, Inc. Stacked field effect transistor configurations
JP4803241B2 (ja) * 2008-11-27 2011-10-26 三菱電機株式会社 半導体モジュール
US8168490B2 (en) * 2008-12-23 2012-05-01 Intersil Americas, Inc. Co-packaging approach for power converters based on planar devices, structure and method
US9166471B1 (en) 2009-03-13 2015-10-20 Rf Micro Devices, Inc. 3D frequency dithering for DC-to-DC converters used in multi-mode cellular transmitters
JP5152526B2 (ja) * 2009-04-24 2013-02-27 株式会社デンソー 車載電力変換装置
US8315576B2 (en) 2009-05-05 2012-11-20 Rf Micro Devices, Inc. Capacitive compensation of cascaded directional couplers
US8410512B2 (en) * 2009-11-25 2013-04-02 Cree, Inc. Solid state light emitting apparatus with thermal management structures and methods of manufacturing
US8548398B2 (en) 2010-02-01 2013-10-01 Rf Micro Devices, Inc. Envelope power supply calibration of a multi-mode radio frequency power amplifier
US8538355B2 (en) 2010-04-19 2013-09-17 Rf Micro Devices, Inc. Quadrature power amplifier architecture
US8565694B2 (en) 2010-04-20 2013-10-22 Rf Micro Devices, Inc. Split current current digital-to-analog converter (IDAC) for dynamic device switching (DDS) of an RF PA stage
US8892063B2 (en) 2010-04-20 2014-11-18 Rf Micro Devices, Inc. Linear mode and non-linear mode quadrature PA circuitry
US8942651B2 (en) 2010-04-20 2015-01-27 Rf Micro Devices, Inc. Cascaded converged power amplifier
US9077405B2 (en) 2010-04-20 2015-07-07 Rf Micro Devices, Inc. High efficiency path based power amplifier circuitry
US8712349B2 (en) 2010-04-20 2014-04-29 Rf Micro Devices, Inc. Selecting a converter operating mode of a PA envelope power supply
US8842399B2 (en) 2010-04-20 2014-09-23 Rf Micro Devices, Inc. ESD protection of an RF PA semiconductor die using a PA controller semiconductor die
US8515361B2 (en) 2010-04-20 2013-08-20 Rf Micro Devices, Inc. Frequency correction of a programmable frequency oscillator by propagation delay compensation
US8706063B2 (en) 2010-04-20 2014-04-22 Rf Micro Devices, Inc. PA envelope power supply undershoot compensation
US8811921B2 (en) 2010-04-20 2014-08-19 Rf Micro Devices, Inc. Independent PA biasing of a driver stage and a final stage
US8699973B2 (en) 2010-04-20 2014-04-15 Rf Micro Devices, Inc. PA bias power supply efficiency optimization
US8731498B2 (en) 2010-04-20 2014-05-20 Rf Micro Devices, Inc. Temperature correcting an envelope power supply signal for RF PA circuitry
US9553550B2 (en) 2010-04-20 2017-01-24 Qorvo Us, Inc. Multiband RF switch ground isolation
US8983410B2 (en) 2010-04-20 2015-03-17 Rf Micro Devices, Inc. Configurable 2-wire/3-wire serial communications interface
US8542061B2 (en) 2010-04-20 2013-09-24 Rf Micro Devices, Inc. Charge pump based power amplifier envelope power supply and bias power supply
US8811920B2 (en) 2010-04-20 2014-08-19 Rf Micro Devices, Inc. DC-DC converter semiconductor die structure
US9900204B2 (en) 2010-04-20 2018-02-20 Qorvo Us, Inc. Multiple functional equivalence digital communications interface
US9184701B2 (en) 2010-04-20 2015-11-10 Rf Micro Devices, Inc. Snubber for a direct current (DC)-DC converter
US8989685B2 (en) 2010-04-20 2015-03-24 Rf Micro Devices, Inc. Look-up table based configuration of multi-mode multi-band radio frequency power amplifier circuitry
US9008597B2 (en) 2010-04-20 2015-04-14 Rf Micro Devices, Inc. Direct current (DC)-DC converter having a multi-stage output filter
US8947157B2 (en) 2010-04-20 2015-02-03 Rf Micro Devices, Inc. Voltage multiplier charge pump buck
US9214865B2 (en) 2010-04-20 2015-12-15 Rf Micro Devices, Inc. Voltage compatible charge pump buck and buck power supplies
US8983407B2 (en) 2010-04-20 2015-03-17 Rf Micro Devices, Inc. Selectable PA bias temperature compensation circuitry
US8559898B2 (en) 2010-04-20 2013-10-15 Rf Micro Devices, Inc. Embedded RF PA temperature compensating bias transistor
US9214900B2 (en) 2010-04-20 2015-12-15 Rf Micro Devices, Inc. Interference reduction between RF communications bands
US8913967B2 (en) 2010-04-20 2014-12-16 Rf Micro Devices, Inc. Feedback based buck timing of a direct current (DC)-DC converter
US9577590B2 (en) 2010-04-20 2017-02-21 Qorvo Us, Inc. Dual inductive element charge pump buck and buck power supplies
US8571492B2 (en) 2010-04-20 2013-10-29 Rf Micro Devices, Inc. DC-DC converter current sensing
US8942650B2 (en) 2010-04-20 2015-01-27 Rf Micro Devices, Inc. RF PA linearity requirements based converter operating mode selection
US8958763B2 (en) 2010-04-20 2015-02-17 Rf Micro Devices, Inc. PA bias power supply undershoot compensation
US8913971B2 (en) 2010-04-20 2014-12-16 Rf Micro Devices, Inc. Selecting PA bias levels of RF PA circuitry during a multislot burst
US9048787B2 (en) 2010-04-20 2015-06-02 Rf Micro Devices, Inc. Combined RF detector and RF attenuator with concurrent outputs
US9362825B2 (en) 2010-04-20 2016-06-07 Rf Micro Devices, Inc. Look-up table based configuration of a DC-DC converter
US8831544B2 (en) 2010-04-20 2014-09-09 Rf Micro Devices, Inc. Dynamic device switching (DDS) of an in-phase RF PA stage and a quadrature-phase RF PA stage
US9030256B2 (en) 2010-04-20 2015-05-12 Rf Micro Devices, Inc. Overlay class F choke
CN102468260B (zh) * 2010-11-04 2014-04-30 无锡华润安盛科技有限公司 兼容高低电压的引线框、引线框阵列及其封装结构
US8896131B2 (en) 2011-02-03 2014-11-25 Alpha And Omega Semiconductor Incorporated Cascode scheme for improved device switching behavior
US8610235B2 (en) 2011-09-22 2013-12-17 Alpha And Omega Semiconductor Incorporated Trench MOSFET with integrated Schottky barrier diode
US9065505B2 (en) 2012-01-31 2015-06-23 Rf Micro Devices, Inc. Optimal switching frequency for envelope tracking power supply
US9054040B2 (en) * 2013-02-27 2015-06-09 Infineon Technologies Austria Ag Multi-die package with separate inter-die interconnects
JP2014187086A (ja) 2013-03-22 2014-10-02 Toshiba Corp 半導体装置
US9041170B2 (en) 2013-04-02 2015-05-26 Infineon Technologies Austria Ag Multi-level semiconductor package
JP2015029040A (ja) * 2013-07-05 2015-02-12 サンケン電気株式会社 半導体モジュール、ｌｅｄ駆動装置及びｌｅｄ照明装置
US9666511B2 (en) * 2015-01-15 2017-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation method for a stand alone high voltage laterally-diffused metal-oxide semiconductor (LDMOS) transistor
DE102015104995B4 (de) 2015-03-31 2020-06-04 Infineon Technologies Austria Ag Verbindungshalbleitervorrichtung mit einem mehrstufigen Träger
US9754864B1 (en) * 2016-06-23 2017-09-05 Alpha And Omega Semiconductor Incorporated Semiconductor power device having single in-line lead module and method of making the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE1007283A3 (nl) * 1993-07-12 1995-05-09 Philips Electronics Nv Halfgeleiderinrichting met een most voorzien van een extended draingebied voor hoge spanningen.
US6506648B1 (en) * 1998-09-02 2003-01-14 Cree Microwave, Inc. Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure
US6788033B2 (en) * 2002-08-08 2004-09-07 Vlt, Inc. Buck-boost DC-DC switching power conversion
US7061057B2 (en) * 2004-06-16 2006-06-13 Cree Microwave, Llc Laterally diffused MOS transistor having N+ source contact to N-doped substrate
US20070146020A1 (en) * 2005-11-29 2007-06-28 Advanced Analogic Technologies, Inc High Frequency Power MESFET Gate Drive Circuits
US20070170897A1 (en) * 2006-01-26 2007-07-26 Advanced Analogic Technologies, Inc. High-Frequency Power MESFET Buck Switching Power Supply
US7825508B2 (en) * 2006-07-28 2010-11-02 Alpha Omega Semiconductor, Inc. Multi-die DC-DC buck power converter with efficient packaging
US7999363B2 (en) * 2007-01-25 2011-08-16 Alpha & Omega Semiconductor, Ltd Structure and method for self protection of power device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760724A (zh) * 2011-04-29 2012-10-31 万国半导体股份有限公司 一种联合封装的功率半导体器件
CN102760724B (zh) * 2011-04-29 2015-02-11 万国半导体股份有限公司 一种联合封装的功率半导体器件
CN103296866A (zh) * 2012-02-28 2013-09-11 株式会社电装 具有开关元件的半导体模块
CN103296866B (zh) * 2012-02-28 2015-10-21 株式会社电装 具有开关元件的半导体模块
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CN103579154B (zh) * 2012-07-30 2017-01-18 英飞凌科技股份有限公司 包括叠层的电气器件封装以及其制造方法
CN104218008A (zh) * 2013-06-04 2014-12-17 英飞凌科技奥地利有限公司 被包装半导体器件
CN104218008B (zh) * 2013-06-04 2017-04-12 英飞凌科技奥地利有限公司 被包装半导体器件
CN107534031A (zh) * 2015-03-16 2018-01-02 克利公司 高速、高效sic功率模块
CN107534031B (zh) * 2015-03-16 2020-09-11 克利公司 高速、高效SiC功率模块
CN109346405A (zh) * 2018-11-23 2019-02-15 江苏新广联半导体有限公司 一种GaN基SBD倒装芯片的制备方法

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