CN101395551B - 具有可编程字长的存储器阵列及其操作方法 - Google Patents
具有可编程字长的存储器阵列及其操作方法 Download PDFInfo
- Publication number
- CN101395551B CN101395551B CN2007800071344A CN200780007134A CN101395551B CN 101395551 B CN101395551 B CN 101395551B CN 2007800071344 A CN2007800071344 A CN 2007800071344A CN 200780007134 A CN200780007134 A CN 200780007134A CN 101395551 B CN101395551 B CN 101395551B
- Authority
- CN
- China
- Prior art keywords
- memory cell
- group
- row
- control signal
- apply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 619
- 238000000034 method Methods 0.000 title abstract description 53
- 238000007667 floating Methods 0.000 claims abstract description 108
- 210000000746 body region Anatomy 0.000 claims description 58
- 239000004065 semiconductor Substances 0.000 claims description 18
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 claims description 14
- 230000004044 response Effects 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 description 34
- 108091006146 Channels Proteins 0.000 description 25
- 230000008569 process Effects 0.000 description 25
- 239000000463 material Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 14
- 230000008901 benefit Effects 0.000 description 12
- 238000012360 testing method Methods 0.000 description 5
- 230000002411 adverse Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000006386 neutralization reaction Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241001269238 Data Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
Abstract
一种存储器单元阵列和具有存储器单元阵列的器件(即集成电路器件,例如逻辑器件(比如微控制器或微处理器)或存储器器件(比如离散存储器))包括在晶体管体中存储电荷的电浮置体晶体管以及用于读取、控制和/或操作这样的存储器单元阵列和这样的器件的技术。该存储器单元阵列和器件包括可变和/或可编程字长。字长与所选存储器单元行的所选存储器单元(经由地址数据来确定)有关。在一个实施例中,字长可以是少于或等于存储器阵列的所选行中存储器单元总数的所选行中任何存储器单元数目。在一个方面中,可以针对存储器阵列的所选行的所选存储器单元执行写入和/或读取操作,而所选行的未选存储器单元不受干扰。
Description
相关申请
本申请主张申请日为2006年4月7日、发明名称为“Memory ArrayHaving a Programmable Word Length,and Technique of ImplementingSame”的美国临时申请No.60/790,111的优先权,将该临时申请的内容通过引用全部结合于此。
技术领域
本发明涉及存储器单元、阵列、架构和器件以及用于读取、控制和/或操作这样的单元和器件的技术,且更具体地在一个方面涉及半导体动态随机存取存储器(“DRAM”)单元、阵列、架构和/或器件,其中存储器单元包括晶体管,该晶体管具有其中存储电荷的电浮置体。
使用提高性能、减少泄漏电流和增强整体比例的技术、材料和器件来利用和/或制作先进集成电路有持续的趋势。绝缘底半导体(Semiconductor-on-Insulator,SOI)是可以在其上或其中(下文统称为“其上”)制作或布置此类器件的材料。此类器件作为SOI器件已知并且例如包括部分耗尽(partially depleted,PD)器件、完全耗尽(fully dipleted,FD)器件、多栅极器件(例如双栅极或三栅极)和鳍式FET。
一类动态随机存取存储器单元特别地基于SOI晶体管的电浮置体效应(例如参见通过引用而结合于此的美国专利6,969,662)。在这方面,动态随机存取存储器单元可以包括PD或FDSOI晶体管(或在块材料/衬底中形成的晶体管)。晶体管的体区域就布置于体区域之下的绝缘层(或例如在块材料/衬底中的非传导区域)而言是电浮置的。存储器单元的状态由SOI晶体管的体区域内的电荷浓度来确定。
参照图1A、1B和1C,在一个实施例中,半导体DRAM阵列10包括多个存储器单元12,各存储器单元包括晶体管14,该晶体管具有栅极16、电浮置的体区域18、源极区20和漏极区22。体区域18布置于源极区20和漏极区22之间。另外,体区域18布置于可以是绝缘区(例如在SOI材料/衬底中)或非传导区(例如在块型材料/衬底中)的区域24上或上方。绝缘或非传导区24可布置于衬底26上。
通过向所选字线28、所选源极线30和/或所选位线32施加适当的控制信号来将数据写入所选存储器单元中或从所选存储器单元读取数据。作为响应,在电浮置体区18中积聚或从该电浮置体区发射和/或排出电荷载流子,其中按照电浮置体区18内的载流子数量来限定数据状态。值得注意的是,`662专利的全部内容,例如包括其中描述和图示的特征、属性、架构、配置、材料、技术和优点,通过引用而结合于此。
如上所述,DRAM阵列10的存储器单元12通过在例如N沟道晶体管的体区域18中积聚多数载流子(电子或空穴)34或从该体区域发射/排出多数载流子(参见图2A和2B)来操作。在这方面,例如在靠近源极区20和/或漏极区22经由撞击电离在存储器单元12的体区域18中积聚多数载流子(在本例中为“空穴”)代表逻辑高或“1”的数据状态(参见图2A)。例如经由正向偏置源极/体接合点和/或漏极/体接合点从体区域18发射或排出多数载流子34代表逻辑低或“0”的数据状态(参见图2B)。
值得注意的是,至少出于本讨论的目的,逻辑高或状态“1”对应于体区域中相对于未编程器件和/或用逻辑低或状态“0”编程的器件而言增加的多数载流子浓度。对照而言,逻辑低或状态“0”对应于体区域中相对于未编程器件和/或用逻辑高或状态“1”编程的器件而言减少的多数载流子浓度。
通过施加小的漏极偏压和在晶体管阈值电压以上的栅极偏压来执行传统的读取。感测的漏极电流取决于浮置体中存储的电荷,这使得有可能区分状态“1”和“0”。浮置体存储器器件具有与两个不同逻辑状态“1”和“0”对应的两个不同电流状态。
在一种传统的技术中,通过向晶体管的漏极施加小的偏压以及施加在晶体管的阈值电压以上的栅极偏压来读取存储器单元。在这方面,在利用N型晶体管的存储器单元背景下,向一个或多个字线28施加正电压以使能够读取与这样的字线相关联的存储器单元。漏极电流的量由在晶体管的电浮置体区中存储的电荷决定/影响。这样,传统的读取技术感测响应于预定电压在存储器单元的晶体管的栅极上的施加而提供/生成的沟道电流的量来确定存储器单元的状态;浮置体存储器单元可以具有与两个或更多不同逻辑状态对应的两个或更多不同电流状态(例如,与两个不同逻辑状态“1”和“0”对应的两个不同电流条件/状态)。
简言之,用于具有N沟道型晶体管的存储器单元的传统的写入编程技术常常通过沟道撞击电离(参见图3A)或通过带间隧穿(栅极引起的漏极泄漏“GIDL”)(参见图3B)来提供过量多数载流子。可以经由漏极侧空穴去除(参见图4A)、源极侧空穴去除(参见图4B)或例如使用反向栅极脉冲(back gate pulsing)的漏极和源极空穴去除(参见图4C)来去除多数载流子。
另外图5图示了传统的读取技术。在一个实施例中,可以通过感测响应于预定电压在存储器单元的晶体管的栅极上的施加而提供/生成的沟道电流的量来确定存储器单元的状态。
可以使用包括例如相对于传统技术而言可以提供更低功耗的技术的其它技术来编程/读取具有电浮置体晶体管14的存储器单元12。例如,可以使用在通过引用而结合于此的申请日为2006年8月24日而发明名称为“Memory Cell and Memory Cell Array Having an Electrically FloatingBody Transistor,and Methods of Operating Same”的美国非临时专利申请No.11/509,188(以下称为“`188专利”)中描述和图示的技术和电路对存储器单元12编程、读取和/或控制。在一方面,`188申请涉及允许低功率存储器编程并且提供更大存储器编程窗口(均与至少传统的编程技术相关)的编程、读取和/或控制方法。
参照图6,在一个实施例中,`188申请利用具有电浮置体晶体管14的存储器单元12。电浮置体晶体管14除MOS晶体管之外还包括本征双极晶体管(在某些境况之下包括大量本征双极电流)。在这一示例性示例实施例中,电浮置体晶体管14是N沟道器件。这样,多数载流子是“空穴”。
参照图7,在一个实施例中,`188申请使用(分别)向存储器单元12的晶体管14的栅极16、源极区20和漏极区22施加的控制信号(具有预定电压,例如Vg=0v、Vs=0v和Vd=3v)来利用、写入或编程逻辑“1”或逻辑高。该控制信号引起或导致撞击电离和/或雪崩倍增现象(参见图7)。与传统方法对照,控制信号的预定电压经由电浮置体中的撞击电离和/或雪崩倍增在存储器单元的晶体管中编程或写入逻辑“1”。在一个实施例中优选通过向栅极16施加的控制脉冲来发起和/或引起负责浮置体中撞击电离和/或雪崩倍增的双极晶体管电流。该脉冲可引起使浮置体电势增加并且接通双极电流的沟道撞击电离。所述方法的优点在于与其它技术相比生成更大量的过量多数载流子。
另外参照图8,在`188申请的一个实施例中,当在存储器单元12的晶体管14中写入或编程逻辑“0”时,控制信号(具有预定电压(例如Vg=1.5v、Vs=0v和Vd=0v))有所不同且在至少一个实施例中高于(分别)向存储器单元12的晶体管14的栅极16、源极区20和漏极区22施加的保持电压(如果适用)。该控制信号引起或提供从晶体管14的电浮置体去除多数载流子。在一个实施例中,通过源极区20和漏极区22从体区域18去除、消除或排出多数载流子(参见图8)。在这一实施例中,以逻辑“0”写入或编程存储器单元12同样可消耗相对于传统技术而言更低的功率。
当以存储器单元阵列配置来实施存储器单元12时,当对存储器单元阵列的一个或多个存储器单元12编程时为某些存储器单元12实施“保持”操作以增强该某些存储器单元12的数据保留特征可能是有利的。可以经由向存储器单元12的晶体管14的栅极16和源极区20及漏极区22施加的控制信号(具有预定电压)的施加将存储器单元12的晶体管14置于“保持”状态。该控制信号在与栅极电介质32和电浮置体区18之间的界面接近的区域中组合地提供、导致和/或引起多数载流子积聚(参见图9)。在这一实施例中,向其中晶体管14是N沟道型晶体管的栅极16施加负电压可能是优选的。
参照图10,在`188申请的一个实施例中,可以通过向晶体管14的栅极16和源极区20及漏极区22施加控制信号(具有预定电压,例如Vg=-0.5v、Vs=3v和Vd=0v)来读取和/或确定存储器单元12的数据状态。这样的信号在存储逻辑状态“1”的那些存储器单元12中组合地引起和/或导致双极晶体管电流。对于编程为逻辑状态“0”的那些存储器单元,这样的控制信号在编程为“0”状态的单元中不引起和/或导致相当大的、实质性的或可充分测量的双极晶体管电流(参见如上所述通过引用而结合于此的`188申请)。
如上所述,可以使用向字线28施加的正电压来执行读取。这样,在正栅极偏压与负栅极偏压之间使器件10的晶体管14定期产生脉冲,其中正栅极偏压(1)驱动远离晶体管14的栅极绝缘体32和体区域18之间的界面的多数载流子(N沟道晶体管的空穴)并且(2)使少数载流子(N沟道晶体管的电子)从源极区20和漏极区22流入在栅极16之下形成的沟道,而负栅极偏压使多数载流子(N沟道晶体管的空穴)在晶体管14的栅极16与体区域18之间的界面中或附近积聚。
继续参照图11和图12,在`188申请的这一示例实施例中,可以向存储器单元12b和12c施加具有预定幅度的控制信号以在其中写入或编程逻辑状态“0”。在这一示例性实施例中,在向存储器单元12b和12c的栅极16施加栅极脉冲之前或与此同时或在向存储器单元12b和12c的栅极16施加栅极脉冲之后可以向存储器单元12b和12c的源极区20施加源极脉冲。在这一示例实施例中,向存储器单元12b和12d的漏极区22施加漏极脉冲(在这一例子中幅度为0.5V)以防止、禁止、限制和/或阻碍双极电流(如果有)在存储器单元12b和12c的浮置体区域中导致或生成充分电荷以将逻辑状态“1”编程或写入到存储器单元12b和12c中。漏极脉冲防止双极电流和逻辑状态“1”的写入但是没有高到足以阻止多数电荷从浮置体区域排出,因此写入逻辑状态“0”。
从相对时序的观点来看,优选的是对存储器单元12b和12c的漏极区22施加漏极脉冲延伸的时间段,或在源极和栅极脉冲之前、期间和之后施加(例如发起、开始、斜升、斜降和/或终止),如图11所示。
值得注意的是,继续参照图11和图12,对于那些未选存储器单元(即耦合到字线28i+1、28i+2和28i+3的存储器单元),可以施加或建立保持条件以防止、最小化或避免对未选存储器单元的数据状态或未选存储器单元中存储的电荷的干扰。在这方面,可以向未选存储器单元的栅极16施加电压(例如-1.2V)以及可以向未选存储器单元的源极区20和漏极区22施加电压(例如0V)以防止、最小化或避免在编程或写入操作过程中对未选存储器单元中数据状态的干扰。在这些条件之下,对所选存储器单元12a-d的编程或写入并不影响(或基本上不影响)未选存储器单元的数据状态。
参照图11和图13,在`188申请中描述和图示的示例实施例中,可以向存储器单元的行(例如存储器单元12a-d)有选择地施加具有预定幅度的控制信号以读取所选存储器单元12a-12d的每一个中的数据状态。在这一示例实施例中,可以向源极区20施加3V的电压脉冲,可以向存储器单元12a-d的栅极16施加-0.5V的电压脉冲。在这一实施例中,在向栅极16施加栅极脉冲之前、与此同时或向栅极16施加栅极脉冲之后可以向源极区20施加源极脉冲。另外,源极脉冲可以在栅极脉冲之前、与此同时(如图11中所示)或在栅极脉冲结束或中止之后中止或终止。
值得注意的是,对于未读取的那些存储器单元(即耦合到字线28i+1、28i+2和28i+3的那些存储器单元),可以施加或建立保持条件以防止、最小化或避免对未选存储器单元中数据状态的干扰。在这方面,可以向未选存储器单元的栅极16施加电压(例如-1.2V)以及可以向未选存储器单元的源极区20施加电压(例如0V)以防止、最小化或避免在读取操作过程中对未选存储器单元中数据状态的干扰。在这些条件之下,对所选存储器单元12a-d的读取并不影响(或基本上不影响)未选存储器单元的状态。
就`188申请而言用以实施写入和读取操作的所示/示例电压电平仅为举例。示出的电压电平可以是相对的或绝对的。可替代地,示出的电压可以是相对的,因为不管一个或多个电压(例如源极、漏极或栅极电压)变成或是正电压和负电压,例如可以将各电压电平增加或减少给定的电压量(例如可以将各电压增加或减少0.25、0.5、1.0和2.0伏特)。
发明内容
这里描述和图示了许多发明。本发明既不限于其任何单个方面或实施例也不限于这些方面和/或实施例的组合和/或交换。另外,本发明的各方面和/或其实施例可以独自地或与本发明的一个或多个其它方面和/或实施例组合地加以利用。为求简洁,许多交换和组合将不在这里个别地加以讨论。
在第一主要方面中,本发明涉及一种包括存储器单元阵列的集成电路器件(例如逻辑或离散存储器器件),该存储器单元阵列具有多个字线、多个源极线、多个位线以及按行和列的矩阵排列的多个存储器单元,其中各存储器单元包括电浮置体晶体管。该电浮置体晶体管(例如N沟道型晶体管或P沟道型晶体管)包括:耦合到相关联的源极线的第一区域;耦合到相关联的位线的第二区域;布置于第一区域和第二区域之间的体区域,其中体区域是电浮置的;以及布置于体区域之上并且耦合到相关联字线的栅极。存储器单元包括多个数据状态,这多个数据状态包括:(i)第一数据状态,代表电浮置体晶体管的体区域中的第一电荷;以及(ii)第二数据状态,代表电浮置体晶体管的体区域中的第二电荷。
这一方面的集成电路器件还包括:第一电路,耦合到第一行存储器单元的各存储器单元,以并行施加:(i)写入控制信号到第一行存储器单元的第一组存储器单元以在其中写入多个数据状态中的一个;以及(ii)写入取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止在其中写入多个数据状态中的一个。
第一组存储器单元的存储器单元数目可以对应于存储器单元阵列的字长。在一个实施例中,该集成电路器件包括用以存储代表字长的数据的字长选择电路(例如熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器、寄存器和/或例如经由向信号线或管脚施加的电压来固定)。
在一个实施例中,写入取消选择控制信号包括(i)向第二组存储器单元的各存储器单元的栅极施加的第一随时间改变的信号、(ii)向第二组存储器单元的各存储器单元的第一区域施加的第二随时间改变的信号和(iii)向第二组存储器单元的各存储器单元的第二区域施加的第三随时间改变的信号。在这一实施例中,写入控制信号可以包括(i)向第一组存储器单元的各存储器单元的栅极施加的第一随时间改变的信号、(ii)向第一组存储器单元的各存储器单元的第一区域施加的第二随时间改变的信号和(iii)向第一组存储器单元的各存储器单元的第二区域施加的第四随时间改变的信号。
在另一实施例中,写入取消选择控制信号包括(i)向第二组存储器单元的各存储器单元的栅极施加的第一随时间改变的信号、(ii)向第二组存储器单元的各存储器单元的第一区域施加的第二随时间改变的信号和(iii)向第二组存储器单元的各存储器单元的第二区域施加的具有基本上恒定的电压幅度的第三信号。在这一实施例中,写入控制信号可以包括(i)向第一组存储器单元的各存储器单元的栅极施加的第一随时间改变的信号、(ii)向第一组存储器单元的各存储器单元的第一区域施加的第二随时间改变的信号和(iii)向第一组存储器单元的各存储器单元的第二区域施加的第四随时间改变的信号。
该集成电路器件还可以包括:第二电路,耦合到第一行存储器单元的各存储器单元以并行施加:(i)读取控制信号到第一行存储器单元的第一组存储器单元以读取第一组存储器单元的各存储器单元的数据状态;以及(ii)读取取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止读取第二组存储器单元的各存储器单元的数据状态。
读取控制信号可以包括向第一组存储器单元的各存储器单元的电浮置体晶体管的栅极施加的信号、向该电浮置体晶体管的第一区域施加的信号和向该电浮置体晶体管的第二区域施加的信号以导致、强制和/或引起读取双极晶体管电流,该读取双极晶体管电流代表第一行存储器单元的第一组存储器单元的各存储器单元的数据状态。
在一个实施例中,第二电路基本上基于读取双极晶体管电流来确定存储器单元的数据状态。实际上,第二电路可以包括多个感测放大器。
在另一实施例中,写入控制信号包括用以写入第一数据状态的控制信号,以及其中响应于用以将第一数据状态写入第一行存储器单元的预定存储器单元的控制信号,第一行存储器单元的预定存储器单元的电浮置体晶体管生成在第一行存储器单元的预定存储器单元的电浮置体晶体管的体区域中基本上提供第一电荷的双极晶体管电流。
在一个实施例中,存储器单元可以存储多于一个数据位(例如两位、三位、四位、五位、六位等)和/或多于两个数据状态(例如三个、四个、五个、六个等数据或逻辑状态)。这样,存储器单元阵列的各存储器单元可以包括代表电浮置体晶体管的体区域中第三电荷的第三数据状态。
在另一主要方面中,本发明涉及一种包括存储器单元阵列的集成电路器件(例如逻辑或离散存储器器件),该存储器单元阵列具有多个字线、多个源极线、多个位线以及按行和列的矩阵排列的多个存储器单元,其中各存储器单元包括电浮置体晶体管。该电浮置体晶体管(例如N沟道型晶体管或P沟道型晶体管)包括:耦合到相关联的源极线的第一区域;耦合到相关联的位线的第二区域;布置于第一区域与第二区域之间的体区域,其中体区域是电浮置的;以及布置于体区域之上并且耦合到相关联的字线的栅极。存储器单元包括多个数据状态,这多个数据状态包括:(i)第一数据状态,代表电浮置体晶体管的体区域中的第一电荷;以及(ii)第二数据状态,代表电浮置体晶体管的体区域中的第二电荷。
这一方面的集成电路器件还包括:电路(例如多个感测放大器),耦合到第一行存储器单元的各存储器单元,以基本上并行施加:(i)读取控制信号到第一行存储器单元的第一组存储器单元以读取第一组存储器单元的各存储器单元的数据状态;以及(ii)读取取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止读取第二组存储器单元的各存储器单元的数据状态。
在一个实施例中,读取控制信号包括向第一组存储器单元的各存储器单元的电浮置体晶体管的栅极施加的信号、向该电浮置体晶体管的第一区域施加的信号和向该电浮置体晶体管的第二区域施加的信号以导致、强制和/或引起读取双极晶体管电流,该读取双极晶体管电流代表第一行存储器单元的第一组存储器单元的各存储器单元的数据状态。在这一实施例中,该电路可以基本上基于读取双极晶体管电流来确定存储器单元的数据状态。
在一个实施例中,该集成电路器件还可以包括:写入电路,耦合到第一行存储器单元的各存储器单元,以并行施加:(i)写入控制信号到第一行存储器单元的第一组存储器单元以在其中写入多个数据状态之一;以及(ii)写入取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止在其中写入多个数据状态之一。写入控制信号包括用以写入第一数据状态的控制信号,以及其中响应于用以将第一数据状态写入第一行存储器单元的预定存储器单元的控制信号,第一行存储器单元的预定存储器单元的电浮置体晶体管生成在第一行存储器单元的预定存储器单元的电浮置体晶体管的体区域中基本上提供第一电荷的双极晶体管电流。
第一组存储器单元的存储器单元数目可以对应于存储器单元阵列的字长。在一个实施例中,集成电路器件包括用以存储代表字长的数据的字长选择电路(例如熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器、寄存器和/或例如经由向信号线或管脚施加的电压来固定)。
在又一主要方面中,本发明涉及一种包括半导体存储器阵列的集成电路器件(例如逻辑或离散存储器器件),该半导体存储器阵列布置于半导体区或层之中或其上,该半导体区或层驻留在衬底的绝缘区或层上或其以上。该半导体存储器阵列包括多个字线、多个源极线、多个位线以及按行和列的矩阵排列的多个存储器单元,其中各存储器单元包括电浮置体晶体管。该电浮置体晶体管(例如N沟道型晶体管或P沟道型晶体管)包括:耦合到相关联的源极线的第一区域;耦合到相关联的位线的第二区域;布置于第一区域和第二区域之间的体区域,其中体区域是电浮置的;以及布置于体区域之上并且耦合到相关联的字线的栅极。存储器单元包括多个数据状态,这多个数据状态包括:(i)第一数据状态,代表电浮置体晶体管的体区域中的第一电荷;以及(ii)第二数据状态,代表电浮置体晶体管的体区域中的第二电荷。
这一方面的集成电路器件还包括:第一电路,耦合到第一行存储器单元的各存储器单元,以并行施加:(i)写入控制信号到第一行存储器单元的第一组存储器单元以在其中写入多个数据状态之一;以及(ii)写入取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止在其中写入多个数据状态之一。
这一方面的集成电路器件还包括:第二电路(例如多个感测放大器),耦合到第一行存储器单元的各存储器单元,以基本上并行施加:(i)读取控制信号到第一行存储器单元的第一组存储器单元以读取第一组存储器单元的各存储器单元的数据状态;以及(ii)读取取消选择控制信号到第一行存储器单元的第二组存储器单元以禁止读取第二组存储器单元的各存储器单元的数据状态。
在一个实施例中,读取控制信号包括向第一组存储器单元的各存储器单元的电浮置体晶体管的栅极施加的信号、向该电浮置体晶体管的第一区域施加的信号和向该电浮置体晶体管的第二区域施加的信号,以导致、强制和/或引起读取双极晶体管电流,该读取双极晶体管电流代表第一行存储器单元的第一组存储器单元的各存储器单元的数据状态。在这一实施例中,第二电路基本上基于读取双极晶体管电流来确定存储器单元的数据状态。
在一个实施例中,写入控制信号包括用以写入第一数据状态的控制信号,以及其中响应于用以将第一数据状态写入第一行存储器单元的预定存储器单元的控制信号,第一行存储器单元的预定存储器单元的电浮置体晶体管生成在第一行存储器单元的预定存储器单元的电浮置体晶体管的体区域中基本上提供第一电荷的双极晶体管电流。
第一组存储器单元的存储器单元的数目可以对应于存储器单元阵列的字长。在一个实施例中,该集成电路器件包括用以存储代表字长的数据的字长选择电路(例如熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器、寄存器和/或例如经由向信号线或管脚施加的电压来固定)。
如上所述,存储器单元可以存储多于一个数据位(例如两位、三位、四位、五位、六位等)和/或多于两个数据状态(例如三个、四个、五个、六个等数据或逻辑状态)。这样,存储器单元阵列的各存储器单元可以包括代表电浮置体晶体管的体区域中第三电荷的第三数据状态。
另外在此说明和示出了许多发明以及本发明的方面。此发明内容并非穷举本发明的范围。另外,此发明内容并非旨在于限制本发明的范围且不应当以这一方式来解释。尽管在此发明内容中说明和/或概括了某些实施例,但是应当理解本发明不限于这样的实施例、描述和/或概括,权利要求也不以这样的方式被限制(权利要求不应解释为由发明内容限制)。实际上,根据说明书、附图和权利要求,与在此发明内容中呈现的方面、发明和实施例可以不同和/或相似的许多其它方面、发明和实施例是明显的。此外,虽然各种特征、属性和优点在此发明内容中已经加以描述和/或根据该发明内容是清楚的,但是应当理解这样的特征、属性和优点无论在本发明的一个、一些还是所有实施例中并非是必需的并且实际上在本发明的任何实施例中并非必然存在。
附图说明
在以下的详细说明中将参照附图。这些附图示出了本发明的不同方面,而在适当之处在不同的图中示出相似结构、部件、材料和/或元件的附图标记被相似地标记。将理解到与具体示出的结构、部件、材料和/或元件不同的结构、部件、材料和/或元件的各种组合被预计并且在本发明的范围内。
而且,在此说明和示出了许多发明。本发明既不限于其任何单个方面或实施例也不限于这些方面和/或实施例的任何组合/或互换。另外,本发明的各方面和/或实施例可以独自地或与本发明的一个或多个其它方面和/或实施例组合地加以利用。为求简洁,许多组合和/或互换将不在这里个别地加以讨论。
图1A是包括多个存储器单元的现有技术DRAM阵列的示意表示图,其中各存储单元包括一个电浮置体晶体管;
图1B是包括一个电浮置体晶体管(PD-SOI NMOS)的示例现有技术存储器单元的三维图;
图1C是沿着线C-C’横切的图1B的现有技术存储器单元的横截面图;
图2A和2B是包括一个电浮置体晶体管(PD-SOI NMOS)的现有技术存储器单元的浮置体、源极区和漏极区就给定的数据状态而言的电荷关系的示意说明图;
图3A和3B是用以将存储器单元编程为逻辑状态“1”的传统方法的示例示意图和一般说明图(即在图1B的存储器单元的晶体管(在这一示例实施例中为N型沟道晶体管)的电浮置体中生成或提供过量多数载流子;通过沟道电子撞击电离(图3A)和通过GIDL或带间隧穿(图3B)来生成或提供这些示例实施例中的多数载流子);
图4A-4C是用以将存储器单元编程为逻辑状态“0”的传统方法的示例示意图和一般说明图(即通过从图1B的存储器单元的晶体管的电浮置体去除多数载流子来提供相对更少的多数载流子;可以通过晶体管的漏极区/端子(图4A)、晶体管的源极区/端子(图4B)以及使用例如向存储器单元的晶体管的衬底/背侧端子施加的反向栅极脉冲的晶体管的漏极和源极区/端子(图4C)去除多数载流子);
图5图示了传统读取技术的示例示意图(和控制信号),存储器单元的状态可由感测响应于预定电压在存储器单元的晶体管的栅极上的施加而提供/生成的沟道电流的量来确定;
图6是除MOS晶体管之外还包括本征双极晶体管的等效电浮置体存储器单元(N沟道型)的示意图。
图7图示了通过在存储器单元的晶体管的电浮置体中生成、存储和/或提供过量多数载流子来将存储器单元编程为逻辑状态“1”的`188申请的一个方面的示例实施例的示例示意图(和控制信号电压关系);
图8图示了通过在存储器单元的晶体管的电浮置体中生成、存储和/或提供相对更少多数载流子(与在编程为逻辑状态“1”的存储器单元的电浮置体中的多数载流子的数目相比)将存储器单元编程为逻辑状态“0”的`188申请的一个方面的示例实施例的示例示意图(和控制信号),其中通过向存储器单元的晶体管的栅极施加控制信号(例如编程脉冲)通过漏极和源极端子去除多数载流子(写入“0”);
图9图示了保持或维持存储器单元的数据状态的`188申请的一个方面的示例实施例的示例示意图(和控制信号);
图10图示了通过感测响应于预定电压在存储器单元的晶体管的栅极上的施加而提供/生成的电流的量来读取存储器单元的数据状态的`188申请一个方面的示例实施例的示例示意图(和控制信号);
图11图示了根据在`188申请中描述和图示的发明的一个实施例用以(i)将逻辑状态“1”编程或写入一个或多个N沟道型存储器单元中、(ii)将逻辑状态“0”编程或写入一个或多个N沟道型存储器单元中和(iii)读取一个或多个N沟道型存储器单元的所选写入控制信号的示例时序关系;
图12和图13图示了根据在`188申请中描述和图示的发明的某些方面的存储器阵列的示例实施例,该存储器阵列具有多个存储器单元(N沟道型)并且结合示例编程技术对各行存储器单元采用分离源极线配置,这些示例编程技术包括示例控制信号电压值(图11)和示例读取技术、包括示例控制信号电压值(图12);
图14图示了根据`188申请的一个实施例用以(i)将逻辑状态“1”编程或写入一个或多个P沟道型存储器单元中、(ii)将逻辑状态“0”编程或写入一个或多个P沟道型存储器单元中和(iii)读取一个或多个P沟道型存储器单元的所选写入控制信号的示例时序关系;
图15图示了根据本发明某些方面的存储器阵列的示例实施例,该存储器阵列结合控制信号电压对各行存储器单元采用共源极线配置以写入/编程所选存储器单元行的所选存储器单元以及控制电压以取消选择或“阻止”所选存储器单元行的未选存储器单元的写入/编程操作;
图16图示了根据本发明某些方面的存储器阵列的示例实施例,该存储器阵列结合控制信号电压对各行存储器单元采用共源极线配置以读取所选存储器单元行的所选存储器单元的数据状态以及控制电压以取消选择或“阻止”所选存储器单元行的未选存储器单元的读取操作;
图17、图18和图19图示了根据本发明某些方面用以(i)取消选择、编程或写入逻辑状态“1”到一个或多个N沟道型存储器单元中、(ii)取消选择、编程或写入逻辑状态“0”到一个或多个N沟道型存储器单元中和(iii)取消选择或读取一个或多个N沟道型存储器单元的所选写入控制信号的示例时序关系,其中取消选择控制信号包括脉冲特征(参见图17)和非脉冲特征(参见图18和图19);
图20A-20C是根据本发明一个或多个方面可以在其中实施存储器单元阵列(和某些外围电路)的示例集成电路器件的示意框图说明图;
图20D和20E是根据本发明一个或多个方面特别地包括存储器单元阵列、数据感测和写入电路、存储器单元选择和控制电路的集成电路器件的实施例的示意框图;以及
图21A-21C是根据本发明一个或多个方面结合具有可编程字长的存储器器件实施控制器/处理器的示例架构和/或实施例的示意图。
具体实施方式
在一个方面中,本发明涉及用于读取、控制和/或操作包括在晶体管体中存储电荷的电浮置体晶体管的半导体存储器单元、阵列、架构和器件(即集成电路器件,例如逻辑器件(比如微控制器或微处理器)或存储器器件(比如离散存储器))的技术。本发明还涉及包括用以实施该读取、控制和/或操作技术的电路的半导体存储器单元、阵列、架构和器件。
在一个实施例中,存储器单元阵列的字长(该字长与给定/预定的所选存储器单元行的所选存储器单元有关)是可变的和/或可编程的。字长可以是与所选行中任何存储器单元数目相等的量,小于或等于存储器阵列的所选行中存储器单元的总数。在本发明的一个方面中,可以关于存储器阵列的所选行的所选存储器单元(即第一组存储器单元)执行写入和/或读取操作,而所选行的未选存储器单元(即第二组存储器单元)不受干扰。
虽然不限于此,但是在本发明的某些方面中将在存储器阵列的字长可变和/或可编程的`188申请的实施例背景下进行说明。
参照示例实施例中的图15、图17和图18,可以(基于地址数据)有选择地将具有预定幅度的示例控制信号施加到给定/预定的存储器单元行(例如连接到同一字线即字线28i的存储器单元12a-d)以将逻辑状态“1”写入所选存储器单元12a中而将逻辑状态“0”写入所选存储器单元12b中。与之并行或基本上并行(下文统称为“并行”)向未选存储器单元12c和12d施加具有预定幅度的示例“写入取消选择”控制信号以防止、禁止和/或去使能写入操作,使得所选存储器单元行的存储器单元12c和12d分别保持于它们的现有存储器状态“0”和“1”。在这点上,向位线32j+2和32j+3施加“写入取消选择”电压脉冲以通过针对先前写入为逻辑状态“1”的单元(这里为存储器单元12c)的情况防止、最小化、消除和/或阻止电荷损失或针对先前写入为逻辑状态“0”的单元(这里为存储器单元12d)的情况防止、最小化、消除双极电流生成来防止、禁止和/或去使能关于存储器单元12c和12d的写入操作。通过向位线32j+2和32j+3施加取消选择控制信号,存储器单元12c和12d的数据状态不受干扰或不利的影响——尽管这样的存储器单元是所选存储器单元行的一部分(基于地址数据)。值得注意的是,可以在写入操作过程中如图17中所示向位线32j+2和32j+3施加取消选择控制信号作为电压脉冲,或可以如图18中所示向位线32j+2和32j+3持续施加取消选择控制信号。
参照示例实施例中的图16-19,向预定或给定的存储器单元行(例如连接到同一字线即字线28i的存储器单元12a-d)(基于地址数据)有选择地施加具有预定幅度的控制信号以读取所选存储器单元12a和12b。与之并行向未选存储器单元12c和12d施加具有预定幅度的示例“读取取消选择”控制信号以防止、禁止/或去使能读取操作,使得所选存储器单元行的存储器单元12c和12d不受读取操作的影响。在这点上,向位线32j+2和32j+3施加“读取取消选择”电压脉冲或恒定电压以防止、禁止和/或去使能关于存储器单元12c和12d的读取操作——尽管这样的存储器单元是所选存储器单元行的一部分。这样,存储器单元12c和12d不被读取、不受读取操作影响和/或不利影响。在这一实施例中,存储器单元12c和12d在读取操作过程中并不明显地传导电流也不受干扰——尽管经由字线28i存取存储器单元行。
(特别是)图15-19中所示用以执行所选操作(例如读取、写入、读取取消选择、写入取消选择、保持)的电压幅度仅为举例。所示电压电平可以是相对的或绝对的。可替代地,如上所述,所示电压可以是相对的,因为不管一个或多个电压(例如源极、漏极或栅极电压)成为或是正电压和负电压,例如可以将各电压电平增加或减少给定的电压量(例如可以将各电压增加或减少0.25、0.5、1.0和2.0伏特(或更多))。
值得注意的是,由于阵列字长和输入/输出字长之间的作为结果的不同,本发明与通过流水线技术典型地包括长行存储器单元阵列以求面积效率的现有技术相比而言具有一些优势。因为对于本发明写入或读取所选行的所选存储器单元,且所选行的未选存储器单元不受预定操作的不利影响,所以尽管维持长行存储器单元阵列以求面积效率,存储器阵列的字长可与输入/输出字长相同。在本发明中,写入或读取所选行的所选存储器单元(而所选行的未选存储器单元并不参与操作或不受操作的不利影响),因而在数据地址并不连续且流水线技术并不有效的情况下增强了功率管理,因为在读取操作过程中不从(假定不需要的)未选存储器单元读取或在写入操作过程中不向这些未选存储器单元写入。
此外,由于存储器单元阵列字长和输入/输出字长相同,所以可以以单个步骤或阶段将数据写入存储器阵列中或从存储器阵列读取数据,这可以提供更快的操作和/或更低功率消耗。在这点上,传统技术常常利用两步骤或阶段写入以先将数据写入锁存器中、然后将数据从锁存器写入存储器单元。类似地对于读取操作,先将数据从存储器单元阵列读取到锁存器中、随后读取到输出。本发明还允许例如通过控制数据写入和感测电路以及存储器单元选择和控制电路来随时在操作之间改变字长。
可以例如在制作时、在测试过程中和/或在原处设置和/或控制字长。例如,可以(i)在通电之后、例如在初始化阶段过程中或(ii)在操作过程中对集成电路器件编程以最小化功率消耗和最大化速度。例如在操作过程中,可以设置随机存取的字长与I/O宽度匹配以求最大速度。然而当数据地址连续时,可以将字长设置为等于行上物理位的数目,使得数据在一次操作中先被写入锁存器、然后被写入整行以求更低功率消耗。可以通过对集成电路的存储器的外部输入来指示连续数据地址,或可以在集成电路的存储器内部检测连续地址。关于不从存储器输入或输出数据但是必需刷新行上所有位的刷新操作,可以设置与行上物理位的数目相等的字长。以这一方式可以减少和/或最小化功率消耗。
值得注意的是,集成电路(例如处理器器件或离散存储器器件)的存储器阵列的字长可以是一次可编程(例如在测试过程中或在制造时编程)或多次可编程(例如在测试过程中、在启动/通电过程中、在初始化序列过程中和/或在操作过程中(在原处))。例如在一个实施例中,字长可以“存储”于驻留在集成电路上的字长选择电路中(例如熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器、寄存器和/或例如经由向信号线或管脚施加的电压来固定)(例如参见图20C和20D)。实际上,无论现在已知还是以后开发的任何编程技术和/或电路都将落入本发明的范围内。
用以确定、实施和/或编程字长的控制电路可以片上实施,即该控制电路驻留于器件上(即集成于器件中),或可以片外实施(即该控制电路布置于不同集成电路器件上或其中,例如布置于存储器控制器、微处理器和/或图形处理器上/中)。控制电路可以实施无论现在已知还是以后开发的任何编程技术和/或电路;所有这样的技术和电路都将落入本发明的范围内。
如上所述,本发明的存储器单元和/或存储器单元阵列以及电路可以实施于具有存储器部分和逻辑部分的集成电路器件中(例如参见图20A和20C)或主要是存储器器件的集成电路器件中(例如参见图20B)。存储器阵列可以包括以多行和多列排列的多个存储器单元,其中各存储器单元包括电浮置体晶体管。存储器阵列可以包括N沟道晶体管、P沟道晶体管和/或这两类晶体管。实际上,在存储器阵列外围的电路(例如数据感测电路(例如感测放大器或比较器)、存储器单元选择和控制电路(例如字线和/或源极线驱动器)以及行和列地址解码器)可以包括P沟道和/或N沟道型晶体管。
例如参照图20D和20E,集成电路器件可以包括具有多个存储器单元12的阵列10、数据写入和感测电路以及存储器单元选择和控制电路。数据写入和感测电路从所选存储器单元12读取数据和将数据写入所选存储器单元12。在一个实施例中,数据写入和感测电路包括多个数据感测放大器。各数据感测放大器接收至少一个位线32和参考生成器电路的输出(例如电流或电压参考信号)。在一个实施例中,数据感测放大器可以是用以感测存储器单元12中存储的数据状态和/或将数据写回存储器单元12中的一个或多个交叉耦合型感测放大器,比如在通过引用整体结合于此的申请人为Waller和Carman、申请日为2005年12月12日而发明名称为“Sense Amplifier Circuitry and Architecture to Write Data intoand/or Read Data from Memory Cells”的非临时美国专利申请No.11/299,590(美国专利申请公开号US2006/0126374)中描述和图示的交叉耦合型感测放大器。
可以用任何电浮置体存储器单元和存储器单元阵列来实施本发明(例如参见上述背景技术部分)。实际上在某些方面中,本发明是具有各包括电浮置体晶体管的多个存储器单元的存储器阵列和/或用以将数据写入或编程到这样的存储器阵列的一个或多个存储器单元中的技术。在本发明的这一方面中,可以对相邻的存储器单元和/或共享字线的存储器单元的数据状态单独编程。此外虽然已经例如在`188申请的实施例的背景下描述了本发明,但是可以用其它存储器单元和存储器阵列技术,例如1T-1C(一个晶体管、一个电容器)和电浮置栅极存储器单元来实施本发明。
存储器阵列可以包括N沟道型晶体管、P沟道型晶体管和/或这两类晶体管。实际上,在存储器阵列外围的电路(例如感测放大器或比较器、行和列地址解码器以及线驱动器(这里未图示))可以包括P沟道型和/或N沟道型晶体管。
当利用P沟道型晶体管作为存储器阵列中的存储器单元12时,有许多适当的写入和读取电压(例如负电压)(例如参见图14)。例如,可以通过向源极区施加-3V的电压脉冲从P沟道型存储器单元读取数据以及可以向要读取的存储器单元的栅极施加0.5V的电压脉冲。在这一实施例中,在向栅极施加栅极脉冲之前、与此同时或在向栅极施加栅极脉冲之后可以向源极区施加源极脉冲。另外,源极脉冲可以在栅极脉冲之前、与此同时(如图14中所示)或在栅极脉冲结束或中止之后中止或终止。
如上所述,可以结合任何电浮置体存储器单元(即包括至少一个电浮置体晶体管的存储器单元)和/或利用(其它类型的存储器单元中)这样的电浮置体存储器单元的架构、布局、结构和/或配置来采用本发明的电路和技术。例如,可以在以下临时和非临时美国专利申请中描述和图示的存储器单元、架构、布局、结构和/或配置中实施使用本发明的技术来读取、编程和/或控制其状态的电浮置体晶体管:
(1)Fazan等人于2003年6月10日提交且发明名称为“Semiconductor Device”的美国非临时专利申请No.10/450,238(现在为美国专利6,969,662);
(2)Fazan等人于2004年2月18日提交且发明名称为“Semiconductor Device”的美国非临时专利申请No.10/487,157(现在为美国专利7,061,050);
(3)Ferrant等人于2004年4月22日提交且发明名称为“Semiconductor Memory Cell,Array,Architecture and Device,andMethod of Operating Same”的美国非临时专利申请No.10/829,877(现在为美国专利7,085,153);
(4)Ferrant等人提交且发明名称为“Semiconductor Memory Deviceand Method of Operating Same”的美国非临时专利申请No.11/096,970(现在为美国专利7,085,156);
(5)Fazan等人于2004年9月15日提交且发明名称为“Low PowerProgramming Technique for a One Transistor SOI Memory Device&Asymmetrical Electrically Floating Body Memory Device,and Method ofManufacturing Same”的美国非临时专利申请No.10/941,692(美国专利申请公开号2005/0063224);
(6)Okhonin等人于2005年12月15日提交且发明名称为“BipolarReading Technique for a Memory Cell Having an Electrically FloatingBody Transistor”的美国非临时专利申请No.11/304,387(美国专利申请公开号2006/0131650);
(7)Okhonin等人于2006年6月15日提交且发明名称为“Method forReading a Memory Cell Having an Electrically Floating Body Transistor,and Memory Cell and Array Implementing Same”的美国非临时专利申请No.11/453,594;
(8)Okhonin等人于2006年8月24日提交且发明名称为“MemoryCell and Memory Cell Array Having an Electrically Floating BodyTransistor,and Methods of Operating Same”的美国非临时专利申请No.11/509,188(参见上文);
(9)Bauser于2006年9月5日提交且发明名称为“Method andCircuitry to Generate a Reference Current for Reading a Memory Cell,and Device Implementing Same”的美国非临时专利申请No.11/515,667;
(10)Popov等人于2006年10月31日提交且发明名称为“Methodand Apparatus for Varying the Programming Duration of a Floating BodyTransistor,and Memory Cell,Array,and/or Device Implementing Same”的美国非临时专利申请No.11/590,147;以及
(11)Okhonin等人于2007年2月7日提交且发明名称为“Multi-BitMemory Cell Having Electrically Floating Body Transistor,and Methodof Programming and Reading Same”的美国非临时专利申请No.11/703,429。
通过引用在此结合这十一(11)个美国专利申请的全部内容,包括例如其中描述和图示的发明、特征、属性、架构、配置、材料、技术和优点。为求简洁将不重复这些讨论;而是这些讨论(文字和图示),包括与存储器单元、架构、布局、结构有关的讨论通过引用整体结合于此。
值得注意的是,可以使用在上文引用的十一(11)个美国专利申请中描述和图示的任何控制电路来控制(例如编程或读取)(具有一个或多个晶体管的)存储器单元。为求简洁将不重复而通过引用在这里结合这些讨论。实际上,无论现在已知还是以后开发的用于对包括具有电浮置体区的晶体管的存储器单元编程、读取、控制和/或操作的所有存储器单元选择和控制电路以及技术都将落入本发明的范围内。
例如,可以使用包括在上文引用的十一(11)个美国专利申请中描述的电路和技术在内的(无论是否传统的)公知电路和技术来读取存储或写入到DRAM阵列/器件10的存储器单元12中的数据。本发明还可以采用在Portmann等人于2004年5月7日提交且发明名称为“ReferenceCurrent Generator,and Method of Programming,Adj usting and/orOperating Same”的美国专利申请No.10/840,902(现在为美国专利6,912,150)中描述和图示的读取电路和技术。
此外,本发明还可以利用在Bauser于2006年9月5日提交且发明名称为“Method and Circuitry to Generate a Reference Current for Readinga Memory Cell,and Device Implementing Same”的美国专利申请No.11/515,667中描述和图示的读取操作技术。如上所述,美国专利申请No.11/515,667的全部内容通过引用而结合于此。
另外,感测放大器(未详细示出)可以用来读取存储器单元12中存储的数据。感测放大器可以使用电压或电流感测技术来感测存储器单元12中存储的数据状态。在电流感测放大器的背景下,电流感测放大器可以比较单元电流和参考电流,例如参考单元(未示出)的电流。根据比较可以确定存储器单元12包含逻辑高(在体区域18内包含相对更多的多数载流子34)还是逻辑低数据状态(在体区域18内包含相对更少的多数载流子34)。
可以使用公知技术和/或材料来制作电浮置存储器单元、晶体管和/或存储器阵列。实际上,无论现在已知还是以后开发的任何制作技术和/或材料都可以用来制作电浮置体存储器单元、晶体管和/或存储器阵列。例如,本发明可以利用硅(无论块型还是SOI)、锗、硅/锗、砷化镓或任何其它可在其中形成晶体管的半导体材料。实际上,电浮置晶体管、存储器单元和/或存储器阵列可以利用在Fazan于2004年7月2日提交的发明名称为“Integrated Circuit Device,and Method of Fabricating Same”的非临时专利申请No.10/884,481和/或Bassin于2006年10月12日提交而又转让的发明名称为“One Transistor Memory Cell having a StrainedElectrically Floating Body Region,and Method of Operating Same”的非临时专利申请No.11/580,169(下文统称为“集成电路器件专利申请”)中描述和图示的技术。通过引用在这里结合集成电路器件专利申请的全部内容,包括例如其中描述和图示的发明、特征、属性、架构、配置、材料、技术和优点。
实际上,如在集成电路器件专利申请中描述和图示的那样,(包括SOI存储器晶体管的)存储器阵列10可以与SOI逻辑晶体管集成。例如在一个实施例中,集成电路器件包括存储器部分(具有例如PD或FD SOI存储器晶体管14)和逻辑部分(具有例如高性能晶体管如鳍式FET、多栅极晶体管和/或非高性能晶体管(例如不具备高性能晶体管的性能特征的单栅极晶体管——未图示))。同样通过引用在这里结合集成电路器件专利申请的全部内容,包括例如其中描述和图示的发明、特征、属性、架构、配置、材料、技术和优点。
另外,存储器阵列可以包括N沟道、P沟道和/或这两类晶体管以及部分耗尽和/或完全耗尽型晶体管。例如,在存储器阵列外围的电路(例如感测放大器或比较器、行和列地址解码器以及线驱动器(这里未图示))可以包括完全耗尽型晶体管(无论P沟道和/或N沟道型)。可替代地,该电路可以包括部分耗尽型晶体管(无论P沟道和/或N沟道型)。有许多用以在同一衬底上集成部分耗尽和/或完全耗尽型晶体管的技术(例如参见Fazan等人于2004年2月18日提交且发明名称为“Semiconductor Device”的美国非临时专利申请No.10/487,157(美国专利申请公开号2004/0238890))。无论现在已知还是以后开发的所有这样的技术都将落入本发明的范围内。
值得注意的是,电浮置体晶体管14可以是对称或非对称器件。当晶体管14对称时,源极区和漏极区实质上可互换。然而当晶体管14是非对称器件时,晶体管14的源极区或漏极区具有不同的电特性、物理特性、掺杂浓度和/或掺杂分布特性。这样,非对称器件的源极区或漏极区通常不可互换。尽管如此,存储器单元的电浮置N沟道晶体管的漏极区(无论源极区和漏极区是否可互换)仍是连接到位线/感测放大器的晶体管的区域。
在此描述和图示了许多发明。尽管已经描述和图示了本发明的某些实施例、特征、属性和优点,但是应当理解本发明的许多其它以及不同和/或相似实施例、特征、属性和优点根据描述和图示是明显的。这样,这里描述和图示的本发明的实施例、特征、属性和优点并非穷举,而应当理解本发明这样的其它、相似以及不同实施例、特征、属性和优点在本发明的范围内。
例如,本发明的多个存储器单元12可以用例如具有多行和多列(例如矩阵形式)的任何存储器阵列来实施。可以用任何电浮置体存储器单元和存储器单元阵列来实施本发明。此外如上文提到的,可以用其它存储器单元和存储器阵列技术,例如1T-1C(一个晶体管、一个电容器)和电浮置栅极存储器单元来实施本发明。
值得注意的是,对于在编程操作过程中未写入的与非使能或未选字线相关联的那些未选存储器单元,可以施加或建立保持条件以防止、最小化或避免对未选存储器单元行的存储器单元的数据状态或这些存储器单元中存储的电荷的干扰。在这点上,可以向未选存储器单元行的存储器单元的栅极施加电压(例如-1.2V)以及可以向未选存储器单元行的存储器单元的源极区和漏极区施加电压(例如0V)以防止、最小化或避免在编程或写入操作过程中对未选存储器单元行的存储器单元中数据状态的干扰。在这些条件之下,对所选行的所选存储器单元的编程或写入并不影响(或基本上不影响)未选存储器单元行的存储器单元的数据状态(例如参见图15)。
另外,对于在读取操作过程中不读取的耦合到非使能或未选字线的那些存储器单元,可以施加或建立保持条件以防止、最小化或避免对阵列的未选存储器单元行的存储器单元中数据状态的干扰。在这点上,可以向未选存储器单元的栅极施加电压(例如-1.2V)以及可以向未选存储器单元行的存储器单元的源极区施加电压(例如0V)以防止、最小化或避免在读取操作过程中对未选存储器单元中数据状态的干扰。在这些条件之下,未选存储器单元行的存储器单元的状态在读取所选存储器单元行的所选存储器单元过程中不受影响(或基本上不受影响)(例如参见图16)。
如上所述,阵列的字长可以是一次可编程(例如在测试过程中、在设计过程中或在制造时编程)或多次可编程(例如在测试过程中、在启动/通电过程中、在初始化序列过程中和/或在操作过程中(在原处))。例如在一个实施例中,代表字长的数据可以存储于片上字长选择电路中(例如在驻留于器件上或集成于器件中的熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器和/或寄存器中)。片上字长选择电路可以整体地或部分地布置于集成电路器件的逻辑部分和/或外围部分中(例如参见图20A-20C)。
除此之外或取而代之,字长选择电路可以整体地或部分地位于片上(例如在熔断器或反熔断器或DRAM、SRAM、ROM、PROM、EPROM、EEPROM单元、锁存器和/或寄存器中),而对该字长选择电路编程的电路可以位于片外。在这点上,参照图21A-21C,可以经由位于或布置于外部控制器/处理器36(例如存储器控制器、微处理器和/或图形处理器)中的电路对(在这一实施例中在片上的)字长选择电路编程。外部控制器/处理器36可以实施于模块100(例如参见图21A)上、具有分布式总线结构的系统1000中(例如参见图21B)和/或具有点到点架构的系统1000中(例如参见图21C)。在各实施例中,控制器/处理器36可以向存储器器件50提供信息,该存储器器件50作为响应控制存储器器件50内阵列的字长。
例如,如上所述,用以实施读取和写入操作的所示/示例电压电平仅为举例。示出的电压电平可以是相对的或绝对的。可替代地,示出的电压可以是相对的,因为无论一个或多个电压(例如源极、漏极或栅极电压)变成或是正电压和负电压,例如可以将各电压电平增加或减少给定的电压量(例如可以将各电压增加或减少0.1、0.15、0.25、0.5、1伏特(或更多))。
另外,本发明的上述实施例仅为举例。它们并非旨在于穷举本发明或将本发明限制于公开的精确形式、技术、材料和/或配置。许多修改和变化根据这一公开是可能的。应理解在不脱离本发明的范围的情况下可以利用其它实施例以及可以做出操作上的改变。这样,本发明的范围并不唯一地限于以上描述,因为对上述实施例的描述是出于说明和描述的目的而呈现的。
应注意术语“电路”可以特别地意味着单个部件或多个部件(无论是集成电路形式还是别的形式),这些部件是有源的和/或无源的并且耦合在一起以提供或执行所需操作。术语“电路”可以特别地意味着电路(无论是否集成)或电路组(无论是否集成)。
术语“禁止”可以特别地意味着防止、妨碍、禁止和/或去使能。措词“感测”或类似措词例如意味着测量、采样、感测、检查、检测、监视和/或捕获。
Claims (31)
1.一种集成电路器件,包括:
存储器单元阵列,包括:
多个字线;
多个源极线;
多个位线;以及
按行和列的矩阵排列的多个存储器单元,其中各存储器单元包括电浮置体晶体管,其中所述电浮置体晶体管包括:
耦合到相关联的源极线的第一区域;
耦合到相关联的位线的第二区域;
布置于所述第一区域和所述第二区域之间的体区域,其中所述体区域是电浮置的;
布置于所述体区域之上并且耦合到相关联的字线的栅极;以及
其中每个存储器单元包括多个数据状态,所述多个数据状态包括:
(i)第一数据状态,代表所述电浮置体晶体管的所述体区域中的第一电荷;以及
(ii)第二数据状态,代表所述电浮置体晶体管的所述体区域中的第二电荷;
第一电路,耦合到第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行写操作:
(i)施加写入控制信号到所述第一行存储器单元的第一组存储器单元,以在各个所述第一组存储器单元中写入所述多个数据状态中的一个,以及
(ii)施加写入取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于其的写操作,且从而在写操作期间禁止在所述第二组存储器单元中写入所述多个数据状态中的任何一个。
2.根据权利要求1所述的集成电路器件,其中所述第一组存储器单元的存储器单元的数目对应于所述存储器单元阵列的字长。
3.根据权利要求2所述的集成电路器件,还包括用以存储代表所述字长的数据的字长选择电路。
4.根据权利要求1所述的集成电路器件,其中所述写入取消选择控制信号包括(i)向所述第二组存储器单元的每个存储器单元的所述栅极施加的第一随时间改变的信号、(ii)向所述第二组存储器单元的每个存储器单元的所述第一区域施加的第二随时间改变的信号和(iii)向所述第二组存储器单元的每个存储器单元的所述第二区域施加的第三随时间改变的信号。
5.根据权利要求4所述的集成电路器件,其中所述写入控制信号包括(i)向所述第一组存储器单元的每个存储器单元的所述栅极施加的所述第一随时间改变的信号、(ii)向所述第一组存储器单元的每个存储器单元的所述第一区域施加的所述第二随时间改变的信号和(iii)向所述第一组存储器单元的每个存储器单元的所述第二区域施加的第四随时间改变的信号。
6.根据权利要求1所述的集成电路器件,其中所述写入取消选择控制信号包括(i)向所述第二组存储器单元的每个存储器单元的栅极施加的第一随时间改变的信号、(ii)向所述第二组存储器单元的每个存储器单元的所述第一区域施加的第二随时间改变的信号和(iii)向所述第二组存储器单元的每个存储器单元的所述第二区域施加的具有恒定的电压幅度的第三信号。
7.根据权利要求6所述的集成电路器件,其中所述写入控制信号包括(i)向所述第一组存储器单元的每个存储器单元的栅极施加的所述第一随时间改变的信号、(ii)向所述第一组存储器单元的每个存储器单元的所述第一区域施加的所述第二随时间改变的信号和(iii)向所述第一组存储器单元的每个存储器单元的所述第二区域施加的第四随时间改变的信号。
8.根据权利要求1所述的集成电路器件,还包括:第二电路,耦合到所述第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行读取操作:(i)施加读取控制信号到所述第一行存储器单元的所述第一组存储器单元以读取所述第一组存储器单元的每个存储器单元的数据状态;以及(ii)施加读取取消选择控制信号到所述第一行存储器单元的所述第二组存储器单元,以禁止关于所述第一行存储器单元的第二组存储器单元的读取操作,且从而禁止在读取操作期间读取所述第二组存储器单元的每个存储器单元的数据状态。
9.根据权利要求8所述的集成电路器件,其中所述读取控制信号包括向所述第一组存储器单元的每个存储器单元的所述电浮置体晶体管的栅极施加的信号、向所述电浮置体晶体管的所述第一区域施加的信号和向所述电浮置体晶体管的所述第二区域施加的信号,以导致、强制和/或引起读取双极晶体管电流,所述读取双极晶体管电流代表所述第一行存储器单元的所述第一组存储器单元的每个存储器单元的数据状态。
10.根据权利要求9所述的集成电路器件,其中所述第二电路基于所述读取双极晶体管电流来确定所述存储器单元的数据状态。
11.根据权利要求9所述的集成电路器件,其中所述第二电路包括多个感测放大器。
12.根据权利要求1所述的集成电路器件,其中所述写入控制信号包括用以写入所述第一数据状态的控制信号,且其中响应于用以将所述第一数据状态写入所述第一行存储器单元的预定存储器单元的所述控制信号,所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管生成双极晶体管电流,该双极晶体管电流在所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管的所述体区域中提供所述第一电荷。
13.根据权利要求1所述的集成电路器件,其中每个所述存储器单元包括代表所述电浮置体晶体管的所述体区域中的第三电荷的第三数据状态。
14.根据权利要求1所述的集成电路器件,其中所述第一电路包括通过并行施加以下信号关于所述第一行存储器单元的存储器单元进行写操作的装置:
(i)施加写入控制信号到所述第一行存储器单元的第一组存储器单元,以在各个所述第一组存储器单元中写入所述多个数据状态中的一个,以及
(ii)施加写入取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于其的写操作,且从而在写操作期间禁止在所述第二组存储器单元中写入所述多个数据状态中的任何一个。
15.一种集成电路器件,包括:
半导体存储器阵列,包括:
多个字线;
多个源极线;
多个位线;以及
按行和列的矩阵排列的多个存储器单元,其中每个存储器单元包括电浮置体晶体管,其中所述电浮置体晶体管包括:
耦合到相关联的源极线的第一区域;
耦合到相关联的位线的第二区域;
布置于所述第一区域和所述第二区域之间的体区域,其中所述体区域是电浮置的;
布置于所述体区域之上并且耦合到相关联的字线的栅极;以及
其中每个存储器单元包括至少两个数据状态,所述至少两个数据状态包括:
(i)第一数据状态,代表相关联的电浮置体晶体管的所述体区域中的第一电荷;以及
(ii)第二数据状态,代表相关联的电浮置体晶体管的所述体区域中的第二电荷;
电路,耦合到第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行读取操作:
(i)施加读取控制信号到所述第一行存储器单元的第一组存储器单元,以读取所述第一组存储器单元的每个存储器单元的数据状态;以及
(ii)施加读取取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于所述第一行存储器单元的第二组存储器单元的读取操作,从而禁止在读取操作期间读取所述第二组存储器单元的每个存储器单元的数据状态。
16.根据权利要求15所述的集成电路器件,其中所述读取控制信号包括向所述第一组存储器单元的每个存储器单元的所述电浮置体晶体管的栅极施加的信号、向所述电浮置体晶体管的第一区域施加的信号和向所述电浮置体晶体管的第二区域施加的信号,以导致、强制和/或引起读取双极晶体管电流,所述读取双极晶体管电流代表所述第一行存储器单元的所述第一组存储器单元的每个存储器单元的数据状态。
17.根据权利要求15所述的集成电路器件,其中所述电路基于所述读取双极晶体管电流来确定所述存储器单元的数据状态。
18.根据权利要求15所述的集成电路器件,其中所述电路包括多个感测放大器。
19.根据权利要求15所述的集成电路器件,还包括:写入电路,耦合到所述第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行写操作:
(i)施加写入控制信号到所述第一行存储器单元的第一组存储器单元,以在各个所述第一组存储器单元中写入所述多个数据状态中的一个;以及
(ii)施加写入取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于其的写操作,且从而禁止在写操作期间在所述第二组存储器单元中写入所述多个数据状态中的任何一个,以及
其中所述写入控制信号包括用以写入所述第一数据状态的控制信号,且其中响应于用以将所述第一数据状态写入所述第一行存储器单元的预定存储器单元的所述控制信号,所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管生成双极晶体管电流,该双极晶体管电流在所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管的所述体区域中提供所述第一电荷。
20.根据权利要求15所述的集成电路器件,其中所述第一组存储器单元的存储器单元的数目对应于所述存储器单元阵列的字长。
21.根据权利要求20所述的集成电路器件,还包括用以存储代表所述字长的数据的字长选择电路。
22.根据权利要求15所述的集成电路器件,其中所述电路包括通过并行施加以下信号关于所述第一行存储器单元的存储器单元进行读取操作的装置:
(i)施加读取控制信号到所述第一行存储器单元的第一组存储器单元,以读取所述第一组存储器单元的每个存储器单元的数据状态;以及
(ii)施加读取取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于所述第一行存储器单元的第二组存储器单元的读取操作,从而禁止在读取操作期间读取所述第二组存储器单元的每个存储器单元的数据状态。
23.一种集成电路器件,包括:
半导体存储器阵列,布置于半导体区或层中或半导体区或层上,所述半导体区或层驻留在衬底的绝缘区或层上或所述绝缘区或层以上,所述半导体存储器阵列包括:
多个字线;
多个源极线;
多个位线;以及
多个动态随机存取存储器单元,布置于所述半导体区或层中或半导体区或层上,并且按行和列的矩阵排列,每个动态随机存取存储器单元包括至少一个晶体管,所述晶体管具有:
耦合到相关联的源极线的第一区域;
耦合到相关联的位线的第二区域;
布置于所述第一区域和所述第二区域之间的体区域,其中所述体区域是电浮置的;
布置于所述体区域之上并且耦合到相关联的字线的栅极;以及
其中每个存储器单元包括至少两个数据状态,所述至少两个数据状态包括:
(i)第一数据状态,代表相关联的电浮置体晶体管的所述体区域中的第一电荷;以及
(ii)第二数据状态,代表相关联的电浮置体晶体管的所述体区域中的第二电荷;
第一电路,耦合到第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行写操作:
(i)施加写入控制信号到所述第一行存储器单元的第一组存储器单元,以在各个所述第一组存储器单元中写入所述多个数据状态中的一个;以及
(ii)施加写入取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于其的写操作,且从而禁止在写操作期间在所述第二组存储器单元中写入所述多个数据状态中的任何一个;以及
第二电路,耦合到所述第一行存储器单元的每个存储器单元,以通过并行施加以下信号来关于所述第一行存储器单元的存储器单元进行读操作:
(i)施加读取控制信号到所述第一行存储器单元的所述第一组存储器单元,以读取所述第一组存储器单元的每个存储器单元的数据状态;以及
(ii)施加读取取消选择控制信号到所述第一行存储器单元的所述第二组存储器单元,以禁止关于其的读取操作,且从而禁止在读取操作期间读取所述第二组存储器单元的每个存储器单元的数据状态。
24.根据权利要求23所述的集成电路器件,其中所述读取控制信号包括向所述第一组存储器单元的每个存储器单元的所述电浮置体晶体管的所述栅极施加的信号、向所述电浮置体晶体管的所述第一区域施加的信号和向所述电浮置体晶体管的所述第二区域施加的信号,以导致、强制和/或引起读取双极晶体管电流,所述读取双极晶体管电流代表所述第一行存储器单元的所述第一组存储器单元的每个存储器单元的数据状态。
25.根据权利要求23所述的集成电路器件,其中所述第二电路基于所述读取双极晶体管电流来确定所述存储器单元的数据状态。
26.根据权利要求23所述的集成电路器件,其中所述第二电路包括多个感测放大器。
27.根据权利要求23所述的集成电路器件,其中所述写入控制信号包括用以写入所述第一数据状态的控制信号,且其中响应于用以将所述第一数据状态写入所述第一行存储器单元的预定存储器单元的所述控制信号,所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管生成双极晶体管电流,该双极晶体管电流在所述第一行存储器单元的所述预定存储器单元的所述电浮置体晶体管的所述体区域中提供所述第一电荷。
28.根据权利要求23所述的集成电路器件,其中每个所述存储器单元包括代表所述电浮置体晶体管的所述体区域中的第三电荷的第三数据状态。
29.根据权利要求23所述的集成电路器件,其中所述第一组存储器单元的存储器单元的数目对应于所述存储器单元阵列的字长。
30.根据权利要求29所述的集成电路器件,还包括用以存储代表所述字长的数据的字长选择电路。
31.根据权利要求23所述的集成电路器件,其中:
所述第一电路包括通过并行施加以下信号关于所述第一行存储器单元的存储器单元进行写操作的装置:
(i)施加写入控制信号到所述第一行存储器单元的第一组存储器单元,以在各个所述第一组存储器单元中写入所述多个数据状态中的一个,以及
(ii)施加写入取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于其的写操作,且从而在写操作期间禁止在所述第二组存储器单元中写入所述多个数据状态中的任何一个;以及
所述第二电路包括通过并行施加以下信号关于所述第一行存储器单元的存储器单元进行读取操作的装置:
(i)施加读取控制信号到所述第一行存储器单元的第一组存储器单元,以读取所述第一组存储器单元的每个存储器单元的数据状态;以及
(ii)施加读取取消选择控制信号到所述第一行存储器单元的第二组存储器单元,以禁止关于所述第一行存储器单元的第二组存储器单元的读取操作,从而禁止在读取操作期间读取所述第二组存储器单元的每个存储器单元的数据状态。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US79011106P | 2006-04-07 | 2006-04-07 | |
US60/790,111 | 2006-04-07 | ||
US11/724,552 | 2007-03-15 | ||
US11/724,552 US7492632B2 (en) | 2006-04-07 | 2007-03-15 | Memory array having a programmable word length, and method of operating same |
PCT/US2007/007591 WO2007126830A2 (en) | 2006-04-07 | 2007-03-29 | Memory array having a programmable word length, and method of operating same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101395551A CN101395551A (zh) | 2009-03-25 |
CN101395551B true CN101395551B (zh) | 2013-01-16 |
Family
ID=38656025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800071344A Active CN101395551B (zh) | 2006-04-07 | 2007-03-29 | 具有可编程字长的存储器阵列及其操作方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US7492632B2 (zh) |
CN (1) | CN101395551B (zh) |
WO (1) | WO2007126830A2 (zh) |
Families Citing this family (250)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070277849A1 (en) | 2006-06-06 | 2007-12-06 | Shah Ketan N | Method of neutralizing a stain on a surface |
US7606066B2 (en) * | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
US7492632B2 (en) * | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
WO2007128738A1 (en) * | 2006-05-02 | 2007-11-15 | Innovative Silicon Sa | Semiconductor memory cell and array using punch-through to program and read same |
US8069377B2 (en) | 2006-06-26 | 2011-11-29 | Micron Technology, Inc. | Integrated circuit having memory array including ECC and column redundancy and method of operating the same |
US7542340B2 (en) * | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
US7733707B2 (en) * | 2006-07-21 | 2010-06-08 | Hynix Semiconductor Inc. | 1-transistor type DRAM cell, DRAM device and DRAM comprising thereof and driving method thereof and manufacturing method thereof |
KR101277402B1 (ko) | 2007-01-26 | 2013-06-20 | 마이크론 테크놀로지, 인코포레이티드 | 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 dram 트랜지스터 |
WO2009031052A2 (en) * | 2007-03-29 | 2009-03-12 | Innovative Silicon S.A. | Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor |
US7688660B2 (en) * | 2007-04-12 | 2010-03-30 | Qimonda Ag | Semiconductor device, an electronic device and a method for operating the same |
US8064274B2 (en) | 2007-05-30 | 2011-11-22 | Micron Technology, Inc. | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same |
US8085594B2 (en) | 2007-06-01 | 2011-12-27 | Micron Technology, Inc. | Reading technique for memory cell with electrically floating body transistor |
US7652910B2 (en) * | 2007-06-30 | 2010-01-26 | Intel Corporation | Floating body memory array |
US20090016118A1 (en) * | 2007-07-12 | 2009-01-15 | Silicon Storage Technology, Inc. | Non-volatile dram with floating gate and method of operation |
US7969808B2 (en) * | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
KR20090116088A (ko) * | 2008-05-06 | 2009-11-11 | 삼성전자주식회사 | 정보 유지 능력과 동작 특성이 향상된 커패시터리스 1t반도체 메모리 소자 |
US8194487B2 (en) | 2007-09-17 | 2012-06-05 | Micron Technology, Inc. | Refreshing data of memory cells with electrically floating body transistors |
KR101308048B1 (ko) * | 2007-10-10 | 2013-09-12 | 삼성전자주식회사 | 반도체 메모리 장치 |
US8536628B2 (en) | 2007-11-29 | 2013-09-17 | Micron Technology, Inc. | Integrated circuit having memory cell array including barriers, and method of manufacturing same |
US8349662B2 (en) * | 2007-12-11 | 2013-01-08 | Micron Technology, Inc. | Integrated circuit having memory cell array, and method of manufacturing same |
KR20090075063A (ko) * | 2008-01-03 | 2009-07-08 | 삼성전자주식회사 | 플로팅 바디 트랜지스터를 이용한 동적 메모리 셀을 가지는메모리 셀 어레이를 구비하는 반도체 메모리 장치 및 이장치의 동작 방법 |
US8773933B2 (en) | 2012-03-16 | 2014-07-08 | Micron Technology, Inc. | Techniques for accessing memory cells |
US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
US8189376B2 (en) * | 2008-02-08 | 2012-05-29 | Micron Technology, Inc. | Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same |
US7957206B2 (en) * | 2008-04-04 | 2011-06-07 | Micron Technology, Inc. | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same |
US7947543B2 (en) | 2008-09-25 | 2011-05-24 | Micron Technology, Inc. | Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation |
US7933140B2 (en) * | 2008-10-02 | 2011-04-26 | Micron Technology, Inc. | Techniques for reducing a voltage swing |
KR20100038975A (ko) * | 2008-10-07 | 2010-04-15 | 삼성전자주식회사 | 커패시터 없는 디램 소자 |
US7924630B2 (en) * | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
US8223574B2 (en) * | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
US8213226B2 (en) | 2008-12-05 | 2012-07-03 | Micron Technology, Inc. | Vertical transistor memory cell and array |
KR20100070158A (ko) * | 2008-12-17 | 2010-06-25 | 삼성전자주식회사 | 커패시터가 없는 동작 메모리 셀을 구비한 반도체 메모리 장치 및 이 장치의 동작 방법 |
KR101442177B1 (ko) | 2008-12-18 | 2014-09-18 | 삼성전자주식회사 | 커패시터 없는 1-트랜지스터 메모리 셀을 갖는 반도체소자의 제조방법들 |
US8319294B2 (en) * | 2009-02-18 | 2012-11-27 | Micron Technology, Inc. | Techniques for providing a source line plane |
US8710566B2 (en) | 2009-03-04 | 2014-04-29 | Micron Technology, Inc. | Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device |
CN102365628B (zh) * | 2009-03-31 | 2015-05-20 | 美光科技公司 | 用于提供半导体存储器装置的技术 |
US8373439B2 (en) | 2009-04-14 | 2013-02-12 | Monolithic 3D Inc. | 3D semiconductor device |
US20110031997A1 (en) * | 2009-04-14 | 2011-02-10 | NuPGA Corporation | Method for fabrication of a semiconductor device and structure |
US8362482B2 (en) * | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US7986042B2 (en) | 2009-04-14 | 2011-07-26 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8427200B2 (en) | 2009-04-14 | 2013-04-23 | Monolithic 3D Inc. | 3D semiconductor device |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8384426B2 (en) | 2009-04-14 | 2013-02-26 | Monolithic 3D Inc. | Semiconductor device and structure |
KR101080200B1 (ko) * | 2009-04-14 | 2011-11-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 리프레쉬 제어 방법 |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8258810B2 (en) | 2010-09-30 | 2012-09-04 | Monolithic 3D Inc. | 3D semiconductor device |
US9711407B2 (en) * | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US8378715B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8754533B2 (en) * | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US8405420B2 (en) * | 2009-04-14 | 2013-03-26 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US8362800B2 (en) | 2010-10-13 | 2013-01-29 | Monolithic 3D Inc. | 3D semiconductor device including field repairable logics |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
US8508994B2 (en) | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
US8498157B2 (en) | 2009-05-22 | 2013-07-30 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
US8537610B2 (en) | 2009-07-10 | 2013-09-17 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
US9076543B2 (en) | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
US8199595B2 (en) * | 2009-09-04 | 2012-06-12 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8294159B2 (en) | 2009-10-12 | 2012-10-23 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US8476145B2 (en) | 2010-10-13 | 2013-07-02 | Monolithic 3D Inc. | Method of fabricating a semiconductor device and structure |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US8174881B2 (en) | 2009-11-24 | 2012-05-08 | Micron Technology, Inc. | Techniques for reducing disturbance in a semiconductor device |
US8310893B2 (en) * | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
US8416636B2 (en) * | 2010-02-12 | 2013-04-09 | Micron Technology, Inc. | Techniques for controlling a semiconductor memory device |
US8298875B1 (en) | 2011-03-06 | 2012-10-30 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US8373230B1 (en) | 2010-10-13 | 2013-02-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8026521B1 (en) | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
US8411513B2 (en) * | 2010-03-04 | 2013-04-02 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device having hierarchical bit lines |
US8576631B2 (en) * | 2010-03-04 | 2013-11-05 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
US8369177B2 (en) * | 2010-03-05 | 2013-02-05 | Micron Technology, Inc. | Techniques for reading from and/or writing to a semiconductor memory device |
US8547738B2 (en) | 2010-03-15 | 2013-10-01 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
US8411524B2 (en) | 2010-05-06 | 2013-04-02 | Micron Technology, Inc. | Techniques for refreshing a semiconductor memory device |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US8163581B1 (en) | 2010-10-13 | 2012-04-24 | Monolith IC 3D | Semiconductor and optoelectronic devices |
US8273610B2 (en) | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US8114757B1 (en) | 2010-10-11 | 2012-02-14 | Monolithic 3D Inc. | Semiconductor device and structure |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US8379458B1 (en) | 2010-10-13 | 2013-02-19 | Monolithic 3D Inc. | Semiconductor device and structure |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US8283215B2 (en) | 2010-10-13 | 2012-10-09 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8531878B2 (en) | 2011-05-17 | 2013-09-10 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
US9559216B2 (en) | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
KR101832934B1 (ko) | 2012-01-27 | 2018-02-28 | 삼성전자주식회사 | 비휘발성 메모리 장치, 그것을 포함하는 메모리 시스템, 그것의 블록 관리 방법, 프로그램 방법 및 소거 방법 |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US9059292B2 (en) | 2012-08-02 | 2015-06-16 | International Business Machines Corporation | Source and drain doping profile control employing carbon-doped semiconductor material |
US8841188B2 (en) | 2012-09-06 | 2014-09-23 | International Business Machines Corporation | Bulk finFET with controlled fin height and high-K liner |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11961827B1 (en) | 2012-12-22 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US8674470B1 (en) | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11967583B2 (en) | 2012-12-22 | 2024-04-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
WO2017053329A1 (en) | 2015-09-21 | 2017-03-30 | Monolithic 3D Inc | 3d semiconductor device and structure |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US9728539B2 (en) * | 2015-12-08 | 2017-08-08 | Korea Advanced Institute Of Science And Technology | Multi bit capacitorless DRAM and manufacturing method thereof |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US10762948B2 (en) * | 2016-12-09 | 2020-09-01 | Rambus Inc. | Floating body DRAM with reduced access energy |
US10366763B2 (en) * | 2017-10-31 | 2019-07-30 | Micron Technology, Inc. | Block read count voltage adjustment |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1469482A (zh) * | 2002-06-18 | 2004-01-21 | ��ʽ���綫֥ | 半导体存储器件 |
CN1490820A (zh) * | 2002-09-11 | 2004-04-21 | ��ʽ���綫֥ | 半导体存储器件 |
CN1725498A (zh) * | 2000-08-17 | 2006-01-25 | 株式会社东芝 | 半导体存储装置 |
Family Cites Families (302)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA272437A (en) | 1925-10-22 | 1927-07-19 | Edgar Lilienfeld Julius | Electric current control mechanism |
US3439214A (en) | 1968-03-04 | 1969-04-15 | Fairchild Camera Instr Co | Beam-junction scan converter |
US4032947A (en) | 1971-10-20 | 1977-06-28 | Siemens Aktiengesellschaft | Controllable charge-coupled semiconductor device |
IT979035B (it) | 1972-04-25 | 1974-09-30 | Ibm | Dispositivo a circuito integrato per la memorizzazione di informa zioni binarie ad emissione elettro luminescente |
FR2197494A5 (zh) | 1972-08-25 | 1974-03-22 | Radiotechnique Compelec | |
US3997799A (en) | 1975-09-15 | 1976-12-14 | Baker Roger T | Semiconductor-device for the storage of binary data |
JPS5567993A (en) | 1978-11-14 | 1980-05-22 | Fujitsu Ltd | Semiconductor memory unit |
US4250569A (en) | 1978-11-15 | 1981-02-10 | Fujitsu Limited | Semiconductor memory device |
DE3065928D1 (en) | 1979-01-25 | 1984-01-26 | Nec Corp | Semiconductor memory device |
JPS55113359A (en) | 1979-02-22 | 1980-09-01 | Fujitsu Ltd | Semiconductor integrated circuit device |
DE3067215D1 (en) | 1979-12-13 | 1984-04-26 | Fujitsu Ltd | Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell |
JPS5742161A (en) | 1980-08-28 | 1982-03-09 | Fujitsu Ltd | Semiconductor and production thereof |
JPS5982761A (ja) | 1982-11-04 | 1984-05-12 | Hitachi Ltd | 半導体メモリ |
JPS6070760A (ja) | 1983-09-27 | 1985-04-22 | Fujitsu Ltd | 半導体記憶装置 |
US4658377A (en) | 1984-07-26 | 1987-04-14 | Texas Instruments Incorporated | Dynamic memory array with segmented bit lines |
JPS6177359A (ja) | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | 半導体記憶装置 |
JPS61280651A (ja) | 1985-05-24 | 1986-12-11 | Fujitsu Ltd | 半導体記憶装置 |
JPH0671067B2 (ja) | 1985-11-20 | 1994-09-07 | 株式会社日立製作所 | 半導体装置 |
JPS62272561A (ja) | 1986-05-20 | 1987-11-26 | Seiko Epson Corp | 1トランジスタ型メモリセル |
JPS6319847A (ja) | 1986-07-14 | 1988-01-27 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
US4807195A (en) | 1987-05-18 | 1989-02-21 | International Business Machines Corporation | Apparatus and method for providing a dual sense amplifier with divided bit line isolation |
US4816884A (en) | 1987-07-20 | 1989-03-28 | International Business Machines Corporation | High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor |
JP2582794B2 (ja) | 1987-08-10 | 1997-02-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5677867A (en) | 1991-06-12 | 1997-10-14 | Hazani; Emanuel | Memory with isolatable expandable bit lines |
DE68926793T2 (de) | 1988-03-15 | 1997-01-09 | Toshiba Kawasaki Kk | Dynamischer RAM |
FR2629941B1 (fr) | 1988-04-12 | 1991-01-18 | Commissariat Energie Atomique | Memoire et cellule memoire statiques du type mis, procede de memorisation |
JPH0666443B2 (ja) | 1988-07-07 | 1994-08-24 | 株式会社東芝 | 半導体メモリセルおよび半導体メモリ |
US4910709A (en) | 1988-08-10 | 1990-03-20 | International Business Machines Corporation | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell |
US5164805A (en) | 1988-08-22 | 1992-11-17 | Massachusetts Institute Of Technology | Near-intrinsic thin-film SOI FETS |
US5144390A (en) | 1988-09-02 | 1992-09-01 | Texas Instruments Incorporated | Silicon-on insulator transistor with internal body node to source node connection |
US5258635A (en) | 1988-09-06 | 1993-11-02 | Kabushiki Kaisha Toshiba | MOS-type semiconductor integrated circuit device |
JPH02168496A (ja) | 1988-09-14 | 1990-06-28 | Kawasaki Steel Corp | 半導体メモリ回路 |
NL8802423A (nl) | 1988-10-03 | 1990-05-01 | Imec Inter Uni Micro Electr | Werkwijze voor het bedrijven van een mos-structuur en daarvoor geschikte mos-structuur. |
US4894697A (en) | 1988-10-31 | 1990-01-16 | International Business Machines Corporation | Ultra dense dram cell and its method of fabrication |
US5010524A (en) | 1989-04-20 | 1991-04-23 | International Business Machines Corporation | Crosstalk-shielded-bit-line dram |
US5366917A (en) | 1990-03-20 | 1994-11-22 | Nec Corporation | Method for fabricating polycrystalline silicon having micro roughness on the surface |
US5024993A (en) | 1990-05-02 | 1991-06-18 | Microelectronics & Computer Technology Corporation | Superconducting-semiconducting circuits, devices and systems |
US5313432A (en) | 1990-05-23 | 1994-05-17 | Texas Instruments Incorporated | Segmented, multiple-decoder memory array and method for programming a memory array |
JPH07123145B2 (ja) | 1990-06-27 | 1995-12-25 | 株式会社東芝 | 半導体集積回路 |
EP0465961B1 (en) | 1990-07-09 | 1995-08-09 | Sony Corporation | Semiconductor device on a dielectric isolated substrate |
JPH04176163A (ja) | 1990-11-08 | 1992-06-23 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5331197A (en) | 1991-04-23 | 1994-07-19 | Canon Kabushiki Kaisha | Semiconductor memory device including gate electrode sandwiching a channel region |
US5424567A (en) | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
US5515383A (en) | 1991-05-28 | 1996-05-07 | The Boeing Company | Built-in self-test system and method for self test of an integrated circuit |
US5355330A (en) | 1991-08-29 | 1994-10-11 | Hitachi, Ltd. | Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode |
EP0537677B1 (en) | 1991-10-16 | 1998-08-19 | Sony Corporation | Method of forming an SOI structure with a DRAM |
US5526307A (en) | 1992-01-22 | 1996-06-11 | Macronix International Co., Ltd. | Flash EPROM integrated circuit architecture |
US5397726A (en) | 1992-02-04 | 1995-03-14 | National Semiconductor Corporation | Segment-erasable flash EPROM |
DE69328743T2 (de) | 1992-03-30 | 2000-09-07 | Mitsubishi Electric Corp | Halbleiteranordnung |
US5528062A (en) | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
US5315541A (en) | 1992-07-24 | 1994-05-24 | Sundisk Corporation | Segmented column memory array |
EP0599388B1 (en) | 1992-11-20 | 2000-08-02 | Koninklijke Philips Electronics N.V. | Semiconductor device provided with a programmable element |
JPH06216338A (ja) | 1992-11-27 | 1994-08-05 | Internatl Business Mach Corp <Ibm> | 半導体メモリセル及びその製造方法 |
JPH0799251A (ja) | 1992-12-10 | 1995-04-11 | Sony Corp | 半導体メモリセル |
EP0606758B1 (en) | 1992-12-30 | 2000-09-06 | Samsung Electronics Co., Ltd. | Method of producing an SOI transistor DRAM |
US5986914A (en) | 1993-03-31 | 1999-11-16 | Stmicroelectronics, Inc. | Active hierarchical bitline memory architecture |
JP3613594B2 (ja) | 1993-08-19 | 2005-01-26 | 株式会社ルネサステクノロジ | 半導体素子およびこれを用いた半導体記憶装置 |
EP0655788B1 (en) | 1993-11-29 | 1998-01-21 | STMicroelectronics S.A. | A volatile memory cell |
US5448513A (en) | 1993-12-02 | 1995-09-05 | Regents Of The University Of California | Capacitorless DRAM device on silicon-on-insulator substrate |
US5432730A (en) | 1993-12-20 | 1995-07-11 | Waferscale Integration, Inc. | Electrically programmable read only memory array |
US5489792A (en) | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
US5446299A (en) | 1994-04-29 | 1995-08-29 | International Business Machines Corporation | Semiconductor random access memory cell on silicon-on-insulator with dual control gates |
JP3273582B2 (ja) | 1994-05-13 | 2002-04-08 | キヤノン株式会社 | 記憶装置 |
JPH0832040A (ja) | 1994-07-14 | 1996-02-02 | Nec Corp | 半導体装置 |
US5583808A (en) | 1994-09-16 | 1996-12-10 | National Semiconductor Corporation | EPROM array segmented for high performance and method for controlling same |
JP3304635B2 (ja) | 1994-09-26 | 2002-07-22 | 三菱電機株式会社 | 半導体記憶装置 |
US5627092A (en) | 1994-09-26 | 1997-05-06 | Siemens Aktiengesellschaft | Deep trench dram process on SOI for low leakage DRAM cell |
US5593912A (en) | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
FR2726935B1 (fr) | 1994-11-10 | 1996-12-13 | Commissariat Energie Atomique | Dispositif a memoire non-volatile electriquement effacable et procede de realisation d'un tel dispositif |
JP3315293B2 (ja) | 1995-01-05 | 2002-08-19 | 株式会社東芝 | 半導体記憶装置 |
JP3274306B2 (ja) | 1995-01-20 | 2002-04-15 | 株式会社東芝 | 半導体集積回路装置 |
US6292424B1 (en) | 1995-01-20 | 2001-09-18 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
JP2806286B2 (ja) | 1995-02-07 | 1998-09-30 | 日本電気株式会社 | 半導体装置 |
JP3407232B2 (ja) | 1995-02-08 | 2003-05-19 | 富士通株式会社 | 半導体記憶装置及びその動作方法 |
JPH08222648A (ja) | 1995-02-14 | 1996-08-30 | Canon Inc | 記憶装置 |
EP0727820B1 (en) | 1995-02-17 | 2004-03-24 | Hitachi, Ltd. | Semiconductor memory device and method of manufacturing the same |
JP3600335B2 (ja) | 1995-03-27 | 2004-12-15 | 株式会社東芝 | 半導体装置 |
US5568356A (en) | 1995-04-18 | 1996-10-22 | Hughes Aircraft Company | Stacked module assembly including electrically interconnected switching module and plural electronic modules |
DE69632098T2 (de) | 1995-04-21 | 2005-03-24 | Nippon Telegraph And Telephone Corp. | MOSFET Schaltung und ihre Anwendung in einer CMOS Logikschaltung |
US5606188A (en) | 1995-04-26 | 1997-02-25 | International Business Machines Corporation | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory |
JP2848272B2 (ja) | 1995-05-12 | 1999-01-20 | 日本電気株式会社 | 半導体記憶装置 |
DE19519159C2 (de) | 1995-05-24 | 1998-07-09 | Siemens Ag | DRAM-Zellenanordnung und Verfahren zu deren Herstellung |
US5629546A (en) | 1995-06-21 | 1997-05-13 | Micron Technology, Inc. | Static memory cell and method of manufacturing a static memory cell |
US6480407B1 (en) | 1995-08-25 | 2002-11-12 | Micron Technology, Inc. | Reduced area sense amplifier isolation layout in a dynamic RAM architecture |
JP3853406B2 (ja) | 1995-10-27 | 2006-12-06 | エルピーダメモリ株式会社 | 半導体集積回路装置及び当該装置の製造方法 |
US5585285A (en) | 1995-12-06 | 1996-12-17 | Micron Technology, Inc. | Method of forming dynamic random access memory circuitry using SOI and isolation trenches |
DE19603810C1 (de) | 1996-02-02 | 1997-08-28 | Siemens Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
JP3759648B2 (ja) | 1996-03-04 | 2006-03-29 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US5936265A (en) | 1996-03-25 | 1999-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device including a tunnel effect element |
WO1997038444A1 (en) | 1996-04-08 | 1997-10-16 | Hitachi, Ltd. | Semiconductor integrated circuit device |
EP0801427A3 (en) | 1996-04-11 | 1999-05-06 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor, semiconductor storage device, method of manufacturing the same and method of driving semiconductor storage device |
US6424016B1 (en) | 1996-05-24 | 2002-07-23 | Texas Instruments Incorporated | SOI DRAM having P-doped polysilicon gate for a memory pass transistor |
US5754469A (en) | 1996-06-14 | 1998-05-19 | Macronix International Co., Ltd. | Page mode floating gate memory device storing multiple bits per cell |
US5886376A (en) | 1996-07-01 | 1999-03-23 | International Business Machines Corporation | EEPROM having coplanar on-insulator FET and control gate |
US5778243A (en) | 1996-07-03 | 1998-07-07 | International Business Machines Corporation | Multi-threaded cell for a memory |
US5811283A (en) | 1996-08-13 | 1998-09-22 | United Microelectronics Corporation | Silicon on insulator (SOI) dram cell structure and process |
JP3260660B2 (ja) | 1996-08-22 | 2002-02-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
US5774411A (en) | 1996-09-12 | 1998-06-30 | International Business Machines Corporation | Methods to enhance SOI SRAM cell stability |
US5798968A (en) | 1996-09-24 | 1998-08-25 | Sandisk Corporation | Plane decode/virtual sector architecture |
JP2877103B2 (ja) | 1996-10-21 | 1999-03-31 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
US6097624A (en) | 1997-09-17 | 2000-08-01 | Samsung Electronics Co., Ltd. | Methods of operating ferroelectric memory devices having reconfigurable bit lines |
KR19980057003A (ko) | 1996-12-30 | 1998-09-25 | 김영환 | 반도체 메모리 디바이스 및 그 제조방법 |
JP3161354B2 (ja) | 1997-02-07 | 2001-04-25 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5732014A (en) | 1997-02-20 | 1998-03-24 | Micron Technology, Inc. | Merged transistor structure for gain memory cell |
EP0860878A2 (en) | 1997-02-20 | 1998-08-26 | Texas Instruments Incorporated | An integrated circuit with programmable elements |
JP3441330B2 (ja) * | 1997-02-28 | 2003-09-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH11191596A (ja) | 1997-04-02 | 1999-07-13 | Sony Corp | 半導体メモリセル及びその製造方法 |
US6424011B1 (en) | 1997-04-14 | 2002-07-23 | International Business Machines Corporation | Mixed memory integration with NVRAM, dram and sram cell structures on same substrate |
US5881010A (en) | 1997-05-15 | 1999-03-09 | Stmicroelectronics, Inc. | Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation |
KR100554112B1 (ko) | 1997-05-30 | 2006-02-20 | 미크론 테크놀로지,인코포레이티드 | 256 메가 다이내믹 랜덤 액세스 메모리 |
US5784311A (en) | 1997-06-13 | 1998-07-21 | International Business Machines Corporation | Two-device memory cell on SOI for merged logic and memory applications |
US6133597A (en) | 1997-07-25 | 2000-10-17 | Mosel Vitelic Corporation | Biasing an integrated circuit well with a transistor electrode |
KR100246602B1 (ko) | 1997-07-31 | 2000-03-15 | 정선종 | 모스트랜지스터및그제조방법 |
US5907170A (en) | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US5943581A (en) | 1997-11-05 | 1999-08-24 | Vanguard International Semiconductor Corporation | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits |
US5976945A (en) | 1997-11-20 | 1999-11-02 | Vanguard International Semiconductor Corporation | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor |
JPH11163329A (ja) | 1997-11-27 | 1999-06-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE19752968C1 (de) | 1997-11-28 | 1999-06-24 | Siemens Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
DE59814170D1 (de) | 1997-12-17 | 2008-04-03 | Qimonda Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
US5943258A (en) | 1997-12-24 | 1999-08-24 | Texas Instruments Incorporated | Memory with storage cells having SOI drive and access transistors with tied floating body connections |
JP4199338B2 (ja) | 1998-10-02 | 2008-12-17 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6097056A (en) | 1998-04-28 | 2000-08-01 | International Business Machines Corporation | Field effect transistor having a floating gate |
US6225158B1 (en) | 1998-05-28 | 2001-05-01 | International Business Machines Corporation | Trench storage dynamic random access memory cell with vertical transfer device |
TW432545B (en) | 1998-08-07 | 2001-05-01 | Ibm | Method and improved SOI body contact structure for transistors |
JP4030198B2 (ja) | 1998-08-11 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
KR100268419B1 (ko) | 1998-08-14 | 2000-10-16 | 윤종용 | 고집적 반도체 메모리 장치 및 그의 제조 방법 |
US6333866B1 (en) | 1998-09-28 | 2001-12-25 | Texas Instruments Incorporated | Semiconductor device array having dense memory cell array and heirarchical bit line scheme |
US6423596B1 (en) | 1998-09-29 | 2002-07-23 | Texas Instruments Incorporated | Method for two-sided fabrication of a memory array |
US6096598A (en) | 1998-10-29 | 2000-08-01 | International Business Machines Corporation | Method for forming pillar memory cells and device formed thereby |
US6214694B1 (en) | 1998-11-17 | 2001-04-10 | International Business Machines Corporation | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
KR100290787B1 (ko) | 1998-12-26 | 2001-07-12 | 박종섭 | 반도체 메모리 소자의 제조방법 |
US6184091B1 (en) | 1999-02-01 | 2001-02-06 | Infineon Technologies North America Corp. | Formation of controlled trench top isolation layers for vertical transistors |
JP3384350B2 (ja) | 1999-03-01 | 2003-03-10 | 株式会社村田製作所 | 低温焼結セラミック組成物の製造方法 |
US20030220716A1 (en) * | 1999-03-12 | 2003-11-27 | Pharmix Corporation | Method and apparatus for automated design of chemical synthesis routes |
US6157216A (en) | 1999-04-22 | 2000-12-05 | International Business Machines Corporation | Circuit driver on SOI for merged logic and memory circuits |
US6111778A (en) | 1999-05-10 | 2000-08-29 | International Business Machines Corporation | Body contacted dynamic memory |
US6333532B1 (en) | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP2001036092A (ja) | 1999-07-23 | 2001-02-09 | Mitsubishi Electric Corp | 半導体装置 |
JP2001044391A (ja) | 1999-07-29 | 2001-02-16 | Fujitsu Ltd | 半導体記憶装置とその製造方法 |
US6566177B1 (en) | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
US6391658B1 (en) | 1999-10-26 | 2002-05-21 | International Business Machines Corporation | Formation of arrays of microelectronic elements |
JP2001180633A (ja) | 1999-12-27 | 2001-07-03 | Toshiba Tec Corp | ラベルプリンタ |
US6633066B1 (en) | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6544837B1 (en) | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
US6359802B1 (en) | 2000-03-28 | 2002-03-19 | Intel Corporation | One-transistor and one-capacitor DRAM cell for logic process technology |
US6524897B1 (en) | 2000-03-31 | 2003-02-25 | Intel Corporation | Semiconductor-on-insulator resistor-capacitor circuit |
US20020031909A1 (en) | 2000-05-11 | 2002-03-14 | Cyril Cabral | Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets |
JP2002064150A (ja) | 2000-06-05 | 2002-02-28 | Mitsubishi Electric Corp | 半導体装置 |
DE10028424C2 (de) | 2000-06-06 | 2002-09-19 | Infineon Technologies Ag | Herstellungsverfahren für DRAM-Speicherzellen |
US6262935B1 (en) | 2000-06-17 | 2001-07-17 | United Memories, Inc. | Shift redundancy scheme for wordlines in memory circuits |
US6479862B1 (en) | 2000-06-22 | 2002-11-12 | Progressant Technologies, Inc. | Charge trapping device and method for implementing a transistor having a negative differential resistance mode |
JP2002009081A (ja) | 2000-06-26 | 2002-01-11 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4011833B2 (ja) | 2000-06-30 | 2007-11-21 | 株式会社東芝 | 半導体メモリ |
KR100339425B1 (ko) | 2000-07-21 | 2002-06-03 | 박종섭 | 리세스된 소이 구조를 갖는 반도체 소자 및 그의 제조 방법 |
JP4226205B2 (ja) | 2000-08-11 | 2009-02-18 | 富士雄 舛岡 | 半導体記憶装置の製造方法 |
US6621725B2 (en) | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
US6492211B1 (en) | 2000-09-07 | 2002-12-10 | International Business Machines Corporation | Method for novel SOI DRAM BICMOS NPN |
US20020070411A1 (en) * | 2000-09-08 | 2002-06-13 | Alcatel | Method of processing a high voltage p++/n-well junction and a device manufactured by the method |
JP4064607B2 (ja) | 2000-09-08 | 2008-03-19 | 株式会社東芝 | 半導体メモリ装置 |
JP2002094027A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 半導体記憶装置とその製造方法 |
US6350653B1 (en) | 2000-10-12 | 2002-02-26 | International Business Machines Corporation | Embedded DRAM on silicon-on-insulator substrate |
US6421269B1 (en) | 2000-10-17 | 2002-07-16 | Intel Corporation | Low-leakage MOS planar capacitors for use within DRAM storage cells |
US6496402B1 (en) * | 2000-10-17 | 2002-12-17 | Intel Corporation | Noise suppression for open bit line DRAM architectures |
US6849871B2 (en) * | 2000-10-20 | 2005-02-01 | International Business Machines Corporation | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS |
US6429477B1 (en) | 2000-10-31 | 2002-08-06 | International Business Machines Corporation | Shared body and diffusion contact structure and method for fabricating same |
US6440872B1 (en) | 2000-11-03 | 2002-08-27 | International Business Machines Corporation | Method for hybrid DRAM cell utilizing confined strap isolation |
US6549450B1 (en) | 2000-11-08 | 2003-04-15 | Ibm Corporation | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system |
US6441436B1 (en) | 2000-11-29 | 2002-08-27 | United Microelectronics Corp. | SOI device and method of fabrication |
JP3808700B2 (ja) | 2000-12-06 | 2006-08-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20020072155A1 (en) * | 2000-12-08 | 2002-06-13 | Chih-Cheng Liu | Method of fabricating a DRAM unit |
US7101772B2 (en) * | 2000-12-30 | 2006-09-05 | Texas Instruments Incorporated | Means for forming SOI |
US6552398B2 (en) | 2001-01-16 | 2003-04-22 | Ibm Corporation | T-Ram array having a planar cell structure and method for fabricating the same |
US6441435B1 (en) | 2001-01-31 | 2002-08-27 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
JP4216483B2 (ja) | 2001-02-15 | 2009-01-28 | 株式会社東芝 | 半導体メモリ装置 |
JP3884266B2 (ja) | 2001-02-19 | 2007-02-21 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
US6620682B1 (en) * | 2001-02-27 | 2003-09-16 | Aplus Flash Technology, Inc. | Set of three level concurrent word line bias conditions for a nor type flash memory array |
US6548848B2 (en) | 2001-03-15 | 2003-04-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP4354663B2 (ja) | 2001-03-15 | 2009-10-28 | 株式会社東芝 | 半導体メモリ装置 |
JP4071476B2 (ja) * | 2001-03-21 | 2008-04-02 | 株式会社東芝 | 半導体ウェーハ及び半導体ウェーハの製造方法 |
US7456439B1 (en) | 2001-03-22 | 2008-11-25 | T-Ram Semiconductor, Inc. | Vertical thyristor-based memory with trench isolation and its method of fabrication |
US6462359B1 (en) | 2001-03-22 | 2002-10-08 | T-Ram, Inc. | Stability in thyristor-based memory device |
TW544911B (en) | 2001-04-26 | 2003-08-01 | Toshiba Corp | Semiconductor device |
JP4053738B2 (ja) | 2001-04-26 | 2008-02-27 | 株式会社東芝 | 半導体メモリ装置 |
US6556477B2 (en) | 2001-05-21 | 2003-04-29 | Ibm Corporation | Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same |
US6563733B2 (en) | 2001-05-24 | 2003-05-13 | Winbond Electronics Corporation | Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell |
TWI230392B (en) | 2001-06-18 | 2005-04-01 | Innovative Silicon Sa | Semiconductor device |
US6573566B2 (en) | 2001-07-09 | 2003-06-03 | United Microelectronics Corp. | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
JP2003031684A (ja) | 2001-07-11 | 2003-01-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2003031693A (ja) | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
US6552935B2 (en) * | 2001-08-02 | 2003-04-22 | Stmicroelectronics, Inc. | Dual bank flash memory device and method |
JP2003132682A (ja) | 2001-08-17 | 2003-05-09 | Toshiba Corp | 半導体メモリ装置 |
EP1288955A3 (en) | 2001-08-17 | 2004-09-22 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US6664589B2 (en) | 2001-08-30 | 2003-12-16 | Micron Technology, Inc. | Technique to control tunneling currents in DRAM capacitors, cells, and devices |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US6552932B1 (en) | 2001-09-21 | 2003-04-22 | Sandisk Corporation | Segmented metal bitlines |
JP3984014B2 (ja) * | 2001-09-26 | 2007-09-26 | 株式会社東芝 | 半導体装置用基板を製造する方法および半導体装置用基板 |
JP4322453B2 (ja) | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6870225B2 (en) | 2001-11-02 | 2005-03-22 | International Business Machines Corporation | Transistor structure with thick recessed source/drain structures and fabrication process of same |
US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6518105B1 (en) | 2001-12-10 | 2003-02-11 | Taiwan Semiconductor Manufacturing Company | High performance PD SOI tunneling-biased MOSFET |
JP3998467B2 (ja) | 2001-12-17 | 2007-10-24 | シャープ株式会社 | 不揮発性半導体メモリ装置及びその動作方法 |
JP2003203967A (ja) | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分soiウェーハの製造方法、半導体装置及びその製造方法 |
US20030123279A1 (en) * | 2002-01-03 | 2003-07-03 | International Business Machines Corporation | Silicon-on-insulator SRAM cells with increased stability and yield |
US20030230778A1 (en) | 2002-01-30 | 2003-12-18 | Sumitomo Mitsubishi Silicon Corporation | SOI structure having a SiGe Layer interposed between the silicon and the insulator |
US6975536B2 (en) | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US6750515B2 (en) | 2002-02-05 | 2004-06-15 | Industrial Technology Research Institute | SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection |
DE10204871A1 (de) | 2002-02-06 | 2003-08-21 | Infineon Technologies Ag | Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren |
JP2003243528A (ja) | 2002-02-13 | 2003-08-29 | Toshiba Corp | 半導体装置 |
US6686624B2 (en) | 2002-03-11 | 2004-02-03 | Monolithic System Technology, Inc. | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
US6661042B2 (en) | 2002-03-11 | 2003-12-09 | Monolithic System Technology, Inc. | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
US6560142B1 (en) | 2002-03-22 | 2003-05-06 | Yoshiyuki Ando | Capacitorless DRAM gain cell |
US20050177280A1 (en) * | 2002-03-22 | 2005-08-11 | Morphochem Aktiengesellschaft Fur Kombinatorische Chemie | Methods and systems for discovery of chemical compounds and their syntheses |
US6677646B2 (en) | 2002-04-05 | 2004-01-13 | International Business Machines Corporation | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS |
JP4880867B2 (ja) * | 2002-04-10 | 2012-02-22 | セイコーインスツル株式会社 | 薄膜メモリ、アレイとその動作方法および製造方法 |
EP1355316B1 (en) | 2002-04-18 | 2007-02-21 | Innovative Silicon SA | Data storage device and refreshing method for use with such device |
US6574135B1 (en) | 2002-04-19 | 2003-06-03 | Texas Instruments Incorporated | Shared sense amplifier for ferro-electric memory cell |
US6940748B2 (en) | 2002-05-16 | 2005-09-06 | Micron Technology, Inc. | Stacked 1T-nMTJ MRAM structure |
JP3962638B2 (ja) | 2002-06-18 | 2007-08-22 | 株式会社東芝 | 半導体記憶装置、及び、半導体装置 |
KR100437856B1 (ko) | 2002-08-05 | 2004-06-30 | 삼성전자주식회사 | 모스 트랜지스터 및 이를 포함하는 반도체 장치의 형성방법. |
US6861689B2 (en) * | 2002-11-08 | 2005-03-01 | Freescale Semiconductor, Inc. | One transistor DRAM cell structure and method for forming |
US7030436B2 (en) * | 2002-12-04 | 2006-04-18 | Micron Technology, Inc. | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means |
DE10306281B4 (de) | 2003-02-14 | 2007-02-15 | Infineon Technologies Ag | Anordnung und Verfahren zur Herstellung von vertikalen Transistorzellen und transistorgesteuerten Speicherzellen |
US6714436B1 (en) * | 2003-03-20 | 2004-03-30 | Motorola, Inc. | Write operation for capacitorless RAM |
US7233024B2 (en) | 2003-03-31 | 2007-06-19 | Sandisk 3D Llc | Three-dimensional memory device incorporating segmented bit line memory array |
US6867433B2 (en) | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
JP2004335553A (ja) | 2003-04-30 | 2004-11-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3913709B2 (ja) | 2003-05-09 | 2007-05-09 | 株式会社東芝 | 半導体記憶装置 |
JP2004335031A (ja) | 2003-05-09 | 2004-11-25 | Toshiba Corp | 半導体記憶装置 |
US7085153B2 (en) | 2003-05-13 | 2006-08-01 | Innovative Silicon S.A. | Semiconductor memory cell, array, architecture and device, and method of operating same |
US6912150B2 (en) * | 2003-05-13 | 2005-06-28 | Lionel Portman | Reference current generator, and method of programming, adjusting and/or operating same |
US20040228168A1 (en) | 2003-05-13 | 2004-11-18 | Richard Ferrant | Semiconductor memory device and method of operating same |
US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7335934B2 (en) | 2003-07-22 | 2008-02-26 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
JP4077381B2 (ja) | 2003-08-29 | 2008-04-16 | 株式会社東芝 | 半導体集積回路装置 |
US6936508B2 (en) | 2003-09-12 | 2005-08-30 | Texas Instruments Incorporated | Metal gate MOS transistors and methods for making the same |
US20050062088A1 (en) * | 2003-09-22 | 2005-03-24 | Texas Instruments Incorporated | Multi-gate one-transistor dynamic random access memory |
US7184298B2 (en) * | 2003-09-24 | 2007-02-27 | Innovative Silicon S.A. | Low power programming technique for a floating body memory transistor, memory cell, and memory array |
US6982902B2 (en) | 2003-10-03 | 2006-01-03 | Infineon Technologies Ag | MRAM array having a segmented bit line |
US7072205B2 (en) * | 2003-11-19 | 2006-07-04 | Intel Corporation | Floating-body DRAM with two-phase write |
US7002842B2 (en) * | 2003-11-26 | 2006-02-21 | Intel Corporation | Floating-body dynamic random access memory with purge line |
JP2005175090A (ja) | 2003-12-09 | 2005-06-30 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
US6952376B2 (en) * | 2003-12-22 | 2005-10-04 | Intel Corporation | Method and apparatus to generate a reference value in a memory array |
JP4559728B2 (ja) * | 2003-12-26 | 2010-10-13 | 株式会社東芝 | 半導体記憶装置 |
US6903984B1 (en) * | 2003-12-31 | 2005-06-07 | Intel Corporation | Floating-body DRAM using write word line for increased retention time |
US7001811B2 (en) | 2003-12-31 | 2006-02-21 | Intel Corporation | Method for making memory cell without halo implant |
US6992339B2 (en) | 2003-12-31 | 2006-01-31 | Intel Corporation | Asymmetric memory cell |
JP4342970B2 (ja) | 2004-02-02 | 2009-10-14 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
JP4028499B2 (ja) | 2004-03-01 | 2007-12-26 | 株式会社東芝 | 半導体記憶装置 |
JP4032039B2 (ja) | 2004-04-06 | 2008-01-16 | 株式会社東芝 | 半導体記憶装置 |
JP4110115B2 (ja) | 2004-04-15 | 2008-07-02 | 株式会社東芝 | 半導体記憶装置 |
JP2005346755A (ja) | 2004-05-31 | 2005-12-15 | Sharp Corp | 半導体記憶装置 |
US7042765B2 (en) | 2004-08-06 | 2006-05-09 | Freescale Semiconductor, Inc. | Memory bit line segment isolation |
JP3898715B2 (ja) | 2004-09-09 | 2007-03-28 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7061806B2 (en) * | 2004-09-30 | 2006-06-13 | Intel Corporation | Floating-body memory cell write |
US7611943B2 (en) | 2004-10-20 | 2009-11-03 | Texas Instruments Incorporated | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
US7476939B2 (en) * | 2004-11-04 | 2009-01-13 | Innovative Silicon Isi Sa | Memory cell having an electrically floating body transistor and programming technique therefor |
US7251164B2 (en) * | 2004-11-10 | 2007-07-31 | Innovative Silicon S.A. | Circuitry for and method of improving statistical distribution of integrated circuits |
US7301838B2 (en) * | 2004-12-13 | 2007-11-27 | Innovative Silicon S.A. | Sense amplifier circuitry and architecture to write data into and/or read from memory cells |
US7301803B2 (en) * | 2004-12-22 | 2007-11-27 | Innovative Silicon S.A. | Bipolar reading technique for a memory cell having an electrically floating body transistor |
CN100562987C (zh) | 2005-02-18 | 2009-11-25 | 富士通微电子株式会社 | 存储单元阵列及其制造方法以及使用该存储单元阵列的半导体电路装置 |
US7563701B2 (en) | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7538389B2 (en) | 2005-06-08 | 2009-05-26 | Micron Technology, Inc. | Capacitorless DRAM on bulk silicon |
US7230846B2 (en) | 2005-06-14 | 2007-06-12 | Intel Corporation | Purge-based floating body memory |
US7317641B2 (en) | 2005-06-20 | 2008-01-08 | Sandisk Corporation | Volatile memory cell two-pass writing method |
US20070023833A1 (en) * | 2005-07-28 | 2007-02-01 | Serguei Okhonin | Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same |
US7511332B2 (en) | 2005-08-29 | 2009-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical flash memory |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7606066B2 (en) * | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
US7355916B2 (en) * | 2005-09-19 | 2008-04-08 | Innovative Silicon S.A. | Method and circuitry to generate a reference current for reading a memory cell, and device implementing same |
US20070085140A1 (en) | 2005-10-19 | 2007-04-19 | Cedric Bassin | One transistor memory cell having strained electrically floating body region, and method of operating same |
US7436706B2 (en) | 2005-10-31 | 2008-10-14 | Gregory Allan Popoff | Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same |
KR100724560B1 (ko) | 2005-11-18 | 2007-06-04 | 삼성전자주식회사 | 결정질 반도체층을 갖는 반도체소자, 그의 제조방법 및그의 구동방법 |
US7687851B2 (en) | 2005-11-23 | 2010-03-30 | M-Mos Semiconductor Sdn. Bhd. | High density trench MOSFET with reduced on-resistance |
JP2007157296A (ja) | 2005-12-08 | 2007-06-21 | Toshiba Corp | 半導体記憶装置 |
KR100675297B1 (ko) | 2005-12-19 | 2007-01-29 | 삼성전자주식회사 | 캐패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치 및 이 장치의 배치 방법 |
US7683430B2 (en) * | 2005-12-19 | 2010-03-23 | Innovative Silicon Isi Sa | Electrically floating body memory cell and array, and method of operating or controlling same |
US8022482B2 (en) | 2006-02-14 | 2011-09-20 | Alpha & Omega Semiconductor, Ltd | Device configuration of asymmetrical DMOSFET with schottky barrier source |
US7542345B2 (en) | 2006-02-16 | 2009-06-02 | Innovative Silicon Isi Sa | Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same |
DE102006009225B4 (de) | 2006-02-28 | 2009-07-16 | Advanced Micro Devices, Inc., Sunnyvale | Herstellung von Silizidoberflächen für Silizium/Kohlenstoff-Source/Drain-Gebiete |
US7492632B2 (en) * | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
US7324387B1 (en) | 2006-04-18 | 2008-01-29 | Maxim Integrated Products, Inc. | Low power high density random access memory flash cells and arrays |
DE102006019935B4 (de) | 2006-04-28 | 2011-01-13 | Advanced Micro Devices, Inc., Sunnyvale | SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung |
JP5068035B2 (ja) | 2006-05-11 | 2012-11-07 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7542340B2 (en) | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
US7545694B2 (en) | 2006-08-16 | 2009-06-09 | Cypress Semiconductor Corporation | Sense amplifier with leakage testing and read debug capability |
US7359226B2 (en) | 2006-08-28 | 2008-04-15 | Qimonda Ag | Transistor, memory cell array and method for forming and operating a memory device |
US7553709B2 (en) | 2006-10-04 | 2009-06-30 | International Business Machines Corporation | MOSFET with body contacts |
KR100819552B1 (ko) | 2006-10-30 | 2008-04-07 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 동작 방법 |
US7608898B2 (en) | 2006-10-31 | 2009-10-27 | Freescale Semiconductor, Inc. | One transistor DRAM cell structure |
JP2008117489A (ja) | 2006-11-07 | 2008-05-22 | Toshiba Corp | 半導体記憶装置 |
US7675781B2 (en) | 2006-12-01 | 2010-03-09 | Infineon Technologies Ag | Memory device, method for operating a memory device, and apparatus for use with a memory device |
US7688660B2 (en) | 2007-04-12 | 2010-03-30 | Qimonda Ag | Semiconductor device, an electronic device and a method for operating the same |
US20080258206A1 (en) | 2007-04-17 | 2008-10-23 | Qimonda Ag | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same |
EP2015362A1 (en) | 2007-06-04 | 2009-01-14 | STMicroelectronics (Crolles 2) SAS | Semiconductor array and manufacturing method thereof |
JP2009032384A (ja) | 2007-06-29 | 2009-02-12 | Toshiba Corp | 半導体記憶装置の駆動方法および半導体記憶装置 |
FR2919112A1 (fr) | 2007-07-16 | 2009-01-23 | St Microelectronics Crolles 2 | Circuit integre comprenant un transistor et un condensateur et procede de fabrication |
US7927938B2 (en) | 2007-11-19 | 2011-04-19 | Micron Technology, Inc. | Fin-JFET |
US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
US7924630B2 (en) * | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
US8223574B2 (en) * | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
-
2007
- 2007-03-15 US US11/724,552 patent/US7492632B2/en active Active
- 2007-03-29 WO PCT/US2007/007591 patent/WO2007126830A2/en active Application Filing
- 2007-03-29 CN CN2007800071344A patent/CN101395551B/zh active Active
-
2009
- 2009-02-13 US US12/371,551 patent/US7940559B2/en active Active
-
2011
- 2011-05-09 US US13/103,511 patent/US8134867B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1725498A (zh) * | 2000-08-17 | 2006-01-25 | 株式会社东芝 | 半导体存储装置 |
CN1469482A (zh) * | 2002-06-18 | 2004-01-21 | ��ʽ���綫֥ | 半导体存储器件 |
CN1490820A (zh) * | 2002-09-11 | 2004-04-21 | ��ʽ���綫֥ | 半导体存储器件 |
Also Published As
Publication number | Publication date |
---|---|
US7492632B2 (en) | 2009-02-17 |
US20070285982A1 (en) | 2007-12-13 |
CN101395551A (zh) | 2009-03-25 |
US8134867B2 (en) | 2012-03-13 |
US7940559B2 (en) | 2011-05-10 |
US20090141550A1 (en) | 2009-06-04 |
WO2007126830A3 (en) | 2008-06-26 |
WO2007126830A9 (en) | 2009-01-15 |
US20110273942A1 (en) | 2011-11-10 |
WO2007126830A2 (en) | 2007-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101395551B (zh) | 具有可编程字长的存储器阵列及其操作方法 | |
CN101233576B (zh) | 具有电浮置体晶体管的存储器单元和存储器单元阵列及其操作方法 | |
US11769550B2 (en) | Systems and methods for reducing standby power in floating body memory devices | |
US8325515B2 (en) | Integrated circuit device | |
US7683430B2 (en) | Electrically floating body memory cell and array, and method of operating or controlling same | |
US20070187775A1 (en) | Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same | |
US8797819B2 (en) | Refreshing data of memory cells with electrically floating body transistors | |
US20050093064A1 (en) | Semiconductor integrated circuit device | |
US7933142B2 (en) | Semiconductor memory cell and array using punch-through to program and read same | |
US9257155B2 (en) | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same | |
US20070090413A1 (en) | Nonvolatile ferroelectric memory device and method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: MICRON TECHNOLOGY, INC. Free format text: FORMER OWNER: INNOVATIVE SILICON ISI SA Effective date: 20110802 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20110802 Address after: Idaho Applicant after: Micron Technology, INC. Address before: Lausanne Applicant before: Innovative Silicon Isi SA |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |