CN101410973A - 晶片级芯片尺寸封装及其制造和使用方法 - Google Patents

晶片级芯片尺寸封装及其制造和使用方法 Download PDF

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Publication number
CN101410973A
CN101410973A CNA2004800199895A CN200480019989A CN101410973A CN 101410973 A CN101410973 A CN 101410973A CN A2004800199895 A CNA2004800199895 A CN A2004800199895A CN 200480019989 A CN200480019989 A CN 200480019989A CN 101410973 A CN101410973 A CN 101410973A
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chip
substrate
salient point
encapsulation
insulating barrier
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CN101410973B (zh
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雷吉夫·乔什
吴宗麟
李相道
崔伦华
朴敏孝
金志奂
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QUICK KOREA SEMICONDUCTOR CO Ltd
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QUICK KOREA SEMICONDUCTOR CO Ltd
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Priority claimed from US10/618,113 external-priority patent/US20050176233A1/en
Priority claimed from US10/731,453 external-priority patent/US20040191955A1/en
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H—ELECTRICITY
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

描述了第一、第二和第三封装的半导体器件(晶片级芯片尺寸封装)。第一封装的半导体器件在芯片焊垫和RDL图案之间不包含UBM。第一器件仅包含在RDL图案和焊接凸点之间的单一非聚合物绝缘层，其中绝缘层不需高温固化工艺并因此在器件中不诱发热应力。提供消除芯片焊垫和RDL图案之间的UBM减小了第一器件的制造成本。第二封装的半导体器件(第二晶片级芯片尺寸封装)包含粘结膜，所述粘结膜包含夹在具有Cu基柱凸点的芯片和包含结合焊垫的衬底之间的导电颗粒。某些导电颗粒夹在柱凸点和结合焊垫之间以产生导电路径。在没有分配焊料和回流焊料的步骤的情况下制造第二器件，且第二器件可选地消除了再分布迹线的使用。使用这样的配置增加了第二晶片级芯片封装的可靠性。第三封装的半导体器件(第三晶片级芯片尺寸封装)包含导电粘结材料作为半导体管芯和构图的导电衬底之间的电互连路径。构图的导电衬底不仅充当衬底，而且还作为将管芯的紧密的焊垫布局转化为电路板中焊料球的较大的阵列配置的再分布层。使用本方法允许形成的较低价格的芯片尺寸封装，该封装克服了在管芯尺寸封装中所使用的管芯尺寸的限制，以及提供印刷电路板可以获得的输入输出图案。于是，对于任何小管芯，本发明可以提供相似于印刷电路板的节距。

Description

晶片级芯片尺寸封装及其制造和使用方法
技术领域
本发明总体涉及一种制造集成电路(IC)和半导体器件以及所得结构的方法。具体而言，本发明涉及半导体封装及制造和使用该封装的方法。更具体而言，本发明涉及晶片级芯片尺寸封装及制造和使用该封装的方法。
背景技术
电子产业中特别是对于个人计算机(PC)、移动电话和个人数字助理(PDA)的最新进展已经激发了人们对于可以迅速处理大量数据的轻、紧凑、多功能且强有力的系统的需求。这些进展还已经引起了半导体芯片和用于这些芯片的封装的尺寸的减小。
半导体芯片通常具有形成于包含IC的硅衬底的顶表面的导电焊垫。使用引线键合来将衬底上的导电焊垫连接到封装衬底上的相应的焊垫。IC中的电路的复杂性增加需要导电焊垫形成得彼此更接近。随着结合焊垫变窄，(引线键合中)引线的长度需要更长且宽度更窄，这不幸地导致了更大的电感量，且由此减小了电路的速度。
最近使用的一类封装是晶片级芯片尺寸封装(WLCSP)。例如，参见美国专利No.6187615和6287893，其公开的内容被引入于此作为参考。
一般地，为了制造WLCSP，处理晶片，且通过光刻工艺和溅射工艺来封装晶片。该方法比使用管芯键合、引线键合和模制的一般封装工艺更容易。与一般封装工艺相比，WLCSP的工艺还具有其他优点。首先，可以同时形成用于形成于晶片上的所有芯片的焊接凸点。第二，在WLCSP工艺期间对每个半导体芯片的操作进行晶片级测试是可能的。由于这些和其他原因，可以比一般封装以更低的成本来制造WLCSP。
图1-3示出了几个公知的晶片级芯片尺寸封装。如图1所示，在硅衬底5上芯片焊垫40由比如铝的金属形成。形成钝化层10来暴露硅衬底5上的每个芯片焊垫40的部分，同时保护硅衬底5的剩余部分。在钝化层10上方形成第一绝缘层15，然后在第一绝缘层15的部分和暴露的芯片焊垫40上方形成再分布线(RDL)图案20(其再分布从结合焊垫40到焊接凸点35的电信号)。在部分的RDL图案20上形成第二绝缘层25，同时留下暴露的部分的RDL图案20。在焊接凸点35和RDL图案20之间形成凸点下金属(UBM)30。RDL图案20包含接近芯片焊垫40的第一绝缘层15上的倾斜部分。在这些区域中，短路可能发生，且图案20可能由于应力而在这些区域中裂开和变形。
如图2所示，封装50包含RDL图案54，RDL图案54附着到圆柱带状的焊料连接52。这样的配置具有几个缺点。首先，RDL图案54和焊料连接52之间的接触区域是最小的，由此恶化了它们之间的电特性。第二，在RDL图案54和焊料连接52之间的接触表面中由于应力可能产生短路。第三，将与形成于芯片焊垫56上的焊接凸点58相连接的焊料连接52暴露于封装50的外部，即空气。于是，存在水汽渗透入焊料连接52的较高的可能性，且减小了焊料连接52的可靠性。第四，只有通过进行许多工艺步骤才能完成封装50，因此制造成本高。
如图3所示，封装70包含RDL图案76，其通过连接凸点74与芯片焊垫72电连接。但是，RDL图案在连接凸点74上倾斜，如上所述那样由于应力而导致裂纹。而且，连接凸点74由镀覆工艺制成且由铝、铜、银或其合金形成。因此，封装60不易制造。
对于常规WLCSP还存在其他问题。通常，这样的封装使用UMB(即，图1中的层30)和两层绝缘层(即，图1中的层15和25)，所述绝缘层由聚合物材料制成，比如聚酰亚胺和苯并环丁烯(BCB)。因为使用的材料和设备，这样的结构制造复杂且非常昂贵，而且，各层之间的热膨胀系数(CTE)可以在IC中诱发热应力，且在这些聚合物材料的高温固化期间损伤IC。
而且，常规的封装方法在倒装片封装中使用了导电膜或导电膏。例如，参见美国专利No.5,9494,142、6,509,634和6,518,097，其公开的内容引入于此作为参考。一般地，这些方法使用了硅管芯上的金凸点，且然后使用超声结合凭借导电膜或导电膏将其结合到衬底(通常陶瓷)。但是这样的方法具有高成本和低可靠性的缺点。
另外，包括WLCSP的半导体封装的趋势是使用更小、更轻和更薄的形状因子，这样的形状因子能够制造更小的半导体器件。但是，在具有小管芯和大量I/O的WLCSP封装中使用较小的形状因子可以引起制造困难。这些困难之一是将管芯501上的焊料球(即，小节距)与印刷电路板502上的焊盘(lands)/焊垫(即，大节距)对准，如图31所示。
发明内容
本发明提供了一种封装的半导体器件(晶片级芯片尺寸封装)，所述器件在芯片焊垫和RDL图案之间没有包含UBM。所述器件包含RDL图案和焊接凸点之间的单一的非聚合物绝缘层，在那里绝缘层不需要高温固化工艺且因此不会在器件中诱发热应力。通过消除芯片焊垫和RDL图案之间的UBM，减小了所述器件的制造成本。
本发明还提供了一种封装的半导体器件(晶片级芯片尺寸封装)，所述器件包含粘结膜，所述粘结膜包含夹在具有Cu基的柱凸点的芯片和包含结合焊垫的衬底之间的导电颗粒。某些导电颗粒夹在柱凸点和结合焊垫之间以产生导电通路。所述器件在没有分配焊料和回流焊料的步骤下被制造，且可以可选地消除使用再分布迹线。使用这样的配置增加了第二晶片级芯片尺寸封装的可靠性。
本发明还提供了一种封装的半导体器件(晶片级芯片尺寸封装)，所述器件包含导电粘结材料作为半导体管芯和构图的导电衬底之间的电互连路径。构图的导电衬底不仅充当衬底，而且作为将管芯的紧密的焊垫布局转化为电路板中焊料球的较大的阵列配置的再分布层。使用本发明允许形成克服了管芯尺寸芯片封装中使用的管芯尺寸的限制的较低价格的芯片尺寸封装，以及可以通过印刷电路板来获得的输入输出图案。于是，对于任何小的管芯，本发明可以提供相似于印刷电路板的节距(即，界面)。
附图说明
图1-39是根据本发明的器件和形成该器件的方法的一方面的视图，其中：
图1是常规晶片级芯片尺寸封装的横截面视图；
图2是另一常规晶片级芯片尺寸封装的横截面视图；
图3是另一常规晶片级芯片尺寸封装的横截面视图；
图4是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图5是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图6是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图7是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图8是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图9是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图10是显示根据本发明的一方面的晶片级芯片尺寸封装的制造方法中的一阶段的横截面图；
图11是根据本发明的一方面的晶片级芯片尺寸封装的横截面图；
图12-15示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的阶段；
图16绘制了本发明的一方面中的晶片级芯片尺寸封装的制造方法中的另一阶段；
图17绘制了在本发明的另一方面中的形成晶片级芯片尺寸封装的工艺；
图18-25示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的阶段；
图26绘制了本发明的一方面中可以使用的导电颗粒；
图27绘制了本发明的一方面中晶片级芯片尺寸封装；
图28显示本发明的一方面中晶片级芯片尺寸封装的制造方法中的阶段；
图29-30示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的阶段；
图31示出了常规的晶片级芯片尺寸封装的问题；
图32-33示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的阶段；
图34示出本发明的一方面中的部分的晶片级芯片尺寸封装；
图35-36示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的阶段；
图37示出本发明的一方面中的部分的晶片级芯片尺寸封装；
图38示出本发明的一方面中的晶片级芯片尺寸封装的制造方法中的一阶段；
图39示出了本发明的一方面中的晶片级芯片尺寸封装。
结合该说明书所呈现的图1-39仅是根据本发明特别而非完全的部分的器件和形成该器件的方法。与以下的描述一起，附图示出并说明了本发明的原理。在附图中，为了清晰起见夸大了层和区的厚度。还可以理解，当层被称为在另一层或基板“上”时，其可以直接在其他层或基板上，或中间层也可以存在。在不同的附图中相同的参考标号代表了相同的元件，且省略了它们的描述。
具体实施方式
参考附图现将在其后更加全面地描述本发明，在附图中示出了本发明的优选实施例。但是，本发明可以实现为许多的不同的形式且不应解释为限于这里阐述的实施例。而是，提供这些方面使得本公开充分和完整，且将本发明的构思传达给本领域的技术人员。虽然相对于IC芯片描述了本发明，但是本发明可以被用于需要封装的其他器件，即，硅MEMS器件、LCD显示器、光电子等。
图4到10示出了本发明的一个方面，用于制造包含再分布线(RDL)图案的晶片级芯片尺寸封装，该RDL图案在焊接凸点的底部和芯片焊垫的顶表面之间不倾斜。参考图4，制备衬底(或芯片)100，在衬底100上形成钝化层110和芯片焊垫115。衬底100可以是任何本领域中公知的半导体衬底，包括“化合物”半导体和单晶硅。钝化层110可以由本领域中公知的任何介电材料制成，比如氮化硅、氧化硅或SOG。
然后，在衬底100的上表面上形成芯片焊垫115。首先，通过常规的掩模和蚀刻工艺来去除该区域中的钝化层的部分。然后，覆盖沉积(blanketdeposit)用于芯片焊垫115的金属，且通过蚀刻和平面化来去除结合焊盘不需要的金属层的部分。芯片焊垫115可以由导电材料制成，比如金属和金属合金。在本发明的一个方面中，芯片焊垫包括铝。
接下来使用毛细管130将引线120贴附到芯片焊垫115。如图5中所示，将引线120的底部结合到芯片焊垫115。然后在预定的压力下执行模压工艺来压制引线120，由此形成模压的柱凸点125。通过使用毛细管130，可以采用简单的结构和简单的制造工艺来形成模压的柱凸点125。
如图6所示，然后沉积第一绝缘层135来覆盖模压的柱凸点125和钝化层110。在本发明的该方面中，第一绝缘层135由介电聚合物材料制成，比如BCB、聚酰亚胺(PI)、和环氧模制化合物(EMC)。如图7所示，使用常规的工艺来平面化第一绝缘层135和模压的柱凸点125。在平面化工艺中，形成柱凸点125’和第一绝缘层135’。在本发明的一方面中，使用化学机械抛光(CMP)工艺来平面化第一绝缘层135和柱凸点125。
如图8所示，在柱凸点125’和第一绝缘层135’上形成再分布线(RDL)图案140。RDL图案140电连接柱凸点125’和在随后的工艺期间形成的焊接凸点(如下述)。通过覆盖沉积金属层来形成该RDL图案，然后通常通过掩模和蚀刻来去除RDL图案140不需要的金属层的部分。RDL图案140可以包含任何导电材料，比如金属和金属合金。这样的金属和金属合金的实例包括Cu、Al、Cr、NiV和Ti。在本发明的一个方面中，RDL包括Cu、Al、Cr和Cu或选自NiV和Ti的材料的复合层。在图1所示的常规的晶片级芯片尺寸封装中，RDL图案20由依次在芯片焊垫40上沉积的Al、NiV、Cu、NiV和Cu形成。这样的配置具有差的粘结特性和可靠性，其不容易制造且具有高的制造成本。
如图9所示，然后形成第二绝缘层150来覆盖RDL图案140和第一绝缘层135’。通常通过掩模和蚀刻来去除部分的第二绝缘层150来暴露其后将贴附焊接凸点的部分的RDL图案140。如图10所示，然后将焊接凸点160贴附到RDL图案140的暴露的部分，如本领域中所公知的。柱凸点包括任何比如金属和金属合金的导电材料。在本发明的一方面中，柱凸点包括金(Au)或铜(Cu)。
在图10中示出了晶片级芯片尺寸封装1000。硅衬底100包括IC(未显示)和芯片焊垫115，芯片焊垫115延伸到钝化层110中且被钝化层110包围。将来自包含在衬底100的IC的电信号传输通过芯片焊垫115、RDL图案140到焊接凸点160，且然后到封装半导体器件的外部(即，到电路板)。
在图10的器件中，第一绝缘层135’包围和覆盖柱凸点125’。因为在本发明的该方面中第一绝缘层135’和柱凸点125’的顶表面是同平面的，所以RDL图案140可以形成为基本平面的层，而没有倾斜的部分。因此，防止由于应力引起的RDL图案中的裂纹。
图10所示的RDL图案140被示出为仅在部分的柱凸点125’的上表面上。在本发明的另一方面中，可以形成RDL图案来覆盖整个柱凸点125’，于是提高了晶片级芯片尺寸封装1000的电特性和可靠性。
在常规的晶片级芯片尺寸封装中，图1的RDL图案20包含倾斜的部分。因此，极难在图1中形成厚的第一绝缘层115。但是，在本发明的该方面中，图10中的第一绝缘层135’形成为厚层。
图11示出了本发明的另一方面，其中晶片级芯片尺寸封装具有两层RDL图案。晶片级芯片尺寸封装2000包含：衬底(或芯片)100；钝化层110；芯片焊垫115；柱凸点125’，形成于芯片焊垫115上且由第一绝缘层135’包围；中间RDL图案210，连接柱凸点125’和中间柱凸点220；中间绝缘层230，绝缘中间RDL图案210；RDL图案140，连接中间柱凸点220和焊接凸点160；第二绝缘层150，绝缘RDL图案140；和焊接凸点160，贴附到每个RDL图案140的部分。
图11中没有描述的组件与参考图10所说明的那些组件相同。图10和11中的相同参考标号指示相同的元件，所述元件具有基本相同功能，由相同的材料形成且以基本相同的形式形成。中间柱凸点220、中间RDL图案210和中间绝缘层230的结构、功能、材料和效果分别与柱凸点125、RDL图案140和第二绝缘层150基本相同。中间柱凸点220连接中间RDL图案210和RDL图案140。每个中间RDL图案210形成于每个中间柱凸点220的底部。中间绝缘层230暴露了部分的中间RDL图案210，从而其可以与中间柱凸点220连接。
在本发明另一方面，除图11所示的两层RDL图案外，可以形成附加的中间柱凸点、中间RDL图案和中间绝缘层来形成三(或更多)层RDL图案。
在上述的本发明的方面中，可以在焊接凸点和芯片焊垫之间减小或防止在本领域中的RDL图案的倾斜部分。这样的配置抑止了RDL图案中的裂纹，即使在下面的绝缘层具有大的厚度的情况。另外，可以使用毛细管来容易并便宜地形成柱凸点。
在本发明的另一方面中，以图12-17中描述的方式来制造晶片级芯片尺寸封装，以在芯片焊盘和RDL图案之间没有包含UBM且包含单一非聚合物绝缘层。在本发明的该方面，且如图17所示，首先再分布结合焊垫(如图12-15中更详细所示)。然后，在晶片上形成柱凸点(在图16中更详细所示)。然后直接或者通过使用焊料膏将焊料球贴附到柱凸点，且将焊料球回流。然后，得到的封装的半导体器件安装于电路板上，如本领域中公知的。
在本发明的该方面，且如图12-13中所示，获得了包含IC 305的衬底(或芯片)300(基本相似于衬底100)。然后在衬底300上形成钝化层310(基本相似于钝化层110)。然后去除部分的钝化层，且在该暴露的部分中形成芯片焊垫315(基本相似于芯片焊垫115)。用于这些工艺的方法基本相似于上述的方法。
接下来，如图14所示，直接在芯片焊垫315和钝化层310上形成再分布(RDL)图案340。RDL图案340电连接芯片焊垫315和在随后工艺器件形成的焊接凸点365(如下所述)。通过覆盖沉积金属层并然后通常通过掩模和蚀刻来去除RDL图案340不需要的部分的金属层，从而形成RDL图案340。RDL图案340可以包含任何的导电材料，比如金属和金属合金。这样的金属和金属合金的实例包括Cu、Al、Cr、NiV和Ti。在本发明的另一方面中，RDL图案包括Al。
接下来，如图15所示，形成绝缘层350来覆盖RDL图案340。在本发明的该方面，在RDL图案340上覆盖沉积用于绝缘层的材料。然后使用掩模和蚀刻工艺来去除区域375的区域中的该绝缘材料的部分(在那里将在后形成柱凸点365)。
用于绝缘层350的材料不包括如BCB、PI和EMC的聚合物材料。如上所述，在常规的WLCSP中通常使用如此的材料。但是，为了形成这样的层，将包含该材料的结构进行高温加热工艺。该加热对于固化聚合物材料是必须的。不幸的是，这样的高温加热工艺损伤了在聚合物材料下面包括衬底300中的IC 305的结构。
在本发明的该方面中，绝缘层350没有由聚合物材料制成。而是，绝缘层350由介电非聚合物材料制成。这样的非聚合物介电材料的实例包括氮化硅、氧化硅和氧氮化硅。通过本领域的任何公知的方法可以沉积如此的材料。
在本发明的该方面，仅使用了单层作为再分布层。在图4-10所示的本发明的该方面中，使用UBM和金属层将来自芯片焊垫115的电信号再分布到柱凸点160。在本发明的该方面通过仅使用金属层，可以消除UBM的制造成本。于是本发明的该方面仅使用单导电层作为WLCSP中的RDL图案。
如图16所示，然后在RDL图案340的暴露的部分上(在区域375中)形成柱凸点。采用如本领域所公知的覆层并通过电镀用于柱凸点的材料，可以形成柱凸点365A。在本发明的该方面，用于柱凸点的材料是Cu且覆层是Ni/Au合金。
或者，通过引线键合工艺可以形成柱凸点365B。在本发明的该方面，使用毛细管385将涂布的引线380贴附到RDL图案340。如图16所示，首先将引线380的底部结合到RDL图案340的金属。然后在预定的压力下执行压模工艺来压制引线380来形成压模的柱凸点365B。通过使用毛细管，可以采用简单的结构和简单的制造工艺来形成压制的柱凸点365B。在本发明的一个方面，用于引线的材料包括Cu且涂层包括Pd。
最后，如图17所示，然后直接或者通过使用焊料膏将焊料球贴附到柱凸点，且将焊料球回流。使用本领域公知的常规工艺来执行这些工艺。
在本发明的又一方面，以图18-30所示的方式来制造晶片级芯片尺寸封装。使用该工艺，消除了分配焊料和回流焊接凸点的步骤，且可选地消除再分布迹线的使用。在本发明的该方面，在芯片和衬底之间使用了粘结膜或膏。
在本发明的该方面，如图18-19所示，提供了包含IC 405的衬底(或芯片)400(基本相似于衬底100)。然后在芯片400上形成钝化层410(基本上相似于钝化层110)。然后去除部分的钝化层且在暴露的部分中形成芯片焊垫415(基本相似于芯片焊垫115)。用于这些工艺的方法基本相似于上述的方法。
接下来，如图20所示，再分布(RDL)图案440可选地直接形成于芯片焊垫415和钝化层410上。根据是否需要再分布，可以采用或不采用RDL图案440来形成半导体封装。当使用时，RDL图案440电连接芯片焊垫415和在随后的工艺期间形成的焊接凸点465(如下述)。通过覆盖沉积金属层并然后通常通过掩模和蚀刻来去除RDL图案440不需要的部分的金属层，从而形成RDL图案440。RDL图案440可以包含任何的导电材料，比如金属和金属合金。这样的金属和金属合金的实例包括Cu、Al、Cr、NiV和Ti。在本发明的另一方面中，RDL图案包括Al。
接下来，如图20所示，当使用RDL图案440时，形成绝缘层450来覆盖RDL图案440。在本发明的该方面，在RDL图案440上覆盖沉积用于绝缘层的材料。然后使用掩模和蚀刻工艺来去除区域475的区域中的该绝缘材料的部分(在那里将在后形成柱凸点465)。
用于绝缘层450的材料不包括如BCB、PI和EMC的聚合物材料。如上所述，在常规的WLCSP中通常使用如此的材料。但是，为了形成这样的层，将包含该材料的结构进行高温加热工艺。该加热对于固化聚合物材料是必须的。不幸的是，这样的高温加热工艺损伤了在聚合物材料下面包括衬底400中的IC 405的结构。
在本发明的该方面中，绝缘层450不是由聚合物材料制成。而是，绝缘层450由介电非聚合物材料制成。这样的非聚合物介电材料的实例包括氮化硅、氧化硅和氧氮化硅。
然后在图19中所示(没有再分布层)和图20中所示(具有再分布层)的结构上形成柱(或柱凸点)465。如图21和22所示，在芯片焊垫415和RDL图案440的暴露的部分(在区域475中)上分别形成柱465。采用如本领域所公知的覆层并通过电镀用于柱凸点的材料，可以形成柱凸点465。在本发明的一个方面，用于柱凸点的材料是Cu，且覆层是Pd。或者，通过如上所述的引线键合工艺可以形成柱凸点465。
接下来，如图23和24所示，将包含导电颗粒495的粘结层458施加到图21和22的结构。如这里所述，粘结层458贴附芯片400和衬底101，同时充当有限的导体。任何以该方式起作用的材料可以被用作粘结层458，包括具有在其中的导电颗粒的粘结材料。在本发明的一方面，粘结层458包括ACF(各向异性导电膜)、ACP(各向异性导电膏)或ICP(各向同性导电膏)。
使用本领域中的任何公知机制可以施加粘结层458。例如，当ACP被用作粘结剂时，可以通过丝网印刷来施加粘结层458。作为另一实例，当ACF被用作粘结剂时，通过膜贴附工艺可以施加层458。
导电颗粒459可以是本领域中的任何公知的，其可以与粘结材料一起使用。在图26中示出了在粘结层458中可以使用的导电颗粒的实例。导电颗粒459a包括具有由绝缘层包围的金属层的聚合物颗粒。导电颗粒459b包括由绝缘层包围的金属颗粒。当在柱凸点和衬底之间存在接触时，在导电颗粒中的绝缘层破裂，由此形成导电路径(如下述)。
接下来，提供了具有结合焊垫201(也称为电极焊垫)的衬底101。结合焊垫201是通过其将衬底101贴附到包含柱465的芯片400的部分。在衬底101上可以设置结合焊垫201，如本领域所公知。在本发明的一个方面，通过常规沉积和蚀刻工艺来提供结合焊垫。衬底101可以由任何适当的材料制成。用于衬底的适当的材料的一个实例是高玻璃转变的材料，如Bismalesimide Triazine(BT)环氧。
接下来，使用任何公知的倒装片工艺来贴附芯片400和衬底101。在本发明的一个方面，将包含柱465的芯片倒转且放置在包含粘结层458的衬底101上。或者，如图25所示，可以将粘结层458放置在芯片400上，且将衬底101倒转且放置在芯片400上。在本发明的又一方面，可以在贴附芯片400和衬底101之前在两者上均形成粘结层。当接触衬底101和芯片400时，结合焊垫201和柱465应基本被对准，如本领域所公知。
接下来，施加压力同时预固化粘结材料，由此初步连接芯片400和衬底101。该工艺中的压力仅需要足够保持芯片400和衬底101在一起同时预固化粘结层458。施加的压力一般可以从约2到3Kgf/cm2的范围，一般持续0.2到约5秒。
然后通过本领域中的任何机制来最终固化粘结材料，其将依据所使用的材料。一般地，可以施加光和/或热来固化粘结层458。在本发明的一个方面，通过在充分的温度下(在约180摄氏度的范围)持续充分的时间(大于约20秒)加热来固化粘结剂来完成固化工艺。
粘结层458包含在粘结层458的内部以一定间隙设置的导电颗粒459。于是，如图27所示，当贴附芯片400和衬底101时，至少一个导电颗粒位于柱凸点465和结合焊垫201之间。因为粘结层458的主体不是导电材料，所以芯片400和衬底101之间的仅有的导通是通过位于柱凸点465和结合焊垫201之间的导电颗粒。
在将芯片和衬底彼此贴附之后，在图27中绘示了所得到的结构。然后，将该结构通过本领域公知的任何工艺来封装。在本发明的一方面，如图28所示，通过首先将支撑膜501施加到衬底201的背侧来进行封装。在本发明的一个方面，支撑膜是聚酰亚胺(PI)膜。接下来，通过任何公知的手段，例如通过使用环氧模制化合物的转移模制(transfer molding)、通过施加的条形状的液体模制化合物、或通过阵列模制(array molding)，从而施加模制化合物502。在施加模制化合物之后，使用本领域公知的工艺来去除支撑膜501。
在模制工艺之后，可以电测试非单体的半导体封装。当半导体封装为条形状时执行参数测试。在电测试之后，可以激光标识半导体封装中的成型的模制材料。在激光标识之后，使用任何适当的工艺来单体化半导体封装阵列中的半导体封装，比如通过切割和划片。
图18-28绘制了WLCSP中芯片焊垫415的使用。在本发明的一方面，可以消除芯片焊垫415。芯片焊垫通常在随后的工艺期间用于保护芯片(IC405)。通过粘结层458也可以实现如此的功能。于是，在本发明的该方面，可以消除芯片焊垫415，如图29-30所示。
在本发明的该方面，半导体封装具有以下的优点。首先，半导体封装更可靠。通过采用ACF的倒装片方法制成的公知半导体封装因为两个原因易于失效。首先，或者在接触区上或者在导电颗粒上形成非导电膜。第二，由于或者粘结力的损失或压缩力的释放引起导电元件之间的机械接触的损失。在本发明中，通过封装减小或消除了这些失效机制。封装减小导电颗粒的水汽侵蚀和氧化。封装还在ACF上提供了压缩的残余应力且减小了高温度/次数下的蠕变。
第二优点在于粘结材料(ACF和ACP)不包含大量的铅，且因此比焊料更加环保。第三优点在于因为较小的颗粒尺寸所以本发明的半导体封装比现在使用焊料膏的那些封装提供了更高的分辨率能力。第四优点在于本发明的半导体封装在比焊接所需的那些温度要低很多的温度下固化，由此减小了热应力且对于热敏感组件和衬底更好。最后的优点在于与焊接工艺相比需要更少的工艺步骤，例如，不需要助焊剂和助焊剂净化工艺。
在本发明的又一方面，以图32-39所示的方式来制造晶片级芯片尺寸封装。在本发明的该方面，且如图32所示，提供了导电衬底515(也称为“衬底”或“衬底515”)。在本发明的该方面，导电衬底515充当用于如下述的粘结层的衬底，且包括一种在后用于形成如下述的导电信号迹线以及衬底的材料。由此，可以使用任何可以提供这些功能的材料来形成衬底515。在本发明的一方面，由导电材料形成衬底515，如金属箔或金属合金箔，比如Cu或Al。在本发明的一方面，衬底515包括Cu箔。在本发明的另一方面，Cu箔是一种Cu箔，其具有足够操作性和稳定性的重量，且能够承载合理量的电流。一般地，Cu箔可以为约0.5到约2盎司(oz)。在本发明的一方面，Cu箔是2盎司箔。可选地，Cu箔的操作性和稳定性可以通过在Cu箔的背侧上使用比如B阶聚合物的聚合物粘结材料来增加。在本发明的另一方面，衬底可以包括多层金属箔层。
导电衬底515可以具有与其上述的功能相一致的任何厚度。一般地，衬底的厚度的范围可以从约70到约300微米。在本发明的一方面，比如当使用Cu箔时，衬底515的厚度是约70微米。
如图32所示，将包含导电颗粒559的粘结层510施加到导电衬底515。如这里所述，粘结层510将衬底515贴附到管芯500(如下述)，同时充当有限的导体。任何以该方式起作用的材料可以被用作粘结层510，包括具有导电颗粒在其中的粘结材料，以及那些上述的用于粘结层458的材料。在本发明的一个方面，粘结材料可以具有液体(比如像ACP或ICP的膏)或固体(比如像ACF的膜)的形式。粘结材料的液体形式和固体形式均包含基本相同的组成(就导电颗粒、树脂、硬化剂等而言)，但是具有不同量的稀释剂(即，对于固态的低量的稀释剂且对于液体的高量的稀释剂)。因为在随后的工艺期间稀释剂蒸发，粘结材料的液体形式和固体形式均可以用于本发明中。
使用本领域中的任何公知机制可以施加粘结层510。例如，当ACP被用作粘结剂时，可以通过丝网印刷来施加层510。作为另一实例，当ACF被用作粘结剂时，可以通过膜贴附工艺来施加层510。
导电颗粒459可以是本领域中的任何公知的，其可以与粘结材料一起使用。在图26中示出了在粘结层458中可以使用的导电颗粒的实例。导电颗粒459a包括具有由绝缘层包围的金属层的聚合物颗粒。导电颗粒459b包括由绝缘层包围的金属颗粒。当在柱凸点和衬底之间存在接触时，在导电颗粒中的绝缘层破裂，由此产生导电路径(如上所述)。通常，导电颗粒包括约1到约40wt％的粘结材料。在本发明一方面，导电颗粒包括约4到约20wt％的粘结材料。
可以针对期望的器件的具体类型设计导电颗粒的含量、尺寸和种类以及因此的在粘结层510中的导电率的量。于是，可以将粘结层5 10的绝缘电阻从约108cm·Ω(对于具有小于30的间距的包含约20％的Au颗粒)到约1015cm·Ω或更多(对于包含约4％的Ni颗粒)进行调节。
粘结层510可以具有与其上述的功能相一致的任何厚度。一般地，衬底的厚度的范围可以从约5到约200微米。在本发明的一方面，比如当使用包含导电填料的由环氧或丙稀基材料制成的ACF时，粘结层5 10的厚度的范围可以从约25到约50微米。粘结层应匹配管芯上的凸点的高度。
如图32所示，然后提供管芯500。管芯(或芯片)500可以是如本领域中公知的任何常规的管芯。然后可以在管芯上形成可选的钝化层(基本相似于钝化层110)。当使用时，然后在集成电路508的区域中去除部分的钝化层，且在所暴露的部分中形成芯片焊垫512。用于这些工艺的方法基本相似于那些上述的方法。
然后，形成柱(或柱凸点)505。如图32所示，在芯片焊垫512上分别形成柱505。采用如本领域所公知的覆层通过电镀用于柱凸点的材料，可以形成柱凸点505。在本发明的一个方面，用于柱凸点的材料是Cu，且覆层是Pd。或者，通过如上所述的引线键合工艺可以形成柱凸点505。
接下来，使用任何公知的倒装片工艺来贴附管芯500(包含柱505)和具有在其上的粘结层510的导电衬底515。在本发明的一个方面，将包含柱505的管芯500倒转且放置在包含粘结层510的衬底515上。或者，如上所述，可以将粘结层510放置在包含柱505的管芯500上，且将衬底515倒转且放置在其上。在本发明的又一方面，可以在贴附管芯500和衬底515之前在两者上均形成粘结层510。
接下来，施加压力同时预固化粘结材料，由此初步连接管芯500和衬底515。该工艺中的压力仅需要足够保持这两个组件在一起同时预固化粘结层510。施加的压力一般可从约2到3Kgf/cm2的范围，一般持续0.2到约5秒。
然后通过本领域中的任何机制来最终固化粘结材料，其将依据所使用的材料。一般地，可以施加光和/或热来固化粘结层510。在本发明的一个方面，通过在充分的温度下(在约1 80摄氏度的范围)持续充分的时间(大于约20秒)加热来固化粘结剂来完成固化工艺。
在该热压结合工艺之后，如图33所示，将管芯500和衬底515电和机械连接。粘结层510包含在粘结层510的内部以一定间隙设置的导电颗粒459。于是，如图34所示，当贴附管芯500和衬底515时，至少一个导电颗粒位于柱凸点505和衬底515之间。因为粘结层510的主体不是导电材料，所以管芯500和衬底515之间的仅有的导通基本上是通过该导电颗粒。
在将芯片和衬底彼此贴附之后，在图33中绘示了所得到的结构。然后，将该结构通过本领域公知的任何工艺来封装。在本发明的一方面，如图35所示，通过任何本领域的公知的上模制(overmolding)工艺来进行封装。例如，参见美国专利No.6,537,853所述的工艺，其公开通过参考引入于此。在本发明的一个方面，上模制工艺包括上述的那些模制工艺。
在形成封装517的模制工艺之后，然后蚀刻衬底515来形成电信号迹线。本领域公知的任何蚀刻工艺可以被用于蚀刻衬底515来形成信号迹线511。在本发明的一个方面，通过常规的工艺来执行蚀刻，所述常规的工艺包括光致抗蚀剂涂布、显影、蚀刻和剥离。在本发明的另一方面，执行蚀刻工艺，从而构图的衬底作为将形成于管芯500上的紧密焊垫布局转变到电路板所需的较大节距布局的再分布层。如图37所示，构图的衬底将来自管芯焊垫位置505的电信号再分布到焊料球所在且用于安装于电路板上的位置525。
在本发明的一方面，然后镀覆包括构图的衬底的迹线516。该镀覆工艺将导电层放置在迹线的上方来保护构图的衬底免受氧化。在本发明中用于该目的任何导电材料可以被用在本方面中，比如Au、Ni、Pd和其组合或合金。在本发明的一个方面，可以使用Ni/Pd作为镀覆的材料。
接下来，可选地在所得到的结构上形成焊料抗蚀剂层530。因为粘结层510可以具有高的水汽吸收率，所以焊料抗蚀剂层530可以保护粘结层510免受水汽和外部冲击的影响，并且可以在构图的衬底515上印刷以将用于焊料球贴附的区域排除在外。如果需要，然后可以通过任何本领域公知的工艺以及上述的那些工艺将焊料球535贴附。
接下来，可以电测试非单体的半导体封装。当半导体封装为条形状时执行参数测试。在电测试之后，可以激光标识半导体封装中的成型的模制材料。在激光标识之后，使用任何适当的工艺来单体化半导体封装阵列中的半导体封装，如图39所示，比如通过切割和划片。
在本发明的该方面，半导体封装具有以下的优点。首先，使用简单的工艺形成半导体封装。第二，贴附到管芯的导电衬底还充当再分布层。第三，可以在引线键合封装及倒装片封装中使用相同的管芯而没有任何改变。第四，用于生产的成本(具体而言对于组装件)比常规的WLCSP的成本低很多。最后，封装尺寸的减小是相当显著的。例如，1.9mm×2.5mm的管芯尺寸通常需要具有约4mm×4mm尺寸的封装。使用本发明，相同管芯尺寸仅需要3mm×2.5mm或更小尺寸的封装。
已经描述了本发明的这些方面，可以理解由权利要求界定的本发明不限于上述描述中所阐述的具体细节，因为许多其明显的变化是可能的而不脱离其精神或范围。

Claims (56)

1、一种晶片级芯片尺寸封装，包括：
芯片焊垫，在衬底上方；
再分布线图案，在所述芯片焊垫上；和
绝缘层，覆盖部分的所述再分布线图案，其中，所述绝缘层包括非聚合物介电材料。
2、如权利要求1所述的封装，还包括：柱凸点，在没有被所述绝缘层覆盖的再分布线图案的部分上。
3、如权利要求1所述的封装，还包括：钝化层，在所述衬底和所述再分布线图案之间。
4、如权利要求1所述的封装，其中，所述绝缘层包括氮化硅、氧化硅或氧氮化硅。
5、如权利要求1所述的封装，其中，所述芯片焊垫和所述再分布线图案包括铝。
6、如权利要求2所述的封装，其中，所述柱凸点包括Cu。
7、如权利要求2所述的封装，其中，在所述芯片焊垫和所述再分布线图案之间没有凸点下金属。
8、一种晶片级芯片尺寸封装，包括：
芯片焊垫，在衬底上方；
再分布线图案，在所述芯片焊垫上；
绝缘层，覆盖部分的所述再分布线图案，其中，所述绝缘层包括非聚合物介电材料；和
柱凸点，在没有被所述绝缘层覆盖的再分布线图案的部分上。
9、一种封装的半导体器件，包括：
芯片焊垫，在衬底上方；
再分布线图案，在所述芯片焊垫上；
绝缘层，覆盖部分的所述再分布线图案，其中，所述绝缘层包括非聚合物介电材料；和
柱凸点，在没有被所述绝缘层覆盖的再分布线图案的部分上。
10、一种包含封装的半导体器件的电子设备，所述器件包括：
芯片焊垫，在衬底上方；
再分布线图案，在所述芯片焊垫上；
绝缘层，覆盖部分的所述再分布线图案，其中，所述绝缘层包括非聚合物介电材料；和
柱凸点，在没有被所述绝缘层覆盖的再分布线图案的部分上。
11、一种形成晶片级芯片尺寸封装的方法，包括：
在衬底上方设置芯片焊垫；
在所述芯片焊垫上设置再分布线图案；
设置覆盖部分的所述再分布线图案的绝缘层，其中，所述绝缘层包括非聚合物介电材料；和
在没有被所述绝缘层覆盖的再分布线图案的部分上设置柱凸点。
12、一种形成晶片级芯片尺寸封装的方法，包括：
提供衬底，在所述衬底的部分上具有钝化层；
在不包含所述钝化层的衬底的部分上形成芯片焊垫；
在所述芯片焊垫上和所述钝化层的部分上形成再分布线图案；
在部分的所述再分布线图案上形成绝缘层，其中，所述绝缘层包括非聚合物介电材料；和
在没有被所述绝缘层覆盖的再分布线图案的部分上形成柱凸点。
13、如权利要求12所述的方法，包括不使用高温固化工艺来形成所述绝缘层。
14、如权利要求12所述的方法，其中，在所述芯片焊垫和所述再分布线图案之间没有凸点下金属。
15、如权利要求12所述的方法，包括通过电镀工艺或引线键合来形成所述柱凸点。
16、如权利要求15所述的方法，包括通过使用毛细管将涂钯的铜引线键合到所述再分布图案来形成所述柱凸点。
17、如权利要求15所述的方法，其中，所述引线键合工艺提供了具有压模形状的柱凸点。
18、一种形成封装的半导体器件的方法，包括：
在衬底上方设置芯片焊垫；
在所述芯片焊垫上设置再分布线图案；
设置覆盖部分的所述再分布线图案的绝缘层，其中，所述绝缘层包括非聚合物介电材料；和
在没有被所述绝缘层覆盖的再分布线图案的部分上设置柱凸点。
19、一种形成包含封装的半导体器件的电子设备的方法，所述方法包括：
提供一种封装的半导体器件，所述器件包括：芯片焊垫，在衬底上方；再分布线图案，在所述芯片焊垫上；绝缘层，覆盖部分的所述再分布线图案，所述绝缘层包括非聚合物介电材料；和在没有被所述绝缘层覆盖的再分布线图案的部分上设置柱凸点；
将所述封装的半导体器件安装于电路板上。
20、一种晶片级芯片尺寸封装，包括：
芯片，包含柱凸点；
衬底，包含结合焊垫；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒。
21、如权利要求20所述的封装，其中，至少一个所述导电颗粒位于所述柱凸点和所述结合焊垫之间。
22、如权利要求20所述的封装，其中，所述导电颗粒包括具有绝缘层的金属。
23、如权利要求20所述的封装，其中，所述粘结材料包括各向异性导电膜，各向异性导电膏、或各向同性导电膏。
24、如权利要求20所述的封装，其中，所述芯片不包含焊料膏。
25、如权利要求20所述的封装，其中，所述柱凸点包含Cu。
26、一种晶片级芯片尺寸封装，包括：
芯片，包含柱凸点，所述柱凸点包含Cu；
衬底，包含结合焊垫；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒，至少一个所述导电颗粒位于所述柱凸点和所述结合焊垫之间。
27、一种封装的半导体器件，包括：
芯片，包含柱凸点，所述柱凸点包含Cu；
衬底，包含结合焊垫；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒，至少一个所述导电颗粒位于所述柱凸点和所述结合焊垫之间。
28、一种包含封装的半导体器件的电子设备，所述器件包括：
芯片，包含柱凸点；
衬底，包含结合焊垫；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒。
29、一种形成晶片级芯片尺寸封装的方法，包括：
提供包含柱凸点的芯片；
提供包含结合焊垫的衬底；
使用包含导电颗粒的粘结材料将所述芯片贴附到所述衬底。
30、一种形成晶片级芯片尺寸封装的方法，包括：
提供具有柱凸点的芯片；
提供包含结合焊垫的衬底；
在所述芯片、所述衬底或两者上设置包含导电颗粒的粘结材料；
将所述芯片和所述衬底压在一起；和
固化所述粘结材料。
31、如权利要求30所述的方法，其中，在所述柱凸点和所述结合焊垫之间设置至少一个所述导电颗粒。
32、如权利要求30所述的方法，其中，所述粘结材料包括各向异性导电膜，各向异性导电膏、或各向同性导电膏。
33、如权利要求30所述的方法，包括对所述芯片提供再分布线图案和覆盖所述再分布图案的绝缘层。
34、如权利要求30所述的方法，其中，所述固化粘结材料将所述芯片贴附到所述衬底。
35、如权利要求34所述的方法，其中，包括没有使用焊料膏将所述芯片贴附到所述衬底。
36、如权利要求30所述的方法，其中，所述柱凸点包含Cu。
37、一种形成包含晶片级芯片尺寸封装的电子设备，所述方法包括：
提供一种晶片级芯片尺寸封装，所述封装包括：芯片，包含柱凸点；衬底，包含结合焊垫；和粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒；和
将所述封装的半导体器件安装于电路板上。
38、一种晶片级芯片尺寸封装，包括：
芯片，包含柱凸点；
导电衬底；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒。
39、如权利要求38所述的封装，其中，导电颗粒位于所述芯片和所述衬底之间。
40、如权利要求38所述的封装，其中，所述导电颗粒包括具有绝缘层的金属。
41、如权利要求38所述的封装，其中，所述粘结材料包括各向异性导电膜或各向异性导电膏。
42、如权利要求38所述的封装，其中，所述导电衬底已经被构图。
43、如权利要求42所述的封装，其中，所述构图的导电衬底充当再分布层。
44、如权利要求38所述的封装，其中，所述导电衬底包括铜。
45、如权利要求44所述的封装，其中，所述导电衬底包括铜箔。
46、一种晶片级芯片尺寸封装，包括：
芯片，包含柱凸点；
导电衬底；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒，所述导电颗粒位于所述芯片和所述衬底之间。
47、一种封装的半导体器件，包括：
芯片，包含柱凸点；
构图的导电衬底；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒，所述导电颗粒位于所述芯片和所述衬底之间。
48、一种包含封装的半导体器件的电子设备，所述器件包括：
芯片，包含柱凸点；
导电衬底；和
粘结材料，包含位于所述芯片和所述衬底之间的导电颗粒。
49、一种形成晶片级芯片尺寸封装的方法，包括：
提供包含柱凸点的芯片；
提供导电衬底；
使用包含导电颗粒的粘结材料将所述芯片贴附到所述衬底。
50、一种形成晶片级芯片尺寸封装的方法，包括：
提供具有柱凸点的芯片；
提供导电衬底；
在所述芯片、所述衬底或两者上设置包含导电颗粒的粘结材料；
将所述芯片和所述衬底压在一起；和
固化所述粘结材料。
51、如权利要求50所述的方法，其中，在所述柱凸点和所述结合焊垫之间设置至少一个所述导电颗粒。
52、如权利要求50所述的方法，其中，所述粘结材料包括各向异性导电膜或各向异性导电膏。
53、如权利要求50所述的方法，其中，所述固化粘结材料将所述芯片电和机械连接到所述衬底。
54、如权利要求50所述的方法，还包括构图所述导电衬底。
55、如权利要求54所述的方法，其中，所述构图的芯片充当再分布层。
56、一种形成包含晶片级芯片尺寸封装的电子设备，所述方法包括：
提供包含柱凸点芯片；提供导电衬底；和使用包含导电颗粒的粘结材料将所述芯片贴附到所述衬底；和
将所述晶片级芯片尺寸封装安装于电路板上。
CN2004800199895A 2003-07-11 2004-07-08 晶片级芯片尺寸封装及其制造和使用方法 Expired - Fee Related CN101410973B (zh)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102254897A (zh) * 2010-05-18 2011-11-23 台湾积体电路制造股份有限公司 具有中介层的封装系统
CN102347320A (zh) * 2010-07-21 2012-02-08 台湾积体电路制造股份有限公司 装置及其制造方法
CN103151275A (zh) * 2011-12-06 2013-06-12 北京大学深圳研究生院 倒装芯片金凸点的制作方法
CN103187394A (zh) * 2011-12-29 2013-07-03 台湾积体电路制造股份有限公司 具有无源器件的封装件及其形成方法
CN105632939A (zh) * 2015-12-24 2016-06-01 合肥祖安投资合伙企业(有限合伙) 一种具有重布线层的封装结构及制造方法
CN105895604A (zh) * 2015-02-17 2016-08-24 南茂科技股份有限公司 半导体装置
CN106970506A (zh) * 2017-04-10 2017-07-21 中国科学院上海光学精密机械研究所 一种基于粒子群优化算法的晶圆曝光路径规划方法
CN108461464A (zh) * 2018-02-07 2018-08-28 睿力集成电路有限公司 半导体封装结构及其制造方法
CN109427719A (zh) * 2017-08-28 2019-03-05 三星电机株式会社 扇出型半导体封装件
CN109937476A (zh) * 2016-09-23 2019-06-25 密克罗奇普技术公司 晶片级封装和方法
CN111527249A (zh) * 2017-12-28 2020-08-11 美来株式会社 利用超声波的医用三维线制造方法及制造装置

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429856B1 (ko) * 2001-11-15 2004-05-03 페어차일드코리아반도체 주식회사 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
US7271496B2 (en) 2005-02-04 2007-09-18 Stats Chippac Ltd. Integrated circuit package-in-package system
TWI284949B (en) * 2005-09-09 2007-08-01 Chipmos Technologies Inc Bumped structure and its forming method
US7371616B2 (en) 2006-01-05 2008-05-13 Fairchild Semiconductor Corporation Clipless and wireless semiconductor die package and method for making the same
DE102006036798B4 (de) * 2006-08-07 2013-08-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) * 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US7618857B2 (en) * 2007-01-17 2009-11-17 International Business Machines Corporation Method of reducing detrimental STI-induced stress in MOSFET channels
JP2008211125A (ja) * 2007-02-28 2008-09-11 Spansion Llc 半導体装置およびその製造方法
JP5584474B2 (ja) * 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR101458538B1 (ko) 2007-07-27 2014-11-07 테세라, 인코포레이티드 적층형 마이크로 전자 유닛, 및 이의 제조방법
KR101538648B1 (ko) 2007-07-31 2015-07-22 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US10074553B2 (en) 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US9460951B2 (en) 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US7766667B2 (en) * 2007-12-18 2010-08-03 Russell James V Separable electrical connectors using isotropic conductive elastomer interconnect medium
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US7952200B2 (en) * 2008-07-16 2011-05-31 Infineon Technologies Ag Semiconductor device including a copolymer layer
US8637983B2 (en) * 2008-12-19 2014-01-28 Ati Technologies Ulc Face-to-face (F2F) hybrid structure for an integrated circuit
TW201032293A (en) * 2009-02-23 2010-09-01 Etron Technology Inc Moisture-proof device, moisture-proof chip, and method for increasing moisture-proof capability of chip
EP2406821A2 (en) 2009-03-13 2012-01-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
FR2943849B1 (fr) * 2009-03-31 2011-08-26 St Microelectronics Grenoble 2 Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur
US20110095417A1 (en) * 2009-10-28 2011-04-28 Fairchild Semiconductor Corporation Leadless semiconductor device terminal
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
CN101800207B (zh) * 2010-03-12 2011-10-26 苏州晶方半导体科技股份有限公司 半导体器件的封装结构及其制造方法
US8362612B1 (en) * 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8698306B2 (en) 2010-05-20 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate contact opening
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
CN102244061A (zh) * 2011-07-18 2011-11-16 江阴长电先进封装有限公司 Low-k芯片封装结构
US9355978B2 (en) 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
CN103681384B (zh) * 2012-09-17 2016-06-01 宏启胜精密电子(秦皇岛)有限公司 芯片封装基板和结构及其制作方法
US9048149B2 (en) 2013-07-12 2015-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-alignment structure for wafer level chip scale package
US9196529B2 (en) 2013-09-27 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor devices
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
CN103887251B (zh) * 2014-04-02 2016-08-24 华进半导体封装先导技术研发中心有限公司 扇出型晶圆级封装结构及制造工艺
CN103929896A (zh) * 2014-05-07 2014-07-16 上海美维科技有限公司 一种内埋芯片的印制电路板制造方法
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
CN104851860B (zh) * 2015-04-30 2018-03-13 华为技术有限公司 一种集成电路管芯及制造方法
KR102456667B1 (ko) 2015-09-17 2022-10-20 삼성전자주식회사 재배선 패드를 갖는 반도체 소자
US9576912B1 (en) 2015-12-03 2017-02-21 Stmicroelectronics Pte Ltd Wafer level chip scale package (WLCSP) having edge protection
US10879195B2 (en) * 2018-02-15 2020-12-29 Micron Technology, Inc. Method for substrate moisture NCF voiding elimination
KR102209383B1 (ko) * 2018-12-31 2021-02-01 (주)단단 이터븀과 이트륨이 공도핑된 사이알론 및 그 제조방법

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2034702A1 (en) * 1990-01-23 1991-07-24 Masanori Nishiguchi Method for packaging semiconductor device
JP3178181B2 (ja) * 1993-09-06 2001-06-18 松下電器産業株式会社 アウターリードボンディング装置およびアウターリードボンディング方法
WO1996005614A1 (en) * 1994-08-12 1996-02-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flip chip bonding with non-conductive adhesive
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5559054A (en) * 1994-12-23 1996-09-24 Motorola, Inc. Method for ball bumping a semiconductor device
KR0181615B1 (ko) * 1995-01-30 1999-04-15 모리시다 요이치 반도체 장치의 실장체, 그 실장방법 및 실장용 밀봉재
WO1996042107A1 (en) * 1995-06-13 1996-12-27 Hitachi Chemical Company, Ltd. Semiconductor device, wiring board for mounting semiconductor and method of production of semiconductor device
KR100201383B1 (ko) * 1995-10-19 1999-06-15 구본준 인터페이스 조립체를 구비한 유에프비지에이 패키지
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5611884A (en) * 1995-12-11 1997-03-18 Dow Corning Corporation Flip chip silicone pressure sensitive conductive adhesive
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
JP3842362B2 (ja) * 1996-02-28 2006-11-08 株式会社東芝 熱圧着方法および熱圧着装置
JP3343642B2 (ja) * 1996-04-26 2002-11-11 シャープ株式会社 テープキャリアパッケージ及び液晶表示装置
US5808874A (en) * 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US5847458A (en) * 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
US6022761A (en) * 1996-05-28 2000-02-08 Motorola, Inc. Method for coupling substrates and structure
US6020220A (en) * 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
US5986334A (en) * 1996-10-04 1999-11-16 Anam Industrial Co., Ltd. Semiconductor package having light, thin, simple and compact structure
JPH10135270A (ja) * 1996-10-31 1998-05-22 Casio Comput Co Ltd 半導体装置及びその製造方法
US6461890B1 (en) * 1996-12-27 2002-10-08 Rohm Co., Ltd. Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same
US6190509B1 (en) * 1997-03-04 2001-02-20 Tessera, Inc. Methods of making anisotropic conductive elements for use in microelectronic packaging
JPH10270624A (ja) * 1997-03-27 1998-10-09 Toshiba Corp チップサイズパッケージ及びその製造方法
US5783465A (en) * 1997-04-03 1998-07-21 Lucent Technologies Inc. Compliant bump technology
JP3455871B2 (ja) * 1997-06-23 2003-10-14 株式会社スリーボンド マイクロカプセル型導電性フィラーの製造方法
US6107122A (en) * 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6097087A (en) * 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US6096578A (en) * 1997-11-05 2000-08-01 Texas Instruments Incorporated Stress relief matrix for integrated circuit packaging
US6064114A (en) * 1997-12-01 2000-05-16 Motorola, Inc. Semiconductor device having a sub-chip-scale package structure and method for forming same
KR100253363B1 (ko) * 1997-12-02 2000-04-15 김영환 반도체 패키지용 기판과 그 기판을 이용한 랜드 그리드 어레이반도체 패키지 및 그들의 제조 방법
US6468830B1 (en) * 1998-01-26 2002-10-22 Tessera, Inc. Compliant semiconductor package with anisotropic conductive material interconnects and methods therefor
TW459032B (en) * 1998-03-18 2001-10-11 Sumitomo Bakelite Co An anisotropic conductive adhesive and method for preparation thereof and an electronic apparatus using said adhesive
US6462284B1 (en) * 1998-07-01 2002-10-08 Seiko Epson Corporation Semiconductor device and method of manufacture thereof
KR100269540B1 (ko) * 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
US6426566B1 (en) * 1998-12-02 2002-07-30 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
JP3487777B2 (ja) * 1999-02-02 2004-01-19 シャープ株式会社 テープキャリアパッケージおよびそれを用いた液晶モジュール
TW408411B (en) * 1999-03-31 2000-10-11 Huang Jr Gung Semiconductor chip scale package
JP2000306948A (ja) * 1999-04-21 2000-11-02 Rohm Co Ltd 半導体装置、およびその製造方法
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
JP2001013883A (ja) * 1999-06-30 2001-01-19 Fujitsu Ltd ドライバｉｃ実装モジュール及びそれを使用した平板型表示装置
KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
KR100366409B1 (ko) * 1999-09-21 2002-12-31 엘지전자 주식회사 접착성 전도체 및 이를 사용한 칩실장구조
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6511901B1 (en) * 1999-11-05 2003-01-28 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
KR100319813B1 (ko) * 2000-01-03 2002-01-09 윤종용 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
JP3420153B2 (ja) * 2000-01-24 2003-06-23 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6548328B1 (en) * 2000-01-31 2003-04-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
JP2002008807A (ja) * 2000-06-22 2002-01-11 Mitsubishi Electric Corp 半導体装置の検査装置および検査方法
KR100370398B1 (ko) * 2000-06-22 2003-01-30 삼성전자 주식회사 전자 및 ｍｅｍｓ 소자의 표면실장형 칩 규모 패키징 방법
US6566748B1 (en) * 2000-07-13 2003-05-20 Fujitsu Limited Flip-chip semiconductor device having an improved reliability
US6518097B1 (en) * 2000-08-29 2003-02-11 Korea Advanced Institute Of Science And Technology Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive
US6689640B1 (en) * 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
JP3526548B2 (ja) * 2000-11-29 2004-05-17 松下電器産業株式会社 半導体装置及びその製造方法
TW554191B (en) * 2000-12-16 2003-09-21 Au Optronics Corp Laminating structure and its forming method
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
AU2002254027A1 (en) * 2001-02-27 2002-09-12 Chippac, Inc. Tape ball grid array semiconductor package structure and assembly process
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
KR100429856B1 (ko) * 2001-11-15 2004-05-03 페어차일드코리아반도체 주식회사 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
US6611052B2 (en) * 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
US6939789B2 (en) * 2002-05-13 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer level chip scale packaging
US6590295B1 (en) * 2002-06-11 2003-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with a spacer redistribution layer via and method of making the same
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102254897B (zh) * 2010-05-18 2015-06-10 台湾积体电路制造股份有限公司 具有中介层的封装系统
CN102254897A (zh) * 2010-05-18 2011-11-23 台湾积体电路制造股份有限公司 具有中介层的封装系统
CN102347320A (zh) * 2010-07-21 2012-02-08 台湾积体电路制造股份有限公司 装置及其制造方法
CN103151275A (zh) * 2011-12-06 2013-06-12 北京大学深圳研究生院 倒装芯片金凸点的制作方法
CN103187394A (zh) * 2011-12-29 2013-07-03 台湾积体电路制造股份有限公司 具有无源器件的封装件及其形成方法
CN103187394B (zh) * 2011-12-29 2015-10-28 台湾积体电路制造股份有限公司 具有无源器件的封装件及其形成方法
CN105895604B (zh) * 2015-02-17 2019-03-01 南茂科技股份有限公司 半导体装置
CN105895604A (zh) * 2015-02-17 2016-08-24 南茂科技股份有限公司 半导体装置
CN105632939A (zh) * 2015-12-24 2016-06-01 合肥祖安投资合伙企业(有限合伙) 一种具有重布线层的封装结构及制造方法
CN109937476A (zh) * 2016-09-23 2019-06-25 密克罗奇普技术公司 晶片级封装和方法
CN109937476B (zh) * 2016-09-23 2023-08-01 密克罗奇普技术公司 晶片级封装和方法
CN106970506A (zh) * 2017-04-10 2017-07-21 中国科学院上海光学精密机械研究所 一种基于粒子群优化算法的晶圆曝光路径规划方法
CN109427719A (zh) * 2017-08-28 2019-03-05 三星电机株式会社 扇出型半导体封装件
CN109427719B (zh) * 2017-08-28 2022-07-05 三星电机株式会社 扇出型半导体封装件
CN111527249A (zh) * 2017-12-28 2020-08-11 美来株式会社 利用超声波的医用三维线制造方法及制造装置
CN108461464A (zh) * 2018-02-07 2018-08-28 睿力集成电路有限公司 半导体封装结构及其制造方法
CN108461464B (zh) * 2018-02-07 2023-07-25 长鑫存储技术有限公司 半导体封装结构及其制造方法

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US20090111219A1 (en) 2009-04-30
US20050012225A1 (en) 2005-01-20
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MY155012A (en) 2015-08-28
WO2005008724A2 (en) 2005-01-27

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