CN101473443A - 用于形成屏蔽栅极沟槽fet的结构和方法 - Google Patents

用于形成屏蔽栅极沟槽fet的结构和方法 Download PDF

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CN101473443A
CN101473443A CNA2007800230139A CN200780023013A CN101473443A CN 101473443 A CN101473443 A CN 101473443A CN A2007800230139 A CNA2007800230139 A CN A2007800230139A CN 200780023013 A CN200780023013 A CN 200780023013A CN 101473443 A CN101473443 A CN 101473443A
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groove
gate electrode
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内森·克拉夫特
克里斯多佛·博古斯洛·科库
保尔·托鲁普
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Fairchild Semiconductor Corp
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Abstract

一种场效应晶体管(FET)包括延伸进入半导体区域的多个沟槽。每个沟槽包括栅极电极和屏蔽电极，其间含有极间电介质，其中，屏蔽电极和栅极电极电连接在一起。

Description

用于形成屏蔽栅极沟槽FET的结构和方法
技术领域
本发明大致涉及半导体功率场效应晶体管(FET)，并且具体地，涉及含有连接在一起的屏蔽电极和栅极电极的屏蔽栅极沟槽FET。
背景技术
屏蔽栅极沟槽FET相对于传统FET的优势在于，屏蔽电极减小了栅极-漏极电容(Cgd)并提高了晶体管的截止电压。图1是传统的屏蔽栅极沟槽MOSFET的简化截面图。n-型外延层102延伸至n+衬底100上方。N+源极区108和p+重体区域106形成于p-型体区域104，所述体区域依次形成于外延层102。沟槽110延伸至体区域104且终止于漂移区。沟槽110包括屏蔽电极114，位于栅极电极122下方。栅极电极122通过使用栅极电介质120而与其邻近的硅区域隔离，而屏蔽电极114通过使用比栅极电介质120厚的屏蔽电介质112而与其邻近硅区域隔离。
栅极电极和屏蔽电极通过介电层116而彼此隔离，该介电层还称作极间电介质或IED。IED层116必须具有足够的质量和厚度来支持可能存在于屏蔽电极114和栅极电极122之间的电势差。此外，屏蔽电极114和IED层116之间的接口处或IED层116中的接口阱(trap)电荷和介电阱电荷与用于形成IED层的方法主要相关。
典型地，有多种处理方法形成IED。然而，确保足够强度和足够可靠的高质量IED以提供需要的电学特性，导致用于形成屏蔽栅极沟槽FET的工艺十分复杂。因此，需要一种用于形成屏蔽栅极沟槽FET的结构和方法来去除对高质量IED的需求，从而作为导通阻抗来维持或提升这种电学特性。
发明内容
根据本发明实施例，场效应晶体管包括延伸进入半导体区域的多个沟槽。每个沟槽包括栅极电极和屏蔽电极，其间含有极间电介质，其中，栅极电极和屏蔽电极电连接在一起。
在一个实施例中，屏蔽电极是每个沟槽的下部，并通过使用屏蔽电介质而与半导体区域隔离。极间电介质延伸至每个屏蔽电极上方。栅极电极位于极间电介质上方的每个沟槽上部，并通过使用栅极电介质而与半导体区域隔离。
在另一实施例中，半导体区域包括第一导电型的漂移区、延伸至漂移区上方的第二导电型的体区域、以及位于邻近沟槽的体区域中的第一导电型的源极区。
在另一实施例中，半导体区域进一步包括第一导电型的衬底，其具有在衬底上方延伸的漂移区，其中，沟槽延伸通过体区域并终止于漂移区中。
在另一实施例中，沟槽延伸通过体区域和漂移区，并终止于衬底中。
在另一实施例中，场效应晶体管进一步包括其中形成有沟槽的活动区(active region)以及非活动区(non-active region)。屏蔽电极和栅极电极延伸至每个沟槽外且延伸进入非活动区，其中，屏蔽电极和栅极电极通过栅极互联层而电连接在一起。
在另一实施例中，屏蔽电极和栅极电极之间的电连接是通过形成于非活动区栅极滑槽区域中的周期性接触开口而进行的。
在又一实施例中，屏蔽电极通过经由每个沟槽中的互联介电层的附加连接而电连接至栅极电极。
在另一实施例中，非活动区包括沿覆盖FET的管芯的周围延伸的终止区，屏蔽电极和栅极电极延伸至每个沟槽外且延伸进入终止区，其中，屏蔽电极和栅极电极由栅极互联层连接在一起。
根据本发明的另一实施例，场效应晶体管以如下方式形成。形成多个延伸进入半导体区域的沟槽。在每个沟槽的底部形成屏蔽电极。在屏蔽电极上方的每个沟槽上部形成栅极电极。形成栅极电极和电连接至屏蔽电极的栅极互联层。
在一个实施例中，在形成屏蔽电极之前，形成位于下部侧壁和底部表面的屏蔽介电层。在形成栅极电极之前，形成位于屏蔽电极的上部沟槽侧壁和表面的介电层。
在另一实施例中，形成屏蔽电极和栅极电极，以使屏蔽电极和栅极电极延伸至沟槽外且延伸至台面区域上方。在延伸至台面区域上方的栅极电极部分中形成多个接触开口，以通过接触开口暴露屏蔽电极的表面区域。形成互联层以填充接触开口，从而使屏蔽电极和栅极电极彼此电连接。
在另一实施例中，台面区域位于覆盖FET的管芯的非活动区中。
在另一实施例中，介电层由硅的氧化物形成。
在另一实施例中，在形成栅极电极之前，在延伸至屏蔽电极上方的介电层部分中形成一个或多个开口，从而一旦在沟槽中形成栅极电极，栅极电极就会通过一个或多个开口而与屏蔽电极电接触。
附图说明
图1是传统的屏蔽栅极沟槽MOSFET的截面图；
图2A-2H是用于形成根据本发明实施例的屏蔽栅极沟槽FET的工艺的多个步骤中的简化截面图；以及
图3是根据本发明实施例的屏蔽栅极沟槽FET中的栅极滑槽部分的等比例图。
具体实施方式
图2A至2H是用于形成根据本发明实施例的屏蔽栅极沟槽(trench)FET的工艺的多个步骤中的简化截面图。图2A至2H中，左侧截面图示出了能够在活动区(active region)中形成屏蔽栅极沟槽FET结构的顺序步骤，而右侧截面图示出了从活动区到非活动区(从右至左)的过度区的对应示图。在本披露中，“活动区”表示用于覆盖(house)活动单元(active cell)的管芯(die)的区域，而“非活动区”表示不包括任何活动单元的管芯的区域。非活动区包括沿管芯周围伸展的终止区、和沿管芯周围或中部伸展的或沿管芯周围和中部伸展的栅极滑槽(gate runner)。
在图2A中，使用传统技术，在半导体区202中形成沟槽210，然后，在沟槽侧壁和底部表面处形成屏蔽电介质212(例如，含有氧化物)并沿邻近沟槽的台面(mesa)区延伸。图2A至图2H的每个图中的右侧截面图均沿垂直于右侧截面图的维度穿过左侧截面图中沟槽的中心。因此，右侧截面图示出了在活动区边缘终止的左侧截面图的沟槽。此外，这些截面图并不按比例确定，且更具体地，左侧和右侧截面图中的相同层或区的物理维度(例如，厚度)可能看起来不同。例如，在图2A中，屏蔽电介质212在右侧截面图中看起来要比左侧更薄。
如图2A中右侧截面图所示，屏蔽电介质212沿沟槽210的底部表面伸展，而在活动区的边缘处，在沟槽210的上部和外部以及在硅区域202上部延伸。在一个实施例中，半导体区域202包括在重掺杂的(highly doped)n-型衬底上放形成的n-型外延(epitaxial)层(未示出)，而沟槽202延伸进入并终止于外延层中。在另一变化中，沟槽202穿过外延层延伸并在衬底中终止。
在图2B中，沿沟槽210的底部形成屏蔽电极214，且屏蔽电极在管芯的非活动区以如下方式被制成为易受电控制。运用已知技术，首先形成填充沟槽并在台面区上延伸的导体材料(例如，含有掺杂或不掺杂的多晶硅)，然后，使该材料深深凹陷进入沟槽210以形成屏蔽电极214。
在凹陷导体材料的过程中，掩膜211用于保护在管芯的非活动区中延伸的导体材料的部分。因此，屏蔽电极214在沟槽210中要比在管芯非活动区中的台面表面上更厚，如图2B中右侧截面图所示。此外，以如下方式对掩膜211进行应用，在活动区的边缘处，屏蔽电极延伸至沟槽210的外部以及非活动区的台面表面上方。因而，沟槽210中的屏蔽电极214被制成为可以在管芯的非活动区中电连接。
在图2C中，运用已知方法，将屏蔽电介质212在活动区中沿沟槽侧壁以及台面表面上方完全移除，如右侧截面图中所示。在一个实施例中，使屏蔽电极214凹陷，以使其顶部表面与屏蔽电介质层212的顶部表面共面。这就为栅极/内电极介电层的随后形成提供了平坦的表面。
在图2D中，运用传统技术形成沿上部沟槽侧壁伸展的栅极介电层216。在一个实施例中，运用传统的硅的氧化技术来形成栅极电介质216。这种过程还会导致屏蔽电极214的氧化，因此在栅极电极214上方形成极间介电(inter-electrode dielectric，IED)层。图右侧截面图所示，介电层216沿活动区和非活动区中屏蔽电极214的所有暴露表面延伸。如下文中的进一步讨论，去除了特别需要用于形成高质量IED的附加处理步骤。
在图2E中，以如下方式在沟槽210中形成凹陷的栅极电极222，且栅极电极被制成为在非活动区中可受电控制。运用已知技术，形成填充沟槽210并在台面区上延伸的第二导电层(例如，含有掺杂的多晶硅)，然后，使该第二导电层凹陷进入沟槽210以形成栅极电极222。
在凹陷第二导电层的过程中，掩膜219用于保护在管芯的非活动区中延伸的第二导电材料的部分。因此，栅极电极222在沟槽210中要比在管芯非活动区中的台面表面上更厚，如图2B中右侧截面图所示。此外，以如下方式对掩膜219进行应用，在活动区的边缘处，凹陷的栅极电极222延伸至沟槽210的外部以及非活动区的台面表面上方。因而，沟槽210中的栅极电极222被制成为可以在管芯的非活动区中电连接。应注意，掩膜219不在非活动区域中的整个屏蔽电极214上方延伸。我们将看到，这会有利于穿过相同接触开口而将栅极电极和屏蔽电极接触。
在图2E中，运用传统的体植入和驱动技术(body implant anddrive in techniques)在半导体区域202中形成p-型体区204。然后，运用传统的源极植入技术在邻近沟槽210的体区域216中形成重掺杂的n-型源极区208。
在图2F中，运用已知技术，在本结构上方形成诸如BPSG的介电层224。在图2G中，介电层224形成图案并蚀刻，以在活动区中形成源极/体接触开口，之后跟随有介电流(dielectric flow)。如左侧截面图中所示，形成完全在栅极电极222上方以及部分在源极区208上方延伸的介电顶罩(dome)225。然后运用传统的植入技术在暴露的半导体区域202中形成P-型重体(heavy body)区域206。在活动区中形成接触开口的相同掩膜/蚀刻处理被用来在非活动区的介电层224中形成接触开口221，以暴露栅极电极222的表面区域和侧壁以及屏蔽电极214的表面区域，如右侧截面图中所示。
在图2H中，在该结构上方形成互联(interconnect)层(例如，包含金属)，然后形成图案，以形成源极/体互联226A和栅极互联226B。如左侧截面图中所示，源极/体互联226A与源极区208和重体区106接触，但通过使用介电顶罩而与栅极电极222隔离。如右侧截面图中所示，栅极金属226B经过接触开口211与屏蔽电极214和栅极电极222接触，从而，使两个电极彼此短接。
因此，与传统的屏蔽栅极FET(其中，屏蔽电极漂移(例如，是在电学上未偏置的)或向源极电势偏置(例如，地电势))相反，在图2H中示出的FET实施例中，屏蔽电极连接至并偏置至于栅极电极相同的电势。在传统FET中，其中，屏蔽电极漂移或连接至地电势，特别需要一种高质量的IED来支持屏蔽电极和栅极电极之间的电势差。然而，将屏蔽电极和栅极电极电连接在一起就消除了对高质量IED的需要。虽然想栅极电势偏置，但屏蔽电势仍用作可以使相同截止电压的导通阻抗减少的充电平衡结构。因此，在去除了与形成高质量IED相关的处理步骤的同时，获取用于相同截止电压的低导通阻抗。理论上，这种结构甚至不需要IED，但IED会在审计介电形成的过程中自然形成。因此，使用简单的制造工艺可以形成高性能的晶体管。
栅极电极和屏蔽电极之间的电接触可以形成在任何非活动区中，诸如有栅极滑槽伸展的管芯的终端或边缘区域，或管芯的中部，如图3所示。图3是根据本发明实施例的屏蔽栅极沟槽FET中的栅极滑槽部分的等比例图。上层(例如，栅极互联层326B和介电层324)被削去以显示下部的结构。如图所示，在活动区341中平行延伸的沟槽310终止于栅极滑槽340的任一侧。
栅极滑槽区域340在结构上关于直线3-3对称，其中每一般均在结构上类似于图2H中示出的栅极滑槽(runner)区域。屏蔽电介质312延伸至该行沟槽310的外部，并延伸至栅极滑槽区域340的台面表面上。同样，屏蔽电极314、极间电介质316和栅极电极322均延伸至该行沟槽310的外部，并延伸至栅极滑槽区域340的台面表面上。区域311表示活动区341中邻近沟槽之间的台面。
接触开口321暴露屏蔽电极314的表面区域，其中栅极互联层326B(例如，包含金属)与屏蔽电极有电接触。此外，栅极互联层326B与经介电层324暴露的栅极电极322有电接触。我们期望将栅极阻抗最小化，以将对沟槽中的单个栅极电极进行偏置的延迟最小化。由于同样的原因，我们期望将对沟槽中的单个屏蔽电极进行偏置的延迟最小化。因此，可以优选栅极滑槽区域340中的接触开口321的频率和形状，并将阻抗最小化，从而将从栅极焊点到每个栅极电极和屏蔽电极的延迟最小化。可以通过对栅极滑槽区域中以及管芯的终端或边缘区域中的接触点形成栅极电极，来进一步减小偏置屏蔽电极和栅极电极的延迟。
屏蔽和栅极电极可以以根据本发明其他实施例的其他方法进行电连接。例如，在IED上放形成栅极电极之前，每个沟槽中的IED可以蚀刻在特定位置。在本实施例中，图2H和3中示出的接触开口不是必需的，而至每个沟槽中的栅极电极的栅极互联接触点也可以经过IED中的短路而连接至对应的屏蔽电极。根据其他实施例，可以通过IED中的开口以及通过形成在诸如终端或栅极滑槽区域的非活动区域的接触开口来形成栅极和屏蔽电极接触点。为了消除形成高质量IED的需要，我们得到了简化的、更为可控的、用于形成含改进的漏源导通阻抗RDSon的屏蔽栅极沟槽MOSFET的过程。
本发明的原理可以应用于诸如在专利申请第11/026,276号，题为“功率半导体器件和制造方法(Power Semiconductor Devices andMethods of Manufacture)”的图3A、3B、4A、4C、6-8、9A-9C、11、12、15、16、24以及26A-26C中示出的任意屏蔽栅极FET结构，该专利的公开通过引证结合在此。
尽管上文提供了本发明优选实施例的完成说明，我们仍可以对本发明做选择、修改、以及等效替换。本领域技术人员应理解，相同的技术可以应用至其他类型的超结结构且可以广泛用于包含后面的器件的其他种类的器件。例如，当在n-沟道MOSFET的内容中描述本发明的实施例时，本发明的原理可以仅通过将多种区域的导电类型翻转而应用于p-沟道MOSFET。因此，上述说明不是为了限制本发明的范围，该范围有所附权利要求进行限定。

Claims (30)

1.一种场效应晶体管(FET)，包括：
沟槽，延伸进入半导体区域；
屏蔽电极，位于所述沟槽下部，所述屏蔽电极通过屏蔽电介质而与所述半导体区域隔离；
极间电介质(IED)，位于所述屏蔽电极上方；以及
栅极电极，位于所述IED上方的所述沟槽上部，所述栅极电极通过栅极电介质而与所述半导体区域隔离，其中，所述屏蔽电极电连接至所述栅极电极。
2.根据权利要求1所述的FET，其中，所述半导体区域包括：
第一导电型的漂移区；
第二导电型的体区域，延伸至所述漂移区上方；
第一导电型的源极区，位于邻近所述沟槽的体区域中。
3.根据权利要求2所述的FET，其中，所述栅极电极凹陷进入所述半导体区域的顶部表面的下方，所述FET进一步包括：
互联层，使所述源极区与所述体区域接触；以及
介电材料，位于所述栅极电极上方，用于使所述栅极电极与所述互联层彼此隔离。
4.根据权利要求2所述的FET，进一步包括所述第一导电型的衬底，所述漂移区在所述衬底上方延伸，其中，所述沟道经由所述体区域延伸并终止于所述漂移区中。
5.根据权利要求2所述的FET，进一步包括所述第一导电型的衬底，所述漂移区在所述衬底上方延伸，其中，所述沟道经由所述体区域和所述漂移区延伸并终止于所述衬底中。
6.根据权利要求1所述的FET，进一步包括：活动区，其中形成有所述沟槽；以及非活动区，所述屏蔽电极和所述栅极电极延伸至所述沟槽外且延伸进入所述非活动区，在所述非活动区中，所述屏蔽电极和所述栅极电极通过栅极互联层而电连接在一起。
7.根据权利要求6所述的FET，其中，所述屏蔽电极与所述栅极电极之间的电连接是经由形成于所述非活动区的栅极滑槽区中的周期性接触开口而进行的。
8.根据权利要求6所述的FET，其中，所述屏蔽电极通过经由所述沟槽中IED的附加连接而电连接至所述栅极电极。
9.根据权利要求1所述的FET，其中，所述栅极电极经由所述沟槽内IED中的至少一个开口而电连接至所述屏蔽电极。
10.根据权利要求1所述FET，还包括：活动区，其中形成有所述沟槽；以及非活动区，其包括沿容纳所述FET的管芯的周围延伸的终止区，所述屏蔽电极和所述栅极电极延伸至所述沟槽外且延伸进入所述终止区，其中，所述屏蔽电极和所述栅极电极通过栅极互联层而电连接在一起。
11.根据权利要求10所述FET，其中，所述屏蔽电极和所述栅极电极之间的电连接是经由所述终止区中的一个或多个接触开口而进行的。
12.一种半导体管芯中的场效应晶体管(FET)，包括：
活动区，容纳(请替换)活动单元；
非活动区，其中具有非活动单元；
第一导电型的漂移区；
第二导电型的体区域，位于所述漂移区上方；以及
多个沟槽，延伸通过所述体区域并进入所述漂移区，每个沟槽包括屏蔽电极和栅极电极，所述屏蔽电极配置于所述栅极电极下方；
其中，所述屏蔽电极和所述栅极电极延伸至每个沟槽外且延伸进入所述非活动区，在所述非活动区中，所述屏蔽电极和所述栅极电极通过栅极互联层而电连接在一起。
13.根据权利要求12所述FET，其中，所述半导体区域包括：
所述第一导电型的源极区，位于邻近所述沟槽的体区域中，以及
所述第二导电型的重体区域，位于邻近所述源极区域的体区域中。
14.根据权利要求13所述FET，其中，所述栅极电极在所述沟槽中凹陷以低于所述源极区域的顶部表面，所述FET进一步包括：
互联层，使所述源极区与所述重体区域接触；以及
介电材料，位于所述栅极电极上方，用于使所述栅极电极与所述互联层彼此隔离。
15.根据权利要求12所述FET，进一步包括所述第一导电型的衬底，所述漂移区延伸至所述衬底上方，其中，所述沟道延伸通过所述体区域并终止于所述漂移区中。
16.根据权利要求12所述的FET，进一步包括所述第一导电型的衬底，所述漂移区在所述衬底上方延伸，其中，所述沟道经所述体区域和所述漂移区延伸并终止于所述衬底中。
17.根据权利要求12所述的FET，进一步包括极间电介质，位于每个沟槽中的所述屏蔽电极和所述栅极电极之间，其中，所述屏蔽电极通过经由所述极间电介质的附加连接而电连接至所述栅极电极。
18.根据权利要求12所述的FET，其中，所述非活动区包括栅极滑槽区域，所述栅极滑槽区域延伸通过所述管芯的中部，所述屏蔽电极和所述栅极电极延伸至所述沟槽外且延伸进入所述栅极滑槽区域，其中，所述屏蔽电极和所述栅极电极通过所述栅极互联层而电连接在一起。
19.根据权利要求12所述的FET，其中，所述非活动区包括终止区，所述终止区沿所述管芯的周围延伸，所述屏蔽电极和所述栅极电极延伸至所述沟槽外且延伸进入所述终止区，其中，所述屏蔽电极和所述栅极电极通过所述栅极互联层而电连接在一起。
20.一种场效应晶体管(FET)，包括延伸进入半导体区域的多个沟槽，每个沟槽均具有栅极电极和屏蔽电极，所述栅极电极和所述屏蔽电极之间含有极间电介质，其中，所述屏蔽电极和所述栅极电极电连接在一起。
21.一种形成场效应晶体管(FET)的方法，包括：
在半导体区域中形成沟槽；
形成衬附于所述沟槽的下部侧壁和底部表面的屏蔽介电层；
在所述沟槽的下部形成屏蔽电极；
沿上部沟槽侧壁和所述屏蔽电极上方形成介电层；
在所述屏蔽电极上方的沟槽中形成栅极电极；以及
形成用于连接所述栅极电极和所述屏蔽电极的互联层。
22.根据权利要求21所述的方法，其中，形成所述屏蔽电极和所述栅极电极，以使所述屏蔽电极和所述栅极电极延伸至所述沟槽外部以及台面区域的上方，所述方法进一步包括：
在所述栅极电极中形成多个接触开口，以便经由所述接触开口暴露所述屏蔽电极的表面区域，其中，所述互联层填充所述接触开口，从而使所述屏蔽电极和所述栅极电极彼此电连接。
23.根据权利要求22所述的方法，其中，所述台面区域是用于覆盖所述FET的管芯的非活动区域。
24.根据权利要求21所述的方法，其中，所述介电层由硅的氧化物形成。
25.根据权利要求21所述的方法，其中，所述半导体区域包括位于所述第一导电型的衬底上方的第一导电型的外延层，所述方法进一步包括：
在所述外延层中形成第二导电型的体区域；
在邻近所述沟槽的体区域中形成所述第一导电型的源极区；以及
在邻近所述源极区的体区域中形成所述第二导电型的重体区域。
26.根据权利要求21所述的方法，还包括，在形成所述栅极电极之前，在延伸至所述屏蔽电极上方的介电层的部分中形成一个或多个开口，从而一旦在所述沟槽中形成所述栅极电极，所述栅极电极就经由所述一个或多个开口而与所述屏蔽电极电接触。
27.一种在半导体管芯中形成场效应晶体管(FET)的方法，所述管芯包括活动区和非活动区，所述方法包括以下步骤：
在所述管芯的活动区中形成多个沟槽，所述多个沟槽延伸进入半导体区域；
在所述管芯的非活动区中形成第一多晶硅层，用于填充每个沟槽并延伸至台面区域的上方；
使所述第一多晶硅层凹陷进入每个沟槽，以便在每个沟槽的底部形成屏蔽电极，每个沟槽中的屏蔽电极保持与所述第一多晶硅层的延伸进入所述台面区域的部分的连续性；
由硅的氧化物形成介电层，以使所述介电层位于：(i)每个沟槽的暴露的上部侧壁，(ii)每个屏蔽电极的上表面，以及(iii)所述第一多晶硅层的位于所述台面区域中的表面区域；
在所述台面区域中形成第二多晶硅层，用于填充每个沟槽并延伸至所述介电层上方；
使所述第二多晶硅层凹陷进入每个沟槽，以便在每个沟槽的上部中形成栅极电极，每个沟槽中的栅极电极保持与所述第二多晶硅层的延伸进入所述台面区域的部分的连续性；
在延伸进入所述台面区域的第二多晶硅层和介电层的部分中形成一个或多个接触开口，以便经由所述接触开口暴露所述第一多晶硅层的表面区域；以及
形成栅极互联层，用于填充所述一个或多个接触开口，从而使所述第一多晶硅层和所述第二多晶硅层电接触在一起。
28.根据权利要求27所述的方法，进一步包括：
在形成所述第一多晶硅层之前，形成屏蔽介电层，所述屏蔽介电层位于每个沟槽的侧壁和底部并延伸至所述台面区域上方；以及
在使所述第一多晶硅层凹陷进入每个沟槽之后，使所述屏蔽介电层凹陷至每个沟槽中，以便暴露每个沟槽的上部侧壁。
29.根据权利要求27所述的方法，其中，所述半导体区域包括第一导电型的外延层，所述外延层位于所述第一导电型的衬底上方，所述方法进一步包括：
在所述外延层中形成第二导电型的体区域；
在邻近每个沟槽的体区域中形成所述第一导电型的源极区；以及
在邻近所述源极区的体区域中形成所述第二导电型的重体区域。
30.一种形成场效应晶体管(FET)的方法，包括：
形成多个沟槽，所述沟槽延伸进入半导体区域；
在每个沟槽的底部形成屏蔽电极；
在所述屏蔽电极上方的每个沟槽上部形成栅极电极；以及
形成栅极互联层，用于将所述屏蔽电极和所述栅极电极电连接。
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MY147032A (en) 2012-10-15
US20110204436A1 (en) 2011-08-25
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