CN101496150B - 控制外延层形成期间形态的方法 - Google Patents
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910000077 silane Inorganic materials 0.000 claims abstract description 35
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
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- 239000000460 chlorine Substances 0.000 claims description 10
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 9
- 229910052801 chlorine Inorganic materials 0.000 claims description 9
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 9
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- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明的第一方面是提供一种在基材上选择性形成外延层的方法。此方法包含加热所述基材至低于约800℃的一温度;以及在所述外延膜形成过程中,一并使用硅烷与二氯甲硅烷作为硅源。本发明亦提供其它各式的方面。
Description
本申请要求2006年7月31日提交的美国临时专利申请第60/820956号的优先权,该申请的全文结合在此作为参考。
相关申请的对照
本申请涉及以下共同待审的申请,下列申请的全文结合在此作为参考。
2004年12月1日提交的美国专利申请第11/001774号(代理人案号9618);以及
2005年9月14日提交的美国专利申请第11/227974号(代理人案号9618/P01)。
技术领域
本发明关于半导体器件的制造,更具体地,关于控制外延层成长期间形态的方法。
背景技术
随着小型晶体管的制造,要生产超浅源/漏极结变得更具挑战性。一般而言,次100纳米(sub-100nm)的互补性金属氧化物半导体(Complementary Metal-OxideSemiconductor;CMOS)器件,所要求的结深度需小于30nm。常利用选择性的外延沉积(selective epitaxial deposition),将含硅材料(例如硅、硅锗或碳化硅)的外延层形成于结中。一般而言,选择性外延沉积能够让外延长在硅沟(silicon moats)上,而非长在介电区上。选择性外延可用于半导体器件,例如提高源/漏极、源/漏极延展、接触插塞或双极性器件的基层沉积。
一般而言,选择性外延工艺牵涉到沉积反应与蚀刻反应。沉积反应与蚀刻反应是同时发生,但对于外延层与多晶质层则具有不同的反应速率。在沉积的过程中,外延层形成于一单晶质层表面,而多晶质层则沉积于至少第二层(例如已有的多晶质层及/或非晶质层)上。然而,所沉积的多晶质层的蚀刻速率通常较外延层快。因此,通过改变蚀刻气体的浓度,净选择工艺的结果为外延材料的沉积,同时限制了或并无多晶质材料的沉积。举例而言,选择性外延工艺会在单晶硅表面上形成含硅材料的外延层,而于间隙壁上无任何沉积。
在形成提高源/漏极与源/漏极延展的特征时,例如在形成含硅的金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)器件时,含硅材料的选择性外延沉积技术具有相当助益。源/漏极延展的制造方式,是先蚀刻硅表面以制造出嵌壁式的源/漏极特征,再利用选择性成长的外延层,例如硅锗(silicon germanium,SiGe)材料,填入蚀刻后的表面。选择性外延能以内掺杂(in-situ doping)近乎完全的掺杂活化(dopant activation),进而省略后续的回火工艺。因此,可通过硅蚀刻与选择性外延准确地定义出结深度。另一方面,超浅源/漏极无可避免地会导致串联电阻的增加。此外,在形成硅化物过程中的结消耗(junction consumption),会进一步地提高串联电阻。为了弥补结消耗,可于结上外延地且选择性地成长提高的源/漏极。一般而言,提高的源/漏极层为未掺杂硅。
然而,现有选择性外延工艺具有某些缺点。为了在现今的外延工艺中维持选择性,因此前体的化学浓度以及反应温度必须在沉积过程中全程控管与调整。若未提供足够的硅前体,蚀刻反应则会居于主要,并延滞整个工艺。此外,亦可能发生对基材特征有害的过度蚀刻。若未提供足够的蚀刻前体,沉积反应则会居于主要,降低在基材表面形成单晶质与多晶质材料的选择性。另外,现今选择性外延工艺需以高反应温度进行,例如800℃、1000℃或更高。但由于热预算(thermal budget)的考量,且于基材表面可能有难以控制的氮化反应,在工艺过程中,此高温反应乃是不利的。
因此,仍待开发需一种工艺,可选择性且外延地沉积具有选择性掺杂物的硅与含硅化合物。此外,在具有快速沉积速率、平滑表面形态且工艺温度维持于例如约800℃或更低时以及优选地约700℃或更低时,此工艺需能与各种元素浓度形成含硅化合物。
发明内容
本发明的第一方面是提供一种于基材上选择性形成外延层的方法。此方法包含将所述基材加热至低于约800℃的一温度,并于该选择性外延膜形成工艺中,一并使用硅烷与二氯甲硅烷作为硅源。
本发明的另一方面提供一种于基材上选择性形成外延层的方法。此方法包含轮流交替至少一个沉积步骤与至少一个蚀刻步骤。所述方法包括将所述基材加热至低于约800℃的一温度。所述沉积步骤一并使用硅烷与二氯甲硅烷作为硅源。在室压约为5-50Torr下,以约10sccm至100sccm的流速流入每一硅源气体。该蚀刻步骤包含流入氯化氢与氯气中的至少一个。
在本发明的另一方面中,提供一种于基材上形成外延层的方法。此方法包含:(1)加热所述基材至低于约800℃的一温度;以及(2)于所述基材上进行一选择性外延膜形成工艺,于该选择性外延膜形成工艺中,一并使用硅烷与二氯甲硅烷作为硅源,以便形成该外延层。硅烷对二氯甲硅烷的比例大于1。本发明亦提供其它各式的方面。
依据下述的实施方式、申请专利范围与所附图表,可使本发明其它特征与方面更为清楚。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂,附图的详细说明如下:
图1是绘示依据本发明的一个实施例,用以形成外延膜的第一示范方法的流程图。
图2是绘示依据本发明的一个实施例,用以形成外延膜的第二示范方法的流程图。
具体实施方式
在以介电膜图案化的硅基材上的选择性外延成长过程中,仅于暴露的硅表面上(例如,不在介电表面上)形成单晶半导体。所谓的选择性厚度则定义为在膜成长开始或在介电表面成核之前,硅表面所获得的最大膜厚度。
选择性外延成长的过程可包含同时进行的蚀刻-沉积工艺,亦或气体交替供应工艺。在同时进行的蚀刻-沉积工艺中,蚀刻剂与沉积物两者同时流动。据此,在形成外延层的过程中,沉积与蚀刻为同时发生。
在美国专利申请案号11/001,774一案中(申请日2004年12月1日,代理人案号9618),则描述了以气体交替供应(alternating gas supply,AGS)于基材上形成外延层的工艺。在AGS工艺中,则是先于基材上进行外延沉积工艺,然后在于基材上进行蚀刻工艺。此种外延沉积工艺续以蚀刻工艺的循环则不断重复,直至形成所需的外延层厚度为止。
当沉积温度小于800℃时,硅烷(silane,SiH4)可作为选择性硅外延的另一种前体。在此较低温度下,硅烷的成长速率比二氯甲硅烷(Dichlorosilane,DCS)高。然而,本发明的发明人却观察到以硅烷为基础的工艺可能会产生形态上的问题(例如表面粗糙或坑洞)。
在本发明的至少一个实施例中,通过一并使用硅烷与二氯甲硅烷(例如于膜成长时,混合硅烷与二氯甲硅烷),可降低及/或消除与使用硅烷有关而观察到的形态问题。相信此方法改变膜表面上的扩散机制,提供较大的形态控制。
虽然本发明可与其它选择性外延工艺一并使用,但在部份实施例中,本发明可与美国专利申请案号11/001,774一案中(申请日2004年12月1日,代理人案号9618),所述的AGS工艺一同施行。
利用仅以硅烷作为硅源的选择性工艺(例如在AGS工艺中)所形成的硅外延膜,已发现表面粗糙且有凹洞。利用硅烷与二氯甲硅烷两者作为硅源的选择性工艺(例如在AGS工艺中)所形成的硅外延膜,已发现具有改善的膜形态,例如改善的表面平滑(例如没有凹洞)。不同于其它方法(例如后沉积平化步骤),不需额外的工艺步骤,使用硅烷与二氯甲硅烷可实时控制膜形态(例如在外延膜形成过程期间)。
在部份实施例中,如上述使用硅源的工艺的示例可包含流速约10sccm到约100sccm硅烷。此外,硅源可包含流速约10sccm到约100sccm的二氯甲硅烷。在此示例中,在AGS工艺中的沉积循环过程中,可采用约5Torr到50Torr的室压范围,而沉积时间约为2-250秒,且较佳约为5-10秒,以及介于约700℃至约750℃之间的温度范围。在部份实施例中,硅烷与二氯甲硅烷的比例可大于1,例如为2∶1,3∶1,4∶1,5∶1,7∶1,10∶1等(硅烷∶二氯甲硅烷)。在沉积循环之后,可进行蚀刻工艺,举例而言,以流速约50sccm至约500sccm的氯化氢(HCl)作为蚀刻剂,约5Torr到100Torr的室压范围,而沉积时间约为2-250秒,且较佳约为5-10秒,以及介于约700℃至约750℃之间的温度范围。在蚀刻循环后,可于约5Torr至50Torr的压力下,温度范围介于约700℃至750℃之间,进行约10秒的清洁循环。在沉积、蚀刻及/或清洁过程中,亦可使用其它的工艺时间、温度及/或流速。举例而言,可如在美国专利申请案号11/227,794(申请日2005年09月14日,代理人案号9618/P01)一案中所述,在每一蚀刻步骤中,使用氯气(Cl2)或氯气与氯化氢的组合。
图1为依据本发明,用以形成外延膜的第一示范方法100的流程图。参照图1,在步骤101中,将基材放入处理室中,并将基材加热至约800℃或低于800℃。在部份实施例中,在外延膜形成过程中,可使用较低温度范围,例如低于750℃,低于700℃或低于650℃。
在步骤102中,硅烷与二氯甲硅烷则与适用的载流气体及/或掺杂物一起流入处理室中,以便于基材上形成外延膜。在部份实施例中,一种或多种蚀刻气体(例如氯化氢、氯气、氯化氢与氯气的组合等)可与硅源气体在相同的时间一起流入(例如在同时进行的沉积-蚀刻工艺过程中)。在其它实施例中,可于沉积之后,采用分开的蚀刻步骤(例如于AGS工艺中)。沉积与蚀刻步骤则持续进行,直至达到所需的外延膜厚度为止。在部份实施例中,所采用的硅烷与二氯甲硅烷的比例可大于1,例如为2∶1,3∶1,4∶1,5∶1,7∶1,10∶1等(硅烷∶二氯甲硅烷)。亦可使用其它的硅源比例。
图2为依据本发明,用以形成外延膜的第二示范方法200的流程图。参照图2,在步骤201中,将基材放入处理室中,并将基材加热至约800℃或低于800℃。在部份实施例中,在外延膜形成过程中,可使用较低温度范围,例如低于750℃,低于700℃或低于650℃。
在步骤202中,硅烷与二氯甲硅烷则与适用的载流气体及/或掺杂物一起流入处理室中,以便在基材上形成外延膜。在部份实施例中,可使用流速约为10sccm至约100sccm的硅烷,随着流速约为10sccm至约100sccm的二氯甲硅烷。可采用约5Torr至约50Torr的压力范围。进行约2-250秒的沉积,且较佳为5-10秒。在部份实施例中,硅烷与二氯甲硅烷的比例可大于1,例如为2∶1、3∶1、4∶1、5∶1、7∶1、10∶1等(硅烷∶二氯甲硅烷)。亦可采用其它流速、压力、温度、时间及/或硅烷与二氯甲硅烷比例。
在步骤203中,蚀刻气体例如氯化氢及/或氯气,则与适用的载流气体一起流入处理室中,以对在步骤202中所沉积的材料进行蚀刻。举例而言,可以流速约50sccm至约500sccm的氯化氢作为蚀刻剂,处理室压力约5Torr到100Torr的室压范围,对基材进行蚀刻,而蚀刻时间约为2-250秒,且较佳约为5-10秒。亦可使用其它蚀刻剂、流速、压力及/或时间。
在步骤204中,在蚀刻循环后,进行约2-250秒的清洁循环,且较佳为约5-10秒。亦可使用其它的清洁时间。
在步骤205中,则确认是否达到所需的外延膜厚度。若达到,则在步骤206终止工艺。否则的话,工艺则回到步骤202,以在基材上沉积额外的外延材料。
前述揭示仅作为本发明的示范实施例。任何熟习此技艺者,在不脱离本发明的精神和范围内,可对前述所揭示的装置与方法可作各种的更动与润饰。举例而言,在外延膜形成过程中,可使用较低的温度范围,例如低于750℃,低于700℃,或小于650℃。
据此,虽然本发明已以实施例揭露如上,然其并非用以限定本发明,其它实施例亦可能落入本发明的精神与范围下,如后权利要求书所界定。
Claims (21)
1.一种形成外延层的方法,所述方法包含:
提供基材;
加热所述基材至低于约800℃的温度;以及
在所述基材上进行选择性外延膜形成工艺,在所述选择性外延膜形成工艺中,一并使用硅烷与二氯甲硅烷作为硅源,以便形成所述外延层;
其中进行所述选择性外延膜形成工艺包含:进行沉积步骤,且在所述沉积步骤后进行蚀刻步骤;
其中进行所述沉积步骤包含提供硅烷流以及二氯甲硅烷流;
其中进行所述沉积步骤包含流入长达约10秒的硅烷与二氯甲硅烷。
2.如权利要求1所述的方法,其中加热所述基材包含将所述基材加热至低于约750℃的温度。
3.如权利要求1所述的方法,其中加热所述基材包含将所述基材加热至低于约700℃的温度。
4.如权利要求1所述的方法,其中加热所述基材包含将所述基材加热至低于约650℃的温度。
5.如权利要求1所述的方法,其中进行所述选择性外延膜形成工艺包含:
流入硅烷与二氯甲硅烷;以及
流入蚀刻气体,所述蚀刻气体包含氯化氢与氯气中的至少一种。
6.如权利要求1所述的方法,其中所述硅烷的流速为约10-100sccm。
7.如权利要求1所述的方法,其中该二氯甲硅烷的流速为约10-100sccm。
8.如权利要求1所述的方法,其中进行所述沉积步骤包含使用约5-50Torr的工艺压力。
9.如权利要求1所述的方法,其中进行所述蚀刻步骤包含流入蚀刻气体,其中所述蚀刻气体包含氯化氢与氯气中的至少一种。
10.如权利要求9所述的方法,其中所述蚀刻气体的流速约为50-500sccm。
11.如权利要求9所述的方法,其中进行所述蚀刻步骤包含采用约5-100Torr的工艺压力。
12.如权利要求9所述的方法,其中所述蚀刻步骤包含流入长达约10秒的蚀刻气体。
13.如权利要求1所述的方法,更包含至少一个清洁步骤。
14.一种形成外延层的方法,所述方法包含:
提供基材;
加热所述基材至低于约800℃的温度;
进行选择性外延膜形成工艺,所述选择性外延膜形成工艺包含至少一个沉积步骤与至少一个蚀刻步骤:
其中在所述至少一个沉积步骤后进行所述至少一个蚀刻步骤;
其中所述沉积步骤与所述蚀刻步骤轮流交替;
其中所述沉积步骤包含在约为5至50Torr的沉积压力下,以约10sccm至100sccm的流速流入硅烷与二氯甲硅烷;以及
其中所述蚀刻步骤包含流入长达约10秒的氯化氢与氯气中的至少一种。
15.如权利要求14所述的方法,其中所述选择性外延膜形成工艺更包含至少一个清洁步骤。
16.如权利要求14所述的方法,其中加热所述基材包含将所述基材加热至低于约750℃的温度。
17.如权利要求14所述的方法,其中加热所述基材包含将所述基材加热至低于约700℃的温度。
18.如权利要求14所述的方法,其中加热所述基材包含将所述基材加热至低于约650℃的温度。
19.一种形成外延层的方法,所述方法包含:
提供基材;
加热所述基材至低于约800℃的温度;以及
在所述基材上进行选择性外延膜形成工艺,在所述选择性外延膜形成工艺中,一并使用硅烷与二氯甲硅烷作为硅源,以便形成所述外延层;
其中硅烷对二氯甲硅烷的比例大于1。
20.如权利要求19所述的方法,其中硅烷对二氯甲硅烷的比例大于2。
21.如权利要求20所述的方法,其中硅烷对二氯甲硅烷的比例大于5。
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-
2007
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- 2007-07-30 WO PCT/US2007/017053 patent/WO2008033186A1/en active Application Filing
- 2007-07-30 CN CN2007800284868A patent/CN101496150B/zh active Active
- 2007-07-30 DE DE112007001813T patent/DE112007001813T5/de not_active Withdrawn
- 2007-07-30 JP JP2009522826A patent/JP5175285B2/ja not_active Expired - Fee Related
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WO2008033186A1 (en) | 2008-03-20 |
DE112007001813T5 (de) | 2009-07-09 |
US20080026549A1 (en) | 2008-01-31 |
US7588980B2 (en) | 2009-09-15 |
CN101496150A (zh) | 2009-07-29 |
KR101369355B1 (ko) | 2014-03-04 |
JP2009545884A (ja) | 2009-12-24 |
JP5175285B2 (ja) | 2013-04-03 |
TWI390606B (zh) | 2013-03-21 |
TW200816280A (en) | 2008-04-01 |
KR20090037481A (ko) | 2009-04-15 |
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