CN101540305B - 半导体封装及其工艺 - Google Patents

半导体封装及其工艺 Download PDF

Info

Publication number
CN101540305B
CN101540305B CN2009101274968A CN200910127496A CN101540305B CN 101540305 B CN101540305 B CN 101540305B CN 2009101274968 A CN2009101274968 A CN 2009101274968A CN 200910127496 A CN200910127496 A CN 200910127496A CN 101540305 B CN101540305 B CN 101540305B
Authority
CN
China
Prior art keywords
protuberance
chip
semiconductor chip
metal
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2009101274968A
Other languages
English (en)
Other versions
CN101540305A (zh
Inventor
张简宝徽
胡平正
陈建文
李旭阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN101540305A publication Critical patent/CN101540305A/zh
Application granted granted Critical
Publication of CN101540305B publication Critical patent/CN101540305B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Abstract

一种半导体封装及其工艺，封装体包括芯片座、多个引脚、芯片以及封装胶体。芯片座包括上倾斜部、下倾斜部以及以具有中心部的凹穴底部定义凹穴的周围边缘区域。每一引脚具有上倾斜部与下倾斜部。芯片配置于凹穴底部的中心部且电性连接至引脚。封装胶体形成于芯片与引脚上，且实质上填满凹穴并实质上覆盖芯片座与引脚的上倾斜部。芯片座与引脚的下倾斜部至少部份延伸至封装胶体的下表面。

Description

半导体封装及其工艺
技术领域
本发明是有关于一种半导体芯片封装，且特别是有关于一种具有一凹穴结构的进阶式四方扁平无引脚封装(advanced Quad Flat No Lead，aQFN)及其工艺。
背景技术
由于使用者对于小尺寸芯片的处理能力的需求越来越大，因此半导体芯片也变得更加复杂。为了解决上述问题，封装技术逐渐发展，举例而说，由增加引脚密度来降低一封装体固定在一印刷电路板上的覆盖面积。此外，有些封装技术，例如四方扁平无引脚封装(Quad Flat No Lead，QFN)，可由提供多行的内引脚与外引脚连接至一导线架的一可抛弃部，来增加引脚密度。然而，这类导线架的制作方式很难达成两行以外的引脚，因此当使用者对于导线架的引脚密度的需求越来越高时，如何利用封装技术来形成所需的引脚密度，实为一待解决的问题。
此外，除了增加引脚密度之外，使用者更希望能由其它的方式来降低封装体的大小，例如是降低封装体的高度。同时，也希望能维持一封装胶体与引脚之间的结合力(mold locking)，并促进封装体能由表面黏着技术接合于一印刷电路板上。当然，也可以制定一符合上述这些目的的封装工艺。然而，目前现有的封装技术只能符合上述其中一些目的，而不符合多数或是所有的目的。
发明内容
本发明的目的是提供一种半导体封装及其工艺。
为实现上述目的，本发明提供的半导体封装，其包括芯片座、多个引脚、半导体芯片与封装胶体。芯片座包括(1)具有上表面且以凹穴底部定义凹穴的周围边缘区域，其中凹穴底部具有中心部(2)配置邻接于周围边缘区域的上表面且面向凹穴的上倾斜部，以及(3)配置邻接于上倾斜部且面向凹穴的下倾斜部。这些引脚环绕芯片座。每一引脚具有上表面、下表面、配置邻接于每一引脚的上表面的上倾斜部以及配置邻接于每一引脚的下表面的下倾斜部。半导体芯片配置于凹穴底部的中心部且电性连接至这些引脚。封装胶体形成于半导体芯片与这些引脚上，以实质上填充于凹穴且实质上覆盖芯片座的上倾斜部与这些引脚的这些上倾斜部，而芯片座的下倾斜部与这些引脚的这些下倾斜部至少部分从封装胶体的下表面向外延伸。
本发明提出的半导体封装的工艺，首先，提供金属承载板。金属承载板包括(1)基部，具有上表面与下表面(2)中心突出部，具有上表面且从基部向上延伸，中心突出部定义基部的上表面的中心区域，中心区域具有中心部(3)多个周围突出部，每一周围突出部具有上表面且从基部向上延伸，并环绕中心突出部(4)第一金属镀层，形成于中心突出部的上表面上与周围突出部的上表面上，以及(5)第二金属镀层，形成于对应中心区域下方、中心突出部下方以及这些周围突出部下方的金属承载板的下表面上。接着，贴附第一半导体芯片于中心突出部。电性连接第一半导体芯片至这些周围突出部至少一第一突出部上。然后，形成封装胶体于第一半导体芯片与这些周围突出部上。最后，蚀刻第二金属镀层之外的金属承载板的下表面的区域，以使这些周围突出部与中心突出部分离而形成多个引脚与芯片座，其中芯片座包括中心突出部与中心区域，每一引脚具有配置邻接每一引脚的下表面的下倾斜部，芯片座具有配置邻接芯片座的下表面的下倾斜部，芯片座的下倾斜部与每一引脚的下倾斜部至少部分从封装胶体的下表面向外延伸。
本发明还提供一种半导体封装，其包括芯片座、多个引脚、半导体芯片以及封装胶体。芯片座包括(1)基部，具有上表面与下表面(2)突出部，从基部向上延伸且配置邻接于基部的周围边缘，其中突出部具有上表面；(3)第一侧表面，延伸介于突出部的上表面与基部的下表面之间，其中第一侧表面具有相较于突出部的上表面更接近基部的下表面的第一尖端。这些引脚环绕芯片座。至少这些引脚之一具有第二尖端的第二侧表面。第一半导体芯片，配置于基部的上表面，且电性连接至这些引脚。封装胶体形成于第一半导体芯片与这些引脚上，以实质上覆盖基部的上表面、第一尖端上方的第一侧表面的至少一部分与第二尖端上方的第二侧表面的至少一部分，而第一尖端下方的第一侧表面的至少一部分与第二尖端下方的第二侧表面的至少一部分突出于封装胶体的下表面。
附图说明
图1为本发明一实施例的一种半导体封装的剖面示意图。
图2为本发明一实施例的一种芯片座的放大剖面示意图。
图3为本发明一实施例的一种引脚的放大剖面示意图。
图4为本发明一实施例的一种金属承载板的一部分的上视图。
图5显示本发明一实施例的一种金属承载板的工艺。
图6显示本发明一实施例的一种半导体封装的工艺。
图7显示本发明一实施例的一种具有多堆叠芯片的半导体封装的工艺。
图8显示本发明一实施例的一种半导体封装进行表面黏着工艺的流程示意图。
图9显示本发明另一实施例的一种半导体封装进行表面工艺的流程示意图。
附图中主要组件符号说明
100、100a、100b封装体；101芯片座；102芯片；102a第一芯片；102b第二芯片；104、104a、104b焊线；106焊垫；108封装胶体；111凹穴；112凹穴底部；112a中心部；112b凹陷部；114周围边缘区域；116、117、126、127金属镀层；140模盖厚度；142厚度；144距离；145引脚间隔；146高度差；148隔开距离；150、151、154、155、164上表面；152、153、156、157、160下表面；162侧表面；166平面；171引脚；171A、171B外引脚；202基部；204、206距离；208侧表面；208a下倾斜部；208b尖端；208c上倾斜部；210保护层；212上表面；212a中心区域；212b凹陷部；213突出部；218上倾斜部；308侧表面；308a下倾斜部；308b尖端；308c上倾斜部；310保护层；400金属承载板；402基部(芯片放置区)；404中心突出部(周围边缘区域)；404a接地段；404b电源段；406周围突出部(周围凸块)；408角落周围突出部；410虚线；500金属承载板；500a、500b内连接部；501铜板；502上表面；504下表面；506、508光阻层；510第一曝光部；512第二曝光部；514第一金属镀层；516第二金属镀层；518、620区域；600a、600b连接封装体；700连接层；800、802焊接界面；804、806液化焊料块；808印刷电路板；900焊料；902焊料块；908印刷电路板。
具体实施方式
为让本发明的上述特征和优点能更明显易懂，以下特举实施例，并配合附图作详细说明。
图1为本发明的一实施例的一种半导体封装的剖面示意图。在本实施例中，封装体100包括一具有一周围边缘区域114的芯片座101，其中周围边缘区域114以一凹穴底部112定义出一凹穴111。周围边缘区域114可完全地环绕凹穴111，但于其它实施例中，周围边缘区域114亦可部分地环绕凹穴111。凹穴底部112具有一中心部112a。凹穴底部112也可包括一环绕中心部112a的凹陷部112b。中心部112a例如是位于凹穴底部112的中央，但当凹陷部112b的宽度不一致时，中心部112a亦可不位于凹穴底部112的中央。凹陷部112b可完全地可完全地环绕中心部112a，但于其它实施例中，凹陷部112b亦可部分地环绕中心部112a。芯片102是由一黏着层(未显示)贴附于凹穴底部112。黏着层例如是一导电黏着材料或一非导电黏着材料，其中非导电黏着材料例如是非导电环氧树脂(epoxy)。在本实施例中，芯片102贴附于中心部112a。芯片102的主动面上的多个焊垫106通过多条焊线104电性连接至这些引脚171与至少部分周围边缘区域114。这些引脚171例如是完全环绕或部分地环绕芯片座101。
图2为本发明的一实施例的一种芯片座的放大剖面示意图。在本实施例中，芯片座101具有一侧表面208，其中侧表面208可完全地或部分地延伸环绕于芯片座101的一周长。图2中，侧表面208包括一配置邻接于周围边缘区域114的一上表面151且面向凹穴111的上倾斜部208c。侧表面208也包括一配置邻接于上倾斜部208c且面向凹穴111的下倾斜部208a。周围边缘区域114亦包括一配置邻接上表面151且朝着凹穴111的上倾斜部218。芯片座101的侧表面208的上倾斜部208c与下倾斜部208a以及周围边缘区域114的上倾斜部218可以是直线或曲线，且不垂直于周围边缘区域114的上表面151。侧表面208亦包括一尖端208b。
图3为本发明的一实施例的一种引脚的放大剖面示意图。在本实施例中，引脚171包括一侧表面308，其中侧表面308可完全地或部分地延伸环绕于引脚171的一周长。于图3中，侧表面308包括一配置邻接于引脚171的一上表面155的上倾斜部308c。侧表面308亦包括一配置邻接于引脚171的一下表面157的下倾斜部308a。引脚171的侧表面308的上倾斜部308c与下倾斜部308a可以是直线或曲线，且分别不垂直于引脚的上表面155与下表面157。侧表面308亦包括一尖端308b。
请同时参考图1、图2与图3，封装胶体108形成于芯片102、芯片座101与引脚171上，以使封装胶体108实质上填充于凹穴111与实质上覆盖周围边缘区域114的上倾斜部218。封装胶体108亦实质上覆盖芯片座101的上倾斜部208c以及引脚171的上倾斜部308c。在此所述的“实质上”一词，部分是意指封装胶体108填充于具有芯片102配置于凹穴底部112的凹穴111，同时也意指封装胶体108填充于凹穴111以充份地减小或降低气泡与湿气，且覆盖芯片102、焊线104、侧表面208的上倾斜部208c、周围边缘区域114的上倾斜部218以及引脚171的上倾斜部308c，用以提供足够的保护来避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。在本实施例中，芯片座101的下倾斜部208a与引脚171的下倾斜部308a至少部分从封装胶体108的下表面160向外延伸。或者，芯片座101的下倾斜部208a或引脚171的下倾斜部308a至少部分从封装胶体108的下表面160向外延伸。
侧表面208的上倾斜部208c、周围边缘区域114的上倾斜部218以及引脚171的上倾斜部308c可显著地增加接触面积，因此除了封装胶体108与芯片座101之间的黏着力以及封装胶体108与引脚171之间的黏着力会增加之外，还可以提高封装胶体108与芯片座101及引脚171之间的结合力(mold locking)，同时亦可延长湿气扩散于封装体100内的时间与路径。
在本实施例中，侧表面208的上倾斜部208c与引脚171的上倾斜部308c实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是侧表面208的上倾斜部208c与引脚171的上倾斜部308c大体而言为凹面，例如朝着芯片座101的中心与引脚171向内环绕，但侧表面208的上倾斜部208c与引脚171的上倾斜部308c可包括不规则的表面或崎岖不平的小尖端，例如为一粗糙表面，以远离芯片座101的中心与引脚171向外环绕。举例而言，图3中引脚171的上倾斜部308c具有一整体形状，其中此整体形状朝着引脚171的中心向内环绕。同时，引脚171的上倾斜部308c是具有许多粗糙的结构。这些粗糙结构于封装时可吸引封装胶体108，因此可增加封装胶体108内的引脚171的结合力。这些粗糙结构可以藉由精准地控制蚀刻速率或其它适合的工艺来形成。同样地，芯片座101的下倾斜部208a与引脚171的下倾斜部308a实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是芯片座101的下倾斜部208a与引脚171的下倾斜部308a大体而言为凹面，例如朝着芯片座101的中心与引脚171向内环绕。举例而言，图2中引脚171的下倾斜部308a具有一整体形状，其中此整体形状朝着引脚171的中心向内环绕。同理，周围边缘区域114的上倾斜部218实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是周围边缘区域114的上倾斜部218大体而言为凹面，例如朝着周围边缘区域114的中心向内环绕。举例而言，图2中周围边缘区域114的上倾斜部218具有一整体形状，其中此整体形状朝着周围边缘区域114的中心向内环绕。
在此必须了解的是，芯片座101可以有不同于上述实施例的描述。举例来说，图2中芯片座101包括一具有一上表面212与一下表面153的基部202，突出部213具有一上表面151，且从基部202延伸向上延伸并配置邻接于基部202的一周围边缘。一侧表面208延伸介于突出部213的上表面151与基部202的下表面153之间，且包括一尖端208b。一侧表面218延伸介于突出部213的上表面151与基部202的上表面212之间。在本实施例中，基部202的上表面212包括一中心区域212a，其中芯片102配置于中心区域212a。基部202的上表面212可更包括一环绕中心区域212a的凹陷部212b。中心区域212a例如大约位于基部202的上表面212的中央，但当凹陷部212b的宽度不一致时，中心区域212a亦可不位于基部202的上表面212的中央。凹陷部212b例如是完全地环绕中心区域212a，但于其它实施例中，凹陷部212b亦可部分地环绕中心区域212a。
在此也必须了解的是，封装胶体108亦可以有不同于上述实施例的描述。举例而言，请参考图1、图2与图3，封装胶体108形成于芯片102、芯片座101与引脚171上，以使封装胶体108实质上覆盖基部202的上表面212与侧表面218。封装胶体108也实质上覆盖于尖端208b上方的至少一部分的侧表面208与尖端308b上方的至少一部分的侧表面308。在此所述的“实质上”一词，部分是意指封装胶体108覆盖于具有芯片102配置于其上表面212的基部202，同时也意指封装胶体108覆盖芯片102、焊线104、基板202的上表面212、侧表面218、尖端208b上方的部分侧表面208与尖端308b上方的部分侧表面308，用以提供足够的保护来避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。在本实施例中，尖端208b下方的至少部分侧表面208从封装胶体108的下表面160向外突出。同理，尖端308b上方的至少部分侧表面308从封装胶体108的下表面160向外突出。
请再参考图1，封装体100还包括一配置于周围边缘区域114的上表面151的金属镀层116，或者，金属镀层116亦可以配置于突出部213的上表面151上，请参考图2。封装体100还包括一配置于芯片座101的下表面153的金属镀层117，请参考图1，或者，金属镀层117亦可以配置于基部202的下表面153上，请参考图2。请再参考图1，封装体100也可以还包括一配置于引脚171的上表面155的金属镀层126以及一配置于引脚171的下表面157的金属镀层127。金属镀层116、117、126、127例如是利用有电电镀(electrolytic plating)或无电电镀(electroless plating)的方式所形成。由于芯片座101的表面与引脚171的表面贴附金属镀层116、117、126、127，因此可于打线接合工艺中有效提高焊线104的接合力，且亦可以保护芯片座101的下表面与引脚171的下表面，以避免受到氧化及其它环境条件的影响来以符合封装需求。于较佳实施例中，金属镀层116、117、126、127可包括一连接于芯片座101的表面151、153以及引脚171的表面155、157的镍层以及一覆盖镍层的金层或钯层。或者，金属镀层116、117、126、127可包括一镍合金以及一金层与一钯层两者之一或其组合。
请再同时参考图1、图2以及图3，一隔开距离148是指芯片座101的下倾斜部208a与/或引脚171的下倾斜部308a从封装胶体108的下表面160向外延伸的距离，于其它实施例中，此隔开距离148可以包括或省略金属镀层117、127的厚度。或者，隔开距离148可以参考尖端208b下方的部分侧表面208与/或尖端308b下方的部分侧表面308从封装胶体108的下表面160向外延伸的距离。芯片座101与/或引脚171从封装胶体108的下表面160向外延伸的突出部可由芯片座101与/或引脚171所暴露出的其它区域贴附焊料来提高芯片座101与引脚171于一电路板上的焊接性(solderability)。也就是说，可提高封装体100由表面黏着技术而接合于电路板上的可靠度。在一实施例中，尖端208b相对于突出部213的上表面151更接近于基板202的下表面153，尖端308b相对于引脚171的上表面155更接近于引脚171的下表面157。
于其它实施例中，隔开距离148是介于芯片座101的厚度142与/或至少一引脚171的厚度142的大约20％与大约50％之间或介于大约25％与大约45％之间，但并不以此为限。于其它实施例中，隔开距离148亦可以介于厚度142的大约5％与大约75％之间。芯片座101的厚度142可以计算从周围边缘区域114的上表面151至芯片座101的下表面153之间的距离。如果金属镀层116、117配置于芯片座101的表面151、153，厚度142可以计算从金属镀层116的上表面150至金属镀层117的下表面152之间的距离。同理，以引脚171来说，如果金属镀层126、127配置于引脚171的表面155、157，厚度142可以计算从金属镀层126的上表面154至金属镀层127的下表面156之间的距离。在此必须说明的是，许多距离是以金属镀层116、117、126、127的表面作为计算的基准。然而，如果没有金属镀层116、117、126、127的话，上述的这些距离可以以芯片座101的表面151、153或引脚171的表面155、157作为计算的基准来取得近似值。
在一实施例中，芯片座101包括金属镀层116、117的厚度142实质上等于至少一引脚171包括金属镀层126、127的厚度142，此厚度142大约为0.125毫米。在此实施例中，芯片座101与至少一引脚171突出于封装胶体108的下表面160的隔开距离148是介于大约0.025毫米与大约0.0625毫米之间或介于大约0.03毫米与大约0.05毫米之间。同样地，芯片座101的侧表面208的尖端208b实质上与引脚171的侧表面308的尖端308b等高。于其它实施例中，芯片座101的厚度142与/或至少一引脚171的厚度142可以大于或小于0.125毫米。
当隔开距离148在厚度142范围的大约20％与大约55％之间所占的百分比越大时，芯片座101与/或引脚171与封装胶体108的结合力会趋于减少，此时，封装体100由表面黏着技术而接合于一引刷电路板的可靠度会趋于增加。同时，底侧所需的蚀刻时间与蚀刻成本也会相对增加，请参考图6。也就是说，隔开距离148的选择如同一厚度142的一百分比，其可以做为上述这些因素之间取舍的交换程度。
一模盖厚度140可以参考封装胶体108的一上表面164至金属镀层116的上表面150之间的距离。同样地，以引脚171而言，模盖厚度140可以计算封装胶体108的上表面164至金属镀层126的上表面154之间的距离。如果模盖厚度140够大，芯片102与焊线104是可以被封装胶体108包覆于内。在一实施例中，模盖厚度140是介于大约0.4毫米与大约1毫米之间，例如是0.675毫米，虽然模盖厚度140在芯片102与焊线104仍然被封装胶体108包覆于内的情况下还可以更小一点。芯片102可以配置于具有凹穴111的芯片座101的凹穴底部112的中心部112a，请参考图1。或者，芯片102可以配置于基部202的上表面212的中心区域212a，请参考图2。
在图1与图2中，距离206是测量中心部112a(或中心区域212a)相对于金属镀层116的上表面150的一深度。距离204是测量凹陷部112b(或凹陷部212b)相对于金属镀层116的上表面150的一深度。在其它实施例中，距离206是介于距离204的大约55％与大约80％之间，但并不以此为限。在一实施例中，距离206大约是0.065毫米，距离204大约是0.095毫米。距离204与距离206可以大于或小于这些值，只要距离204与距离206在一极限内仍然小于芯片座101的厚度142，例如大约0.01毫米。较佳地，中心部112a(或中心区域212a)与凹陷部112b(或凹陷部212b)是蚀刻后的结果(请参考图5)，而不是利用电镀来形成周围边缘区域114(或中央突出部213)。电镀相对于后续的蚀刻工艺可能需花费成本与消耗更多时间，请参考图5。
当芯片102配置于凹穴底部112(或基部202的上表面212)时，芯片102的上表面会相对于金属镀层116的上表面150下降距离206，此时芯片102的上表面较邻近金属镀层116的上表面150，且金属镀层116的上表面150相对于芯片102的上表面较低，而每一引脚171的金属镀层126的上表面154也相对于芯片102的上表面较低。因此，模盖厚度140可以减小，以使封装体100具有较薄的封装厚度。此外，芯片102的下表面是相对邻近金属镀层117的下表面152。因此，可以提高传导芯片102所产生的热能通过芯片座101的扩散效率。
请再同时参考图1、图2与图3，一高度差146指的是通过中心部112a(或中心区域212a)的最高点的一平面166至封装胶体108的下表面160之间的距离。封装胶体108的下表面160至少大约对应于封装胶体108于凹陷部112b(或凹陷部212b)内的下表面。在本发明的一实施例中，高度差146是介于大约0.02毫米与大约0.04毫米之间，但并不以此为限。在本发明的另一实施例，金属镀层116的上表面150可配置介于距离平面116上方大约0.05毫米与大约0.08毫米之间，但并不以此为限。芯片座101的侧表面208的尖端208b与至少一引脚171的侧表面308的尖端308b可配置于平面116的下方。高度差146与尖端208b、308b相对于平面166的位置可以由蚀刻来控制，例如经由一上侧的蚀刻工艺，请参考图5。
距离144指的是封装胶体108的侧表面162至任何引脚171的侧表面308的最小距离。请参考图1，在图1中所显示的距离144如同从侧表面162至最左侧的外引脚171A的尖端308b的距离。在本发明的一实施例中，距离144是介于大约0.1毫米至大约0.3毫米之间，但本发明并不以此为限。部分的封装胶体108在左边最左侧的外引脚171A(与在右边最右侧的外引脚171B相同)可以避免于分离工艺(singulation)(请参考图6)与使用封装体100时外引脚171A、171B剥落(peeling)或分离的情形。
引脚间隔145指的是介于两相邻的引脚171中心的距离，也是指端子间距(terminal pitch)。在本发明的一实施例中，引脚间隔145是介于大约0.35毫米与0.55毫米之间，但并不以此为限。引脚间隔145可以由蚀刻来控制，例如经由一上侧的蚀刻工艺，请参考图5。
在图3中，一保护层310实质上覆盖至少这些引脚171的一的下倾斜部308a。在此所述的“实质上”一词是指保护层310覆盖至少一引脚171的下倾斜部308a来保护下方的金属以避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。封装胶体108实质上覆盖引脚171的上倾斜部308c(或于尖端308b上方的部分侧表面308)，但是不完全覆盖引脚171的下倾斜部308a(或于尖端308b下方的部分侧表面308)或至少不覆盖引脚171从封装胶体108的下表面160向外延伸的下倾斜部308a。因此，保护层310是除了引脚171的下表面157上的保护的金属镀层127之外，可用来防止或减少下方金属的氧化与腐蚀作用，其中保护层310例如是一铜或一铜合金。类似的保护层也可以应用于芯片座101的下倾斜部208a(或于尖端208b下方的部分侧表面208)。在图2中，一保护层210实质上覆盖芯片座101的下倾斜部208a。保护层210与芯片座101的侧表面153上保护的金属镀层117一同保护芯片座101下方的金属，以符合封装需求。
在一实施例中，保护层210、310可以包括一金属镀层。此金属镀层可以包括至少一锡层、一镍层与一金层。或者，金属镀层可以包括一层二个或多个上述这些金属的合金。金属镀层例如是利用浸没法(immersion)、有电电镀法(electrolytic plating)、无电电镀法(electroless plating)或其它适合的方法而贴附于下倾斜部208a、308a。
在其它实施例中，保护层210、310可以包括一焊接材料。焊接材料可以包括一焊料膏。当保护的金属镀层117、127(无焊料膏)实质上覆盖于芯片座101的下表面153与至少一引脚171的下表面157时，焊料膏可以有选择地配置于下倾斜部208a、308a。在此所述的“实质上”一词是指保护的金属镀层117、127覆盖下表面153、157来保护在下方的金属以避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。保护的金属镀层117、127也可以于蚀刻时保护下方的金属，请参考图5。或者，焊料膏可以同时配置于下倾斜部208a、308a与下表面153、157上。然后，烘干或硬化焊料膏。或者，焊料膏可以经由回焊而硬化成一焊料凸块。
在其它实施例中，保护层210、310可以包括一有机保焊层(organicsolderability preservative layer，OSP layer)。有机保焊层可由浸没法、一以有机材料为主的溶剂的漂洗法或其它适合的方法来贴附于下倾斜部208a、308a。有机材料可以是一以咪唑(imidazole)为主的材料。有机保焊层可以有选择地配置于下倾斜部208a、308a或配置于下倾斜部208a、308a二者择一、芯片座101的下表面153以及至少一引脚171的下表面157。如果有机保焊层配置于下表面153、157上，则去除有机保焊层另外的处理程序也许可以被省去。详细而言，因为当焊接芯片座101与至少一引脚171于一印刷电路板时，焊接时的温度会蒸发有机保焊层。
使用一焊接材料与/或一有机材料作为保护层210、310的一部分，至少有以下两个原因。第一，一般的焊接材料与有机材料相较于金属材料较为便宜，其中金属材料例如是镍、金与锡。第二，焊接材料与有机材料可无须使用有电电镀法或无电电镀法即可以被应用于芯片座101与至少一引脚171上，可简化保护层210、310的制作。
图4为本发明的一实施例的一种金属承载板的一部分的上视图。请参考图4，在本实施例中，金属承载板400的形成方式如图5所描述。金属承载板400包括一基部402，其中基部402具有一从基部402向上延伸的中心突出部404。在此所述的“中心”一词是指突出部404是大约位于部分金属承载板400的中心内，请参考图4。当然，图4中的部分金属承载板400可位于金属承载板400的任何位置，包括金属承载板400的接界边缘。于图4中，虽然中心突出部404是完全地延伸环绕基部402的一周长，但于其它实施例中，中心突出部404可以只有部分地延伸环绕基部402。多个周围突出部406环绕基部402配置。于图4中，虽然周围突出部406实质上完全地环绕基部402，但于其它实施例中，周围突出部406可以只有部分地延伸环绕基部402。一角落周围突出部408位于部分金属承载板400的一角落，且角落周围突出部408可以有不同于周围突出部408的外形与/或尺寸。在一封装体进行表面黏着工艺时，此角落周围突出部408可以作为一公认标记来帮助定位。
金属承载板400中画斜线的部分(404、406与408)是没有被蚀刻，也就是说，突出于金属承载板400的其它部分(包括402)是于上侧蚀刻(请参考图5)时被蚀刻。在一实施例中，周围突出部406配置至少三行在基部402的至少一侧。在下侧蚀刻(请参考图6)之后，基部402与周围突出部406彼此分开且形成芯片座101与引脚171，如同前述图1至图3所述。由于周围突出部406不需要连接至一导线架的一可抛弃部，意即周围突出部406如同一四方扁平无引脚封装(QFN)导线架的框，因此相对于习的四方扁平无引脚封装(QFN)的制作程序而言，利用图5与图6的制作程序可有效达成二行或多行的引脚171的设计。
在一实施例中，于下侧蚀刻(请参考图6)之后，中心突出部404可包括一接地段，其中一芯片(例如芯片102)由焊线(例如焊线104)电性连接至接地段。接地段可以是一包括完整中心突出部404的接地环。于其它实施例中，接地段可以是中心突出部404的一第一部分404a，一电源段可以是中心突出部404的一第二部分404b。在本实施例中，连接至接地段404a的基部402的一第一部分与连接至电源段404b的基部402的一第二部分是电性绝缘。由蚀刻法、分离法或其它适合的方式，例如沿着虚线410，来结构性地分开基部402的第一部分与基部402的第二部分，以达成电性绝缘。
在此必须了解的是，于图4所示的部分金属承载板400亦可以有以下的描述法。举例而言，金属层载板400包括一有一周围边缘区域404的一芯片放置区402。多个周围凸块406环绕芯片放置区402。
图5显示本发明的一实施例的一种金属承载板的工艺。一第一光阻层506形成于一铜板501的一上表面502上，一第二光阻层508形成铜板501的一下表面504上。第一光阻层506与第二光阻层508是利用涂布法、电镀法或其它适合的方法所形成。预先决定或选择部分的第一光阻层506与第二光阻层508来进行曝光与显影工艺，以于铜板501上形成一第一曝光部510与一第二曝光部512。第一光阻层506与第二光阻层508于曝光后所产生光化学反应，可定义为一光罩。
接着，一第一金属镀层514形成于第一曝光部510，一第二金属镀层516形成于第二曝光部512。第一金属镀层514与第二金属镀层516与前述所述的金属镀层116、117、126、127具有相同的特性，在此不再赘述。接着，掀离第一光阻层506与第二光阻层508。之后，铜板501的上表面502没有第一金属镀层514保护的区域518会被蚀刻，以形成金属承载板500。此金属承载板500包括前述所述的中心区域212a、中心突出部213与周围突出部406。或者，蚀刻后可以形成如前述的部分金属承载板500的芯片放置区402与周围凸块406。此种蚀刻操作方式指的是上侧蚀刻。
金属承载板500包括多个内连接部，例如内连接部500a、500b。每一内连接部500a(或500b)包括前述所述的中心区域212a、中心突出部213与周围突出部406。
图6显示本发明的一实施例的一种半导体封装的工艺。请参考图6，一芯片102贴附于一金属承载板500一部分的一中心区域212a(或芯片放置区402)，例如内连接部500a、500b，其中每一芯片102是利用如同前述所说明的一黏着层(未显示)来贴附。接着，每一芯片102由焊线104电性连接至周围突出部406(或周围凸块406)。接着，一封装胶体108形成于每一芯片102与每一周围突出部406上。封装胶体108材料例如是由人造树脂(synthetic resin)的所组成，且由注模成形法所形成，其中注模成形法例如是移转注模成形法(transfer molding)。接着，蚀刻金属承载板500的下表面没有保护的金属镀层516的区域620来分离周围突出部406与中心突出部213，以形成前述所述的引脚171与芯片座101。此种蚀刻操作方式指的是下侧蚀刻。引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。分离工艺可由例如锯切处理来形成具有垂直侧表面的封装体100a、100b，请参考图6。
图7显示本发明的一实施例的一种具有多堆叠芯片的半导体封装的工艺。一第一芯片102a贴附于一金属承载板500的一部分的一中心区域212a(或芯片放置区402)，例如内连接部500a、500b，其中每一第一芯片102a是利用如同前述所说明的一黏着层(未显示)来贴附。然后，每一第一芯片102a由焊线104a电性连接至中心突出部213(或周围边缘区域114)至少一部分。在其它实施例中，每一第一芯片102a可以电性连接至一或多个周围突出部406。
接着，一连接层700配置于每一第一芯片102a的上表面。接着，一第二芯片102b由连接层700接合至每一第一芯片102a的上表面。每一第二芯片102b可由焊线104b电性连接至周围突出部406。于其它实施例中，每一第二芯片102b可以电性连接中心突出部213的至少一部份。第二芯片102b所连接的任何周围突出部406或部分中心突出部213是与对应的第一芯片102b所连接的周围突出部406或部分中心突出部213电性绝缘。
接着，封装胶体108形成于每一堆叠的第一芯片102a与第二芯片102b以及周围突出部406上。接着，蚀刻金属承载板500的下表面没有保护的金属镀层516的区域620来分离周围突出部406与中心突出部213，以形成前述所述的引脚171与芯片座101。引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。
在一实施例中，连接层700包括一黏着层。黏着层的材质例如是导电黏着材料或非导电黏着材料，其中非导电黏着材料例如是非导电环氧树脂(epoxy)。黏着层可以是液体型态的黏着层或薄膜型态的黏着层，例如是一双面胶。黏着层亦可以是一焊在线薄膜(film-on-wire)型黏着层，此焊在线薄膜型黏着层的特性与薄膜型态黏着层的特性相似，但其厚度比薄膜型态黏着层的厚度较厚。
在一实施例中，第二芯片102b延伸超过第一芯片102a的周围。焊在线薄膜型黏着层的优点在于黏着层的厚度较厚，因此当第二芯片102b贴附于此黏着层时，仍然有间隙可以让焊线104a焊接至第一芯片102a。如果不是使用此焊在线薄膜型黏着层，连接层700除了液体型态的黏着层与/或薄膜型态的黏着层之外还必需包括一间隙。此间隙的目的在于隔开第一芯片102a与第二芯片102b，以使焊线104a可焊接至第一芯片102a。
随着上述工艺的描述，可由将芯片102配置于凹穴底部112(或基部202的上表面212)，而使所形成的封装体100具有较薄的厚度。以图7中的一具有堆叠芯片的封装体100来说，由凹穴111来提供放置的空间而使得封装体100具有较薄的厚度。此外，堆叠的顺序也是很重要的。举例来说，于图7中，第二芯片102b延伸超过凹穴111且部分覆盖于芯片座101的周围边缘区域114上，所以第二芯片102b不能放置于凹穴底部112。然而，第一芯片102a是按一定尺寸制作，所以第一芯片102a可于配置于凹穴底部112。在此实施例中，如果第一芯片102a的高度加上连接层700的高度够大且足够提供间隙于配置在周围边缘区域114上的金属镀层116的上表面150上方与焊线104a上方时，第二芯片102b可以堆叠于第一芯片102a的上表面。
图8显示本发明的一实施例的一种半导体封装进行表面黏着工艺的流程示意图。随着上述工艺的描述，引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。在本实施例中，一焊料膏802实质上覆盖至少一引脚171的一倾斜蚀刻区域308a，且一金属镀层127的一下表面156配置于此引脚171的下表面157上。接着，固化焊料膏802来定义一焊接接口802，以作为后序表面黏着工艺用。焊料膏802也可以实质上覆盖芯片座101的一倾斜蚀刻区域208a与芯片座101的一金属镀层117的一下表面152。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。
就表面黏着型封装体100a而言，焊接接口800、802可以由回焊工艺而形成液化焊料块804、806。接着，一印刷电路板808与液化焊料块804、806相连接，之后，固化液化焊料块804、806。焊接接口800、802于回焊焊料进行表面黏着工艺时具有足够的焊料，因此焊料对所对应覆盖的倾斜蚀刻区域208a与308a而言，如同一保护层。
除了利用焊料作为一保护层之外，图8的表面黏着工艺的其它优点在于：可以由回焊焊接接口800、802来使封装体100a进行表面黏着工艺。焊接接口800、802经由回焊会产生液态的焊料，此液态的焊料会移动于印刷电路板808上来作为封装体100a进行表面黏着工艺用。
图9显示本发明的另一实施例的一种半导体封装进行表面黏着工艺的流程示意图。在此实施例中，首先，提供一无焊接接口800、802的封装体100来作为表面黏着工艺的用。一芯片座101的一倾斜蚀刻区域208a与至少一引脚171的一倾斜蚀刻区域308a可覆盖一保护层，例如是一有机保焊层，此有机保焊层如同前述所述。接着，焊料膏900配置于一准备用来给封装体100进行表面黏着工艺的印刷电路板908上。在封装体100与印刷电路板908相互接近后，先回焊焊料膏900后固化形成焊料块902，以使封装体100贴附于印刷电路板908上。
随着上述工艺的描述，印刷电板908上具有足够的焊料膏900，以便于回焊焊料膏900进行表面黏着工艺时具有足够的焊料，而焊料对所对应覆盖的倾斜蚀刻区域208a与308a而言，如同一保护层。
虽然本发明已以实施例描述如上，然其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围应当以申请的权利要求范围所界定的内容为准。

Claims (16)

1.一种半导体封装，包括：
芯片座，包括：
周围边缘区域，具有上表面，且以凹穴底部定义出凹穴，其中该凹穴底部具有中心部；
上倾斜部，配置邻接于该周围边缘区域的该上表面，且面向远离该凹穴；
下倾斜部，配置邻接于该上倾斜部，且面向远离该凹穴；
多个引脚，围绕该芯片座，其中各该引脚包括：
上表面；
下表面；
上倾斜部，配置邻接于各该引脚的该上表面；
下倾斜部，配置邻接于各该引脚的该下表面；
第一半导体芯片，配置于该凹穴底部的中心部且电性连接至该些引脚；以及
封装胶体，形成于该第一半导体芯片与该些引脚上，以填充于该凹穴且覆盖该芯片座的该上倾斜部与该些引脚的该些上倾斜部，该芯片座的该下倾斜部与该些引脚的该些下倾斜部至少部分从该封装胶体的下表面向外延伸.
2.如权利要求1所述的半导体封装，其中，该周围边缘区域包括配置邻近该周围边缘区域的该上表面且面向该凹穴的上倾斜部。
3.如权利要求1所述的半导体封装，其中，该芯片座的该周围边缘区域包括接地段，该第一半导体芯片电性连接至该接地段。
4.如权利要求1所述的半导体封装，包括：
第一金属镀层，配置于该周围边缘区域的该上表面与该些引脚的该些上表面上；以及
第二金属镀层，配置于该芯片座的该下表面与该些引脚的该些下表面上。
5.如权利要求1所述的半导体封装，其中，该凹穴底部包括环绕该中心部的凹陷部。
6.如权利要求1所述的半导体封装，其中，该芯片座的该上倾斜部与该下倾斜部与该些引脚的该些上倾斜部与该些下倾斜部皆具有凹陷的轮廓。
7.如权利要求1所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中封装胶体形成于该第二半导体芯片上，且该连接层包括黏着层。
8.如权利要求1所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外。
9.一种半导体封装工艺，包括：
提供金属承载板，该金属承载板包括：
基部，具有上表面与下表面；
中心突出部，具有上表面且从该基部向上延伸，该中心突出部定义该基部的该上表面的中心区域，且该中心区域具有中心部；
多个周围突出部，各该周围突出部具有上表面且从该基部向上延伸，并环绕该中心突出部；
第一金属镀层，形成于该中心突出部的该上表面上与该周围突出部的该上表面上；
第二金属镀层，形成于对应该中心区域下方、该中心突出部下方以及该些周围突出部下方的该金属承载板的该下表面上；
贴附第一半导体芯片于该中心突出部；
电性连接该第一半导体芯片至该些周围突出部至少一第一突出部上；
形成封装胶体于该第一半导体芯片与该些周围突出部上；以及
蚀刻该第二金属镀层之外的该金属承载板的该下表面的区域，以使该些周围突出部与该中心突出部分离而形成多个引脚与芯片座，其中该芯片座包括该中心突出部与该中心区域，各该引脚具有配置邻接各该引脚的下表面的下倾斜部，该芯片座具有配置邻接该芯片座的下表面的下倾斜部，该芯片座的该下倾斜部与各该引脚的该下倾斜部至少部分从该封装胶体的下表面向外延伸。
10.如权利要求9所述的半导体封装工艺，其中，形成该金属承载板的步骤，包括：
提供铜板，该铜板具有上表面与下表面；
涂布第一光阻层于该铜板的该上表面上以及第二光阻层与该铜板的该下表面上；
对该第一光阻层与该第二光阻层进行曝光与显影，以于该铜板的该上表面形成第一曝光部以及于该铜板的该下表面形成第二曝光部；
形成第一金属镀层于该第一曝光部以及第二金属镀层于该第二曝光部；
移除该第一光阻层；
蚀刻该第一金属镀层之外的该铜层的该上表面，以形成该中心区域、该中心突出部与该些周围突出部；以及
移除该第二光阻层。
11.如权利要求9所述的半导体封装工艺，其中，该中心区域具有环绕该中心部的凹陷部。
12.如权利要求9所述的半导体封装工艺，包括：
由连接层贴附第二半导体芯片于该第一半导体芯片的上表面上，该连接层包括间隙与黏着层，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外；以及
电性连接该第二半导体芯片至该些周围突出部至少一第二突出部上，其中该封装胶体形成于该第二半导体芯片上。
13.一种半导体封装，包括：
芯片座，包括：
基部，具有上表面与下表面；
突出部，从该基部向上延伸且配置邻接于该基部的周围边缘，其中该突出部具有上表面；
第一侧表面，延伸介于该突出部的该上表面与该基部的该下表面之间，其中该第一侧表面具有相较于该突出部的该上表面更接近该基部的该下表面的第一尖端；
多个引脚，环绕该芯片座，至少该些引脚之一包含第二尖端的第二侧表面；
第一半导体芯片，配置于该基部的该上表面，且电性连接至该些引脚；
封装胶体，形成于该第一半导体芯片与该些引脚上，以覆盖该基部的该上表面、该第一尖端上方的该第一侧表面的至少一部分与该第二尖端上方的该第二侧表面的至少一部分，使得该第一尖端下方的该第一侧表面的至少一部分与该第二尖端下方的该第二侧表面的至少一部分突出于该封装胶体的下表面。
14.如权利要求13所述的半导体封装，其中，该基板的该上表面包括：
中心区域，该第一半导体芯片配置于该中心区域；以及
凹陷部，环绕该中心区域。
15.如权利要求14所述的半导体封装，其中，该中心区域定义为平面，且该第一尖端配置于该平面的下方。
16.如权利要求13所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外。
CN2009101274968A 2008-03-14 2009-03-13 半导体封装及其工艺 Active CN101540305B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US3647008P 2008-03-14 2008-03-14
US61/036,470 2008-03-14
US12/192,702 2008-08-15
US12/192,702 US8492883B2 (en) 2008-03-14 2008-08-15 Semiconductor package having a cavity structure

Publications (2)

Publication Number Publication Date
CN101540305A CN101540305A (zh) 2009-09-23
CN101540305B true CN101540305B (zh) 2011-03-30

Family

ID=41062123

Family Applications (4)

Application Number Title Priority Date Filing Date
CN2009101274934A Active CN101533825B (zh) 2008-03-14 2009-03-13 半导体封装结构及其工艺与表面粘着型半导体封装结构
CN2009101274987A Active CN101540310B (zh) 2008-03-14 2009-03-13 半导体封装及其制作方法
CN2009101274953A Active CN101540309B (zh) 2008-03-14 2009-03-13 半导体封装及其制作方法
CN2009101274968A Active CN101540305B (zh) 2008-03-14 2009-03-13 半导体封装及其工艺

Family Applications Before (3)

Application Number Title Priority Date Filing Date
CN2009101274934A Active CN101533825B (zh) 2008-03-14 2009-03-13 半导体封装结构及其工艺与表面粘着型半导体封装结构
CN2009101274987A Active CN101540310B (zh) 2008-03-14 2009-03-13 半导体封装及其制作方法
CN2009101274953A Active CN101540309B (zh) 2008-03-14 2009-03-13 半导体封装及其制作方法

Country Status (3)

Country Link
US (4) US20090230524A1 (zh)
CN (4) CN101533825B (zh)
TW (4) TWI419269B (zh)

Families Citing this family (152)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799611B2 (en) * 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8236612B2 (en) * 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
CN101601133B (zh) * 2006-10-27 2011-08-10 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US7777310B2 (en) * 2007-02-02 2010-08-17 Stats Chippac Ltd. Integrated circuit package system with integral inner lead and paddle
US7875988B2 (en) * 2007-07-31 2011-01-25 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8022511B2 (en) 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8212339B2 (en) * 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
JP4567773B2 (ja) * 2008-07-18 2010-10-20 三菱電機株式会社 電力用半導体装置
US8410584B2 (en) 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP2010056372A (ja) * 2008-08-29 2010-03-11 Sanyo Electric Co Ltd 樹脂封止型半導体装置とその製造方法
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8106502B2 (en) * 2008-11-17 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with plated pad and method of manufacture thereof
JP2010129591A (ja) * 2008-11-25 2010-06-10 Mitsui High Tec Inc リードフレーム、このリードフレームを用いた半導体装置及びその中間製品、並びにこれらの製造方法
US20100207257A1 (en) * 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US8110902B2 (en) 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8673687B1 (en) 2009-05-06 2014-03-18 Marvell International Ltd. Etched hybrid die package
US8044495B2 (en) * 2009-06-22 2011-10-25 Texas Instruments Incorporated Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US8803300B2 (en) * 2009-10-01 2014-08-12 Stats Chippac Ltd. Integrated circuit packaging system with protective coating and method of manufacture thereof
US8502357B2 (en) * 2009-10-01 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with shaped lead and method of manufacture thereof
US20110108966A1 (en) * 2009-11-11 2011-05-12 Henry Descalzo Bathan Integrated circuit packaging system with concave trenches and method of manufacture thereof
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8368185B2 (en) 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8030750B2 (en) 2009-11-19 2011-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) * 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
TWI453844B (zh) * 2010-03-12 2014-09-21 矽品精密工業股份有限公司 四方平面無導腳半導體封裝件及其製法
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8222726B2 (en) * 2010-03-29 2012-07-17 Advanced Semiconductor Engineering, Inc. Semiconductor device package having a jumper chip and method of fabricating the same
KR101192181B1 (ko) * 2010-03-31 2012-10-17 (주)포인트엔지니어링 광 소자 디바이스 및 그 제조 방법
US8373279B2 (en) * 2010-04-23 2013-02-12 Infineon Technologies Ag Die package
TWI429043B (zh) 2010-04-26 2014-03-01 Advance Materials Corp 電路板結構、封裝結構與製作電路板的方法
US20110316163A1 (en) * 2010-06-24 2011-12-29 Byung Tai Do Integrated circuit packaging system with molded interconnects and method of manufacture thereof
US9059151B2 (en) * 2010-07-20 2015-06-16 Stats Chippac Ltd. Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
US8669654B2 (en) * 2010-08-03 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with die paddle and method of manufacture thereof
US8304277B2 (en) 2010-09-09 2012-11-06 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8476772B2 (en) 2010-09-09 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
TWI420630B (zh) * 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
US8404524B2 (en) 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof
KR101121862B1 (ko) 2010-09-17 2012-03-20 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8669649B2 (en) * 2010-09-24 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof
CN101944520B (zh) * 2010-09-26 2012-06-27 日月光半导体制造股份有限公司 半导体封装结构与半导体封装工艺
US8912046B2 (en) 2010-10-28 2014-12-16 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
TWI419290B (zh) 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
US20120119342A1 (en) * 2010-11-11 2012-05-17 Mediatek Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
TWI455213B (zh) * 2010-12-15 2014-10-01 Chipmos Technologies Inc 無外引腳封裝結構及其製作方法
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US20120200281A1 (en) * 2011-02-07 2012-08-09 Texas Instruments Incorporated Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing
US20120205811A1 (en) * 2011-02-14 2012-08-16 Byung Tai Do Integrated circuit packaging system with terminal locks and method of manufacture thereof
US8735224B2 (en) * 2011-02-14 2014-05-27 Stats Chippac Ltd. Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US8969136B2 (en) * 2011-03-25 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
TW201241970A (en) * 2011-04-08 2012-10-16 Advanced Semiconductor Eng Semiconductor package with recesses in the edged leadas
US20120261689A1 (en) * 2011-04-13 2012-10-18 Bernd Karl Appelt Semiconductor device packages and related methods
CN102184908A (zh) * 2011-04-26 2011-09-14 日月光半导体制造股份有限公司 进阶式四方扁平无引脚封装结构及其制作方法
CN102214635A (zh) * 2011-05-27 2011-10-12 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
US8957509B2 (en) * 2011-06-23 2015-02-17 Stats Chippac Ltd. Integrated circuit packaging system with thermal emission and method of manufacture thereof
US9035440B2 (en) 2011-06-23 2015-05-19 Stats Chippac Ltd. Integrated circuit packaging system with a lead and method of manufacture thereof
WO2013006209A2 (en) * 2011-07-03 2013-01-10 Eoplex Limited Lead carrier with thermally fused package components
US8502363B2 (en) * 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
CN107256851B (zh) * 2011-07-18 2020-04-24 日月光半导体制造股份有限公司 半导体封装结构
TWI441296B (zh) * 2011-07-19 2014-06-11 矽品精密工業股份有限公司 封裝結構及其製法
CN102263080B (zh) * 2011-07-29 2015-06-17 天水华天科技股份有限公司 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法
CN102263081A (zh) * 2011-07-29 2011-11-30 天水华天科技股份有限公司 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法
CN102280431B (zh) * 2011-08-01 2016-02-17 日月光半导体制造股份有限公司 具有保护层的半导体封装及其制作方法
US20130133193A1 (en) * 2011-11-28 2013-05-30 Mediatek Singapore Pte. Ltd. Surface mount technology process for advanced quad flat no-lead package process and stencil used therewith
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
TWI505425B (zh) * 2012-01-30 2015-10-21 Advanced Semiconductor Eng 整合屏蔽膜之半導體封裝件及其製造方法
US8674487B2 (en) * 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
US9799589B2 (en) * 2012-03-23 2017-10-24 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
TWI459517B (zh) * 2012-06-14 2014-11-01 矽品精密工業股份有限公司 封裝基板暨半導體封裝件及其製法
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
US9324584B2 (en) * 2012-12-14 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with transferable trace lead frame
US20140165389A1 (en) * 2012-12-14 2014-06-19 Byung Tai Do Integrated circuit packaging system with routable grid array lead frame
CN103021892B (zh) * 2012-12-28 2016-05-11 日月光半导体（昆山）有限公司 无外引脚半导体封装构造及其制造方法与导线架条
CN103021879B (zh) * 2012-12-28 2015-09-09 日月光半导体（昆山）有限公司 无外引脚半导体封装构造及其制造方法与导线架条
US9013028B2 (en) * 2013-01-04 2015-04-21 Texas Instruments Incorporated Integrated circuit package and method of making
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US20140357022A1 (en) * 2013-06-04 2014-12-04 Cambridge Silicon Radio Limited A qfn with wettable flank
US9368423B2 (en) * 2013-06-28 2016-06-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package
US9012268B2 (en) * 2013-06-28 2015-04-21 Stmicroelectronics, Inc. Leadless packages and method of manufacturing same
CN103400825B (zh) 2013-07-31 2016-05-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US9978667B2 (en) 2013-08-07 2018-05-22 Texas Instruments Incorporated Semiconductor package with lead frame and recessed solder terminals
CN104425396A (zh) * 2013-09-02 2015-03-18 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
GB201318911D0 (en) * 2013-10-25 2013-12-11 Litecool Ltd LED Package
CN104576883B (zh) 2013-10-29 2018-11-16 普因特工程有限公司 芯片安装用阵列基板及其制造方法
CN104112728B (zh) * 2013-11-22 2017-10-31 广东美的制冷设备有限公司 器件安装结构和集成电路模块
US9484278B2 (en) * 2013-11-27 2016-11-01 Infineon Technologies Ag Semiconductor package and method for producing the same
GB2525585B (en) * 2014-03-20 2018-10-03 Micross Components Ltd Leadless chip carrier
TWI550784B (zh) * 2014-04-18 2016-09-21 南茂科技股份有限公司 扁平無引腳封裝及其製造方法
US9219025B1 (en) * 2014-08-15 2015-12-22 Infineon Technologies Ag Molded flip-clip semiconductor package
DE102014114982B4 (de) * 2014-10-15 2023-01-26 Infineon Technologies Ag Verfahren zum Bilden einer Chip-Baugruppe
DE102014117897B4 (de) 2014-12-04 2022-01-13 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von optoelektronischen Modulen und Anordnung mit einem solchen Modul
US9748187B2 (en) * 2014-12-19 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and method for wafer dicing
KR102334377B1 (ko) * 2015-02-17 2021-12-02 삼성전자 주식회사 실링 영역 및 디커플링 커패시터 영역을 포함하는 반도체 소자
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
JP2016219520A (ja) * 2015-05-18 2016-12-22 Ｔｏｗａ株式会社 半導体装置及びその製造方法
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
US9515032B1 (en) * 2015-08-13 2016-12-06 Win Semiconductors Corp. High-frequency package
US9373569B1 (en) 2015-09-01 2016-06-21 Texas Instruments Incorporation Flat no-lead packages with electroplated edges
US9922843B1 (en) 2015-11-10 2018-03-20 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
CN110637364B (zh) * 2016-04-22 2022-10-28 德州仪器公司 改进的引线框系统
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
JP6788825B2 (ja) * 2016-07-20 2020-11-25 大日本印刷株式会社 リードフレームおよび半導体装置
JP6761738B2 (ja) * 2016-11-15 2020-09-30 新光電気工業株式会社 リードフレーム及びその製造方法、電子部品装置の製造方法
JP6777365B2 (ja) * 2016-12-09 2020-10-28 大口マテリアル株式会社 リードフレーム
CN106783792A (zh) * 2017-03-22 2017-05-31 江苏长电科技股份有限公司 一种塑封体侧面引脚具有侧边爬锡性能的封装结构
US9972558B1 (en) * 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing
US20180315725A1 (en) * 2017-04-26 2018-11-01 Nanya Technology Corporation Package structure having bump with protective anti-oxidation coating
CN107146777A (zh) * 2017-05-27 2017-09-08 江苏长电科技股份有限公司 一种免切割封装结构及其制造工艺
US10204814B1 (en) * 2017-07-28 2019-02-12 Stmicroelectronics, Inc. Semiconductor package with individually molded leadframe and die coupled at solder balls
US10529672B2 (en) 2017-08-31 2020-01-07 Stmicroelectronics, Inc. Package with interlocking leads and manufacturing the same
CN108417522B (zh) * 2018-01-17 2021-01-01 桂林电子科技大学 三层板结构电路封装方法
US10593612B2 (en) * 2018-03-19 2020-03-17 Stmicroelectronics S.R.L. SMDs integration on QFN by 3D stacked solution
US20190287881A1 (en) 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
US10361148B1 (en) * 2018-03-30 2019-07-23 Semiconductor Components Industries, Llc Leadframe with efficient heat dissipation for semiconductor device package assembly
CN108364930B (zh) * 2018-05-04 2024-01-26 扬州扬杰电子科技股份有限公司 一种vdmos功率器件芯片焊接层空洞补偿结构
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN109712955B (zh) * 2018-11-23 2021-05-11 华为技术有限公司 一种基于pcb本体出引脚的封装模块及其制备方法
DE102019112778B4 (de) 2019-05-15 2023-10-19 Infineon Technologies Ag Batchherstellung von Packages durch eine in Träger getrennte Schicht nach Anbringung von elektronischen Komponenten
CN112309873B (zh) * 2019-07-26 2023-11-10 江苏长电科技股份有限公司 电磁屏蔽封装结构及其封装方法
DE102019220215A1 (de) * 2019-12-19 2021-06-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von Halbleiterbauelementen und Halbleiterbauelement
US11887916B2 (en) * 2020-09-09 2024-01-30 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11569179B2 (en) * 2020-11-19 2023-01-31 Advanced Semiconductor Engineering, Inc. Package structure including an outer lead portion and an inner lead portion and method for manufacturing package structure

Family Cites Families (171)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948032A (en) 1988-11-21 1990-08-14 Atmel Corporation Fluxing agent
US5200025A (en) 1990-09-20 1993-04-06 Dainippon Screen Manufacturing Co. Ltd. Method of forming small through-holes in thin metal plate
US5389739A (en) * 1992-12-15 1995-02-14 Hewlett-Packard Company Electronic device packaging assembly
US5497032A (en) 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
JPH08115989A (ja) 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
US5646831A (en) * 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR0185512B1 (ko) * 1996-08-19 1999-03-20 김광호 칼럼리드구조를갖는패키지및그의제조방법
WO1998013500A2 (en) * 1996-09-24 1998-04-02 Bavarian Nordic Research Institute A/S Recombinant mva virus expressing dengue virus antigens, and the use thereof in vaccines
US6097098A (en) 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JP2928190B2 (ja) * 1997-04-09 1999-08-03 九州日本電気株式会社 テーピングリードフレーム
KR100235308B1 (ko) * 1997-06-30 1999-12-15 윤종용 2중 굴곡된 타이바와 소형 다이패드를 갖는 반도체 칩 패키지
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
JP3097653B2 (ja) 1998-04-17 2000-10-10 日本電気株式会社 半導体装置用パッケージおよびその製造方法
US6949816B2 (en) 2003-04-21 2005-09-27 Motorola, Inc. Semiconductor component having first surface area for electrically coupling to a semiconductor chip and second surface area for electrically coupling to a substrate, and method of manufacturing same
US6132593A (en) 1998-06-08 2000-10-17 Tan; Yong-Jun Method and apparatus for measuring localized corrosion and other heterogeneous electrochemical processes
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6989294B1 (en) * 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7247526B1 (en) * 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US7226811B1 (en) * 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP3764587B2 (ja) 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
JP4030200B2 (ja) 1998-09-17 2008-01-09 株式会社ルネサステクノロジ 半導体パッケージおよびその製造方法
US6667541B1 (en) * 1998-10-21 2003-12-23 Matsushita Electric Industrial Co., Ltd. Terminal land frame and method for manufacturing the same
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
KR100705521B1 (ko) * 1998-12-02 2007-04-10 가부시키가이샤 히타치세이사쿠쇼 반도체 장치
DE19905055A1 (de) * 1999-02-08 2000-08-17 Siemens Ag Halbleiterbauelement mit einem Chipträger mit Öffnungen zur Kontaktierung
SG75154A1 (en) * 1999-02-23 2000-09-19 Inst Of Microelectronics Plastic ball grid array package
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20020100165A1 (en) * 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
TW423133B (en) 1999-09-14 2001-02-21 Advanced Semiconductor Eng Manufacturing method of semiconductor chip package
US6525406B1 (en) * 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
JP2001185651A (ja) 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6333252B1 (en) 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6261864B1 (en) * 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6342730B1 (en) 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6548328B1 (en) * 2000-01-31 2003-04-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
JP3706533B2 (ja) * 2000-09-20 2005-10-12 三洋電機株式会社 半導体装置および半導体モジュール
US7173336B2 (en) * 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7091606B2 (en) 2000-01-31 2006-08-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device and semiconductor module
US6306685B1 (en) * 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6562660B1 (en) * 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
US6242284B1 (en) 2000-05-05 2001-06-05 Advanced Semiconductor Engineering, Inc. Method for packaging a semiconductor chip
JP3883784B2 (ja) 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
JP2001338947A (ja) * 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
TW507482B (en) * 2000-06-09 2002-10-21 Sanyo Electric Co Light emitting device, its manufacturing process, and lighting device using such a light-emitting device
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
TW506236B (en) 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
JP3650001B2 (ja) 2000-07-05 2005-05-18 三洋電機株式会社 半導体装置およびその製造方法
US6429536B1 (en) * 2000-07-12 2002-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device
TW473965B (en) * 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
TW497371B (en) * 2000-10-05 2002-08-01 Sanyo Electric Co Semiconductor device and semiconductor module
US6762118B2 (en) 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
JP4417541B2 (ja) * 2000-10-23 2010-02-17 ローム株式会社 半導体装置およびその製造方法
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
JP3653460B2 (ja) 2000-10-26 2005-05-25 三洋電機株式会社 半導体モジュールおよびその製造方法
US6906414B2 (en) 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
JP3895570B2 (ja) 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6720207B2 (en) * 2001-02-14 2004-04-13 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US6545347B2 (en) 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6545345B1 (en) * 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
JP3609737B2 (ja) 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
KR100393448B1 (ko) * 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP4034073B2 (ja) 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003017646A (ja) 2001-06-29 2003-01-17 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置およびその製造方法
ATE546835T1 (de) 2001-07-09 2012-03-15 Sumitomo Metal Mining Co Verfahren zur herstellung eines leiterrahmens
TW538658B (en) * 2001-08-27 2003-06-21 Sanyo Electric Co Manufacturing method for circuit device
JP2003124421A (ja) * 2001-10-15 2003-04-25 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
US7001798B2 (en) 2001-11-14 2006-02-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
TW523887B (en) * 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
JP4173346B2 (ja) 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
WO2003085728A1 (en) * 2002-04-11 2003-10-16 Koninklijke Philips Electronics N.V. Carrier, method of manufacturing a carrier and an electronic device
US7799611B2 (en) * 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP4095827B2 (ja) * 2002-05-10 2008-06-04 株式会社ルネサステクノロジ 半導体装置
JP2004063615A (ja) 2002-07-26 2004-02-26 Nitto Denko Corp 半導体装置の製造方法、半導体装置製造用接着シートおよび半導体装置
KR20040030283A (ko) * 2002-09-05 2004-04-09 신꼬오덴기 고교 가부시키가이샤 리드 프레임 및 그 제조 방법
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6777788B1 (en) 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
WO2004057668A2 (en) 2002-12-20 2004-07-08 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
US20040124505A1 (en) 2002-12-27 2004-07-01 Mahle Richard L. Semiconductor device package with leadframe-to-plastic lock
DE10310144A1 (de) 2003-03-07 2004-09-16 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Entladungslampe für dielektrisch behinderte Entladungen mit zurückspringend überhändenden Entladungselektrodenabschnitten
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
TW200425427A (en) * 2003-05-02 2004-11-16 Siliconware Precision Industries Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
US6927479B2 (en) 2003-06-25 2005-08-09 St Assembly Test Services Ltd Method of manufacturing a semiconductor package for a die larger than a die pad
US20040262781A1 (en) * 2003-06-27 2004-12-30 Semiconductor Components Industries, Llc Method for forming an encapsulated device and structure
JP2005026466A (ja) * 2003-07-02 2005-01-27 Renesas Technology Corp 半導体装置およびリードフレーム
TWI233674B (en) 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
WO2005017968A2 (en) 2003-08-14 2005-02-24 Advanced Interconnect Technologies Limited Semiconductor device package and method for manufacturing same
TWI257693B (en) 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
US7060535B1 (en) * 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
KR100568225B1 (ko) 2003-11-06 2006-04-07 삼성전자주식회사 리드 프레임 및 이를 적용한 반도체 패키지 제조방법
JP2005191240A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP2005191342A (ja) * 2003-12-26 2005-07-14 Renesas Technology Corp 半導体装置およびその製造方法
TWI254437B (en) * 2003-12-31 2006-05-01 Advanced Semiconductor Eng Leadless package
US7122406B1 (en) * 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
JP2005203390A (ja) * 2004-01-13 2005-07-28 Seiko Instruments Inc 樹脂封止型半導体装置の製造方法
US7009286B1 (en) 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7494557B1 (en) 2004-01-30 2009-02-24 Sandia Corporation Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures
US7215009B1 (en) * 2004-02-23 2007-05-08 Altera Corporation Expansion plane for PQFP/TQFP IR—package design
US7008820B2 (en) * 2004-06-10 2006-03-07 St Assembly Test Services Ltd. Chip scale package with open substrate
CN2726111Y (zh) 2004-06-22 2005-09-14 胜开科技股份有限公司 堆叠集成电路封装组件
JP2008507123A (ja) 2004-07-13 2008-03-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 集積回路を備える電子デバイス
US7087461B2 (en) 2004-08-11 2006-08-08 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
TWI256096B (en) * 2004-10-15 2006-06-01 Advanced Semiconductor Eng Method for fabricating quad flat non-leaded package
US7598606B2 (en) 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
US7087462B1 (en) 2005-06-07 2006-08-08 Advanced Semiconductor Engineering, Inc. Method for forming leadless semiconductor packages
US7348663B1 (en) * 2005-07-15 2008-03-25 Asat Ltd. Integrated circuit package and method for fabricating same
TWI287275B (en) * 2005-07-19 2007-09-21 Siliconware Precision Industries Co Ltd Semiconductor package without chip carrier and fabrication method thereof
JP3947750B2 (ja) 2005-07-25 2007-07-25 株式会社三井ハイテック 半導体装置の製造方法及び半導体装置
US8003444B2 (en) 2005-08-10 2011-08-23 Mitsui High-Tec, Inc. Semiconductor device and manufacturing method thereof
US7262491B2 (en) 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
TWI264091B (en) 2005-09-15 2006-10-11 Siliconware Precision Industries Co Ltd Method of manufacturing quad flat non-leaded semiconductor package
US8536689B2 (en) * 2005-10-03 2013-09-17 Stats Chippac Ltd. Integrated circuit package system with multi-surface die attach pad
US8163604B2 (en) 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7372133B2 (en) 2005-12-01 2008-05-13 Intel Corporation Microelectronic package having a stiffening element and method of making same
TW200729429A (en) * 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
TW200729444A (en) * 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
US20090215159A1 (en) * 2006-01-23 2009-08-27 Quidel Corporation Device for handling and analysis of a biological sample
JP2007221045A (ja) * 2006-02-20 2007-08-30 Oki Electric Ind Co Ltd マルチチップ構造を採用した半導体装置
US7301225B2 (en) 2006-02-28 2007-11-27 Freescale Semiconductor, Inc. Multi-row lead frame
TWI286375B (en) 2006-03-24 2007-09-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same
US7683461B2 (en) 2006-07-21 2010-03-23 Stats Chippac Ltd. Integrated circuit leadless package system
TW200810044A (en) * 2006-08-04 2008-02-16 Advanced Semiconductor Eng Non-lead leadframe and package therewith
US20080029855A1 (en) * 2006-08-04 2008-02-07 Yi-Ling Chang Lead Frame and Fabrication Method thereof
CN100559577C (zh) * 2006-08-23 2009-11-11 南茂科技股份有限公司 具有阵列接垫的晶片封装构造及其制造方法
US9281218B2 (en) 2006-08-30 2016-03-08 United Test And Assembly Center Ltd. Method of producing a semiconductor package
JP4533875B2 (ja) * 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
US20080079127A1 (en) * 2006-10-03 2008-04-03 Texas Instruments Incorporated Pin Array No Lead Package and Assembly Method Thereof
US20080079124A1 (en) 2006-10-03 2008-04-03 Chris Edward Haga Interdigitated leadfingers
US7741704B2 (en) * 2006-10-18 2010-06-22 Texas Instruments Incorporated Leadframe and mold compound interlock in packaged semiconductor device
CN101601133B (zh) * 2006-10-27 2011-08-10 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US7608484B2 (en) 2006-10-31 2009-10-27 Texas Instruments Incorporated Non-pull back pad package with an additional solder standoff
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
US7605477B2 (en) * 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
KR100950378B1 (ko) * 2007-01-31 2010-03-29 야마하 가부시키가이샤 반도체 장치와 패키징 구조체
TWI337387B (en) 2007-04-20 2011-02-11 Chipmos Technologies Inc Leadframe for leadless package, package structure and manufacturing method using the same
US7800211B2 (en) * 2007-06-29 2010-09-21 Stats Chippac, Ltd. Stackable package by using internal stacking modules
US7675146B2 (en) * 2007-09-07 2010-03-09 Infineon Technologies Ag Semiconductor device with leadframe including a diffusion barrier
US7838974B2 (en) * 2007-09-13 2010-11-23 National Semiconductor Corporation Intergrated circuit packaging with improved die bonding
US20090127682A1 (en) 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US7808089B2 (en) 2007-12-18 2010-10-05 National Semiconductor Corporation Leadframe having die attach pad with delamination and crack-arresting features
US20090189261A1 (en) 2008-01-25 2009-07-30 Lay Yeap Lim Ultra-Thin Semiconductor Package
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US7834431B2 (en) * 2008-04-08 2010-11-16 Freescale Semiconductor, Inc. Leadframe for packaged electronic device with enhanced mold locking capability
TWI368983B (en) 2008-04-29 2012-07-21 Advanced Semiconductor Eng Integrated circuit package and manufacturing method thereof
TWI372458B (en) 2008-05-12 2012-09-11 Advanced Semiconductor Eng Stacked type chip package structure
TW200947654A (en) 2008-05-12 2009-11-16 Advanced Semiconductor Eng Stacked type chip package structure and method of fabricating the same
US7786557B2 (en) 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US20090315159A1 (en) 2008-06-20 2009-12-24 Donald Charles Abbott Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
CN101442035B (zh) 2008-12-14 2011-03-16 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110163430A1 (en) 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof

Also Published As

Publication number Publication date
US20090230526A1 (en) 2009-09-17
CN101540310A (zh) 2009-09-23
TW200939417A (en) 2009-09-16
TW200939416A (en) 2009-09-16
TWI380416B (en) 2012-12-21
CN101540309A (zh) 2009-09-23
TW200939418A (en) 2009-09-16
US20090230523A1 (en) 2009-09-17
TWI459513B (zh) 2014-11-01
US8492883B2 (en) 2013-07-23
CN101540309B (zh) 2011-06-29
US20090230524A1 (en) 2009-09-17
US8115285B2 (en) 2012-02-14
US20090230525A1 (en) 2009-09-17
CN101540310B (zh) 2011-01-05
CN101540305A (zh) 2009-09-23
CN101533825B (zh) 2011-01-05
CN101533825A (zh) 2009-09-16
TWI419269B (zh) 2013-12-11
TWI416678B (zh) 2013-11-21
US8120152B2 (en) 2012-02-21
TW200939427A (en) 2009-09-16

Similar Documents

Publication Publication Date Title
CN101540305B (zh) 半导体封装及其工艺
CN207781575U (zh) 经封装的电子装置
TWI705539B (zh) 半導體封裝方法、半導體封裝和堆疊半導體封裝
US8236612B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20100178734A1 (en) Leadless Semiconductor Package with Electroplated Layer Embedded in Encapsulant and the Method for Manufacturing the Same
CN101383301B (zh) 形成倒装芯片突起载体式封装的方法
CN110416097A (zh) 防止铟金属溢出的封装结构及封装方法
US20020189853A1 (en) BGA substrate with direct heat dissipating structure
CN104716110A (zh) 芯片封装结构及其制造方法
CN104733334A (zh) 具有无过孔衬底的集成电路封装系统及其制造方法
US10109564B2 (en) Wafer level chip scale semiconductor package
CN205920961U (zh) 倒装芯片封装结构
CN106158792A (zh) 半导体封装及其制造方法
US20080135939A1 (en) Fabrication method of semiconductor package and structure thereof
CN101944520B (zh) 半导体封装结构与半导体封装工艺
CN111816625A (zh) 多层芯片堆叠结构和多层芯片堆叠方法
CN101325191A (zh) 芯片上具有图案的四方扁平无引脚封装结构
TWI637536B (zh) 電子封裝結構及其製法
CN101937901B (zh) 线路基板及其制作方法与封装结构
US9673175B1 (en) Heat spreader for package-on-package (PoP) type packages
CN106449428A (zh) 芯片封装工艺
CN202940236U (zh) 封装基板构造
KR100393094B1 (ko) 지지각을 갖는 기판을 이용한 반도체 패키지
US20180240738A1 (en) Electronic package and fabrication method thereof
KR100708033B1 (ko) 반도체 패키지용 섭스트레이트 및 이의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant