CN101546782B - 薄膜晶体管、其制造方法及有机发光二极管显示装置 - Google Patents

薄膜晶体管、其制造方法及有机发光二极管显示装置 Download PDF

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CN101546782B
CN101546782B CN200910127094.8A CN200910127094A CN101546782B CN 101546782 B CN101546782 B CN 101546782B CN 200910127094 A CN200910127094 A CN 200910127094A CN 101546782 B CN101546782 B CN 101546782B
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semiconductor layer
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film transistor
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CN101546782A (zh
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朴炳建
徐晋旭
梁泰勋
李吉远
李东炫
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Samsung Display Co Ltd
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
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    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst

Abstract

薄膜晶体管、其制造方法及有机发光二极管显示装置。该薄膜晶体管包括:基板;布置在所述基板上的半导体层,包括沟道区、源极区、漏极区和基体接触区;布置在所述半导体层上从而使所述第一基体接触区暴露的栅极绝缘层;布置在所述栅极绝缘层上从而接触所述第一基体接触区的栅电极;布置在所述栅电极上的层间绝缘层;以及布置在所述层间绝缘层上并且被电连接至所述源极区和所述漏极区的源电极和漏电极。所述基体接触区被形成在所述半导体层的边缘中。

Description

薄膜晶体管、其制造方法及有机发光二极管显示装置
技术领域
本发明方面涉及薄膜晶体管、制造该薄膜晶体管的方法以及包括该薄膜晶体管的有机发光二极管显示装置。
背景技术
通常,由于多晶硅层的高场效应迁移率及对高速电路和/或互补金属氧化物半导体(CMOS)电路的适应性,多晶硅层被广泛用作薄膜晶体管的半导体层。使用这样的多晶硅层的薄膜晶体管被用作有源矩阵液晶显示(AMLCD)装置的开关装置。这样的薄膜晶体管也用作有源矩阵有机发光二极管显示装置(AMOLED)的开关装置和/或驱动装置。
用在有源矩阵显示装置中的多晶硅薄膜晶体管通常是具有浮动的、岛状的半导体层的浮体多晶硅薄膜晶体管(poly-Si TFT)。随着浮体多晶硅薄膜晶体管按比例缩小,导致该多晶硅薄膜晶体管的漏极电流和饱和区减少。
为了解决该问题,已提出其中半导体层与栅电极相连的栅极-基体接触TFT。栅极-基体接触TFT在低栅极电压下具有增大的亚阈值斜率值和高的漏极电流。因此,即使在这样的低栅极电压下,也能实现开/关特性,从而形成低功率平板显示装置。
通常,为了实现栅极-基体接触薄膜晶体管,接触栅电极的基体接触区被独立形成,以便从现有的不具有基体接触区的半导体层延伸。然而,这样的结构增加了半导体层和基体接触区所占的面积,因此不适于装置集成。
发明内容
通过利用半导体层的边缘区作为基体接触区而不从半导体层延伸独立的基体接触层来实施栅极-基体接触结构,本发明方面提供比现有的栅极-基体接触薄膜晶体管具有较小面积的薄膜晶体管。本发明方面也涉及制造该薄膜晶体管的方法,以及包括该薄膜晶体管的有机发光二极管显示装置。
根据本发明的示例性实施例,薄膜晶体管包括:基板;布置在所述基板上并且包括沟道区、源极区、漏极区和基体接触区的半导体层;布置在所述半导体层上并使所述基体接触区暴露的栅极绝缘层;布置在所述栅极绝缘层上、与所述基体接触区接触的栅电极;布置在所述栅电极上的层间绝缘层;以及布置在所述层间绝缘层上并且被电连接至所述源极区和所述漏极区的源电极和漏电极。所述基体接触区被布置在所述半导体层的边缘处。
根据本发明的另一示例性实施例,制造薄膜晶体管的方法包括:在基板上形成半导体层;在所述半导体层上形成栅极绝缘层,以使所述半导体层的边缘暴露;在所述栅极绝缘层上形成接触所述半导体层的暴露的边缘的栅电极;在所述栅电极上形成层间绝缘层;以及在所述层间绝缘层上形成源电极和漏电极。所述源电极和漏电极通过所述层间绝缘层和所述栅极绝缘层中的开口被电连接至所述半导体层的源极区和漏极区。
根据本发明的又一示例性实施例,有机发光二极管显示装置包括:基板;布置在所述基板上并且包括沟道区、源极区、漏极区和基体接触区的半导体层;布置在所述半导体层上并使所述基体接触区暴露的栅极绝缘层;布置在所述栅极绝缘层上、与所述基体接触区接触的栅电极;布置在所述栅电极上的层间绝缘层;布置在所述层间绝缘层上并且被电连接至所述源极区和所述漏极区的源电极和漏电极;被电连接至所述源电极和漏电极之一的第一电极;布置在所述第一电极上并且包括发射层的有机层;以及布置在所述有机层上的第二电极。所述基体接触区被布置在所述半导体层的边缘处。
本发明的另外的方面和/或优点将在下面的说明书中部分地提出,部分地,从本说明书中将是显而易见的,或者通过实践本发明而获知。
附图说明
从以下结合附图对示例性实施例的描述中,本发明的这些和/或其它方面及优点将变得显而易见和更加容易理解,其中:
图1A、2A、3A、4A和5A为示出根据本发明示例性实施例1的制造薄膜晶体管的过程的平面图,并且图1B、2B、3B、4B和5B为分别沿着图1A、2A、3A、4A和5A的线A-A′的剖面图;
图6A、7A和8A为示出根据本发明示例性实施例2的制造薄膜晶体管的过程的平面图,并且图6B、7B和8B为分别沿着图6A、7A和8A的线B-B′的剖面图;并且
图9为根据本发明示例性实施例的包括薄膜晶体管的有机发光二极管显示装置的剖面图。
具体实施方式
现将详细参考本发明的示例性实施例,其中示例被示出在附图中。说明书中,相同的附图标记始终表示相同的元件。为了解释本发明的方面,下面将参考附图描述示例性实施例。
正如在此处提及的,当描述第一元件被布置或形成于第二元件之“上”,或与第二元件“相邻”时,第一元件可以直接接触第二元件,或者可以通过位于它们之间的一个或多个元件与第二元件分离。相反地,当提到元件被“直接”布置或形成于另一元件“上”时,则不存在中间元件。正如在此处使用的,术语“和/或”包括一个或多个相关列出项的任意和全部组合。
示例性实施例1
图1A、2A、3A、4A和5A为示出根据本发明示例性实施例1的制造薄膜晶体管的过程的平面图。图1B、2B、3B、4B和5B为沿着图1A、2A、3A、4A和5A的线A-A′的剖面图。
参考图1A和1B,缓冲层101被形成在可由玻璃或塑料形成的基板100上。缓冲层101可以包括一个或多个诸如氧化硅层或氮化硅层之类的绝缘层。例如,该绝缘层可以通过化学气相沉积或物理气相沉积形成。缓冲层101防止水分和/或杂质从基板100扩散。在非晶硅层结晶期间,缓冲层101也可用于控制传热速率。
然后,多晶硅层102被形成在缓冲层101上。可以通过使用诸如快速热退火(RTA)、固相结晶(SPC)、准分子激光晶化(ELA)、金属诱导结晶(MIC)、金属诱导横向结晶(MILC)、顺次横向固化(SLS)或超晶粒硅(SGS)之类的结晶方法对非晶硅层进行结晶从而形成多晶硅层102。
然后,绝缘层103形成在多晶硅层102上。绝缘层103可以是氧化硅层、氮化硅层或它们的组合。
参考图2A和2B,多晶硅层102和绝缘层103被图案化。多晶硅层102被图案化以形成半导体层104。绝缘层103被图案化以形成栅极绝缘层105。栅极绝缘层105使半导体层104的一个或多个边缘区106暴露。
此处,半导体层104的长度参考与连接半导体层104的源极区107(图3A)和漏极区108(图3A)的线平行的方向,而半导体层104的宽度参考垂直于长度方向的方向,即沿着线A-A′延伸的方向。半导体层104的边缘区106横过半导体层104的宽度被分开预定的距离。
通过一次图案化工艺,即通过调整蚀刻条件以使绝缘层103相对于多晶硅层102是过蚀刻的,栅极绝缘层105可以被形成以使半导体层104的边缘区106暴露。例如,通过使绝缘层103的临界尺寸(CD)偏差大于下面的多晶硅层102的临界尺寸偏差,栅极绝缘层105可以被蚀刻以使得半导体层104的边缘区106暴露。
边缘区106的宽度a小于约0.1μm。该范围形成不具有独立延伸的基体接触区的栅极-基体接触TFT结构,而且不会大大减少现有半导体层104的沟道区的面积。
参考图3A和3B,杂质被注入半导体层104的通过栅极绝缘层105而暴露的边缘区106。另一类型的杂质被注入半导体层104的源极区107和漏极区108。例如,一种杂质可以是N型杂质,而另一种杂质可以是P型杂质。这导致半导体层104的源极区107和漏极区108及边缘区106的PNP或NPN型结构,以使从源极区107和漏极区108流出的电流不流入边缘区106。P型杂质可以从由硼(B)、铝(Al)、镓(Ga)和铟(In)构成的组中选择。N型杂质可以从由磷(P)、砷(As)和锑(Sb)构成的组中选择。
通过注入杂质到半导体层104的源极区107和漏极区108要被形成的区域,形成半导体层104的源极区107和漏极区108。沟道区109被形成在源极区107和漏极区108之间。基体接触区110被形成在半导体层104的边缘区106中,并且在源极区107和漏极区108之间延伸。基体接触区110被连接至沟道区109,并且被布置在沟道区109的相对侧。为了方便起见,下文中,仅提到一个基体接触区110。
源极区107和漏极区108可以通过使用光刻胶图案作为掩模将杂质注入半导体层104中而形成。可替代地,源极区107和漏极区108可以通过使用随后形成的栅电极作为掩模将杂质注入半导体层104中而形成。
参考图4A和4B,栅电极材料被沉积在栅极绝缘层105上,然后被图案化以形成栅电极111。栅电极111叠盖沟道区109和基体接触区110。栅电极111可以是铝(Al)层、诸如铝-钕(Al-Nd)之类的铝合金层或堆积在铬(Cr)或钼(Mo)合金上的多层铝合金。由于绝缘层103被图案化以使基体接触区110暴露,所以栅电极111接触基体接触区110,从而形成栅极-基体接触TFT。因为基体接触区110被布置在沟道区109的相对的边缘,所以沟道区109的宽度b小于半导体层104整体的宽度,即小于沟道区109加上基体接触区110的宽度。
在相关技术中,通过在基板的整个表面上形成多晶硅层、在多晶硅层上形成光刻胶图案以及使用光刻胶图案作为掩模蚀刻多晶硅层来形成半导体层。在蚀刻多晶硅层的过程中,半导体层的边缘可能被蚀刻溶液或用于蚀刻的等离子体破坏。
此外,半导体层的边缘上残余的光刻胶可能使半导体层不均匀和/或具有不好的特性。这可能影响包括这样的半导体层的TFT的阈值电压或S-系数,并且可能导致TFT的I-V特性曲线上的峰值。这些问题是由于在沟道区中包括破坏的边缘而导致的。
通过向半导体层的与沟道区接触的边缘注入杂质,而不是将边缘包括在沟道区中,本发明方面能够解决上述和/或其它问题。杂质形成接触栅电极的基体接触区。这使得利用现有的半导体层形成栅极-基体接触薄膜晶体管而不形成独立的基体接触区成为可能。
参考图5A和5B,层间绝缘层112被形成在基板100的整个表面上。层间绝缘层112可以是氮化硅层、氧化硅层或它们的多层。
然后,层间绝缘层112和栅极绝缘层105被蚀刻以形成使半导体层104的源极区107和漏极区108暴露的接触孔113。然后,源电极114和漏电极115通过接触孔113被连接至源极区107和漏极区108。源电极114和漏电极115可以由钼(Mo)、铬(Cr)、钨(W)、铝-钕(Al-Nd)、钛(Ti)、钼钨(MoW)和铝(Al)中的一种形成。
示例性实施例2
图6A、7A和8A为示出根据本发明示例性实施例2的制造薄膜晶体管的过程的平面图。图6B、7B和8B为分别沿着图6A、7A和8A的线B-B′的剖面图。
参考图6A和6B,缓冲层601被形成在基板600上,然后多晶硅层602被形成在缓冲层601上。参考图7A和7B,同示例性实施例1不同的是,最初只有多晶硅层602被图案化以形成半导体层603。
绝缘层被沉积在基板600的整个表面上。绝缘层被图案化从而形成栅极绝缘层604。栅极绝缘层604的图案化使连接至半导体层603的沟道区607的半导体层603的边缘暴露。
然后,第一杂质被注入半导体层603暴露的边缘以形成基体接触区608。第二杂质被注入半导体层603的另外的部分以形成源极区605和漏极区606。沟道区607是与基体接触区608接触的半导体层603的非掺杂部分,且被布置在源极区605和漏极区606之间。第一和第二杂质可以是N型或P型杂质,只要它们是不同类型的杂质。基体接触区608的长度c可以等于或大于沟道区607的长度。
参考图8A和8B,栅电极材料被沉积在栅极绝缘层604上。然后,栅电极材料被图案化以形成叠盖沟道区607和基体接触区608的栅电极609。栅电极609通过将被图案化的栅极绝缘层604图案化时形成的孔而与基体接触区608接触,从而形成完成的栅极-基体接触薄膜晶体管。
层间绝缘层610被形成在基板的整个表面上。然后,层间绝缘层610和栅极绝缘层604被蚀刻以形成使半导体层603的源极区605和漏极区606暴露的接触孔611。源电极612和漏电极613通过接触孔611被连接至源极区605和漏极区606。
示例性实施例3
现在将描述利用根据本发明示例性实施例3的、利用半导体层的边缘在半导体层中吸除(gettering)结晶诱导金属的过程。结晶诱导金属被用于使多晶硅层结晶成示例性实施例1和2的半导体层。
该吸除过程指通过执行退火过程,将保留在沟道形成区中的结晶诱导金属吸除到半导体层的暴露的边缘中。在杂质特别是N型杂质被注入半导体层的边缘后执行该退火过程。
因为暴露的边缘接触沟道区,所以利用暴露的边缘的吸除过程具有高吸除效率,因为沟道区中存在的结晶诱导金属只需移动短距离就可到达暴露的边缘。
在450℃到900℃的温度范围内,退火过程执行约30秒至约10小时。低于约450℃的退火温度可能不会有效地从半导体层转移结晶诱导金属。超过900℃的退火温度可能使基板变形。退火时间少于30秒可能不会有效地移动结晶诱导金属。退火时间超过10小时可能使基板变形,增加TFT的制造成本,并且减少产率。
示例性实施例4
图9为根据本发明示例性实施例的包括TFT的有机发光二极管显示装置的剖面图。参考图9,绝缘层116被形成在根据如图5B所示的本发明示例性实施例的包括TFT在内的基板100的整个表面上。绝缘层116可以由选自氧化硅层、氮化硅层、玻璃上硅层的无机层或者选自聚酰亚胺、苯二氮系列树脂或丙烯酸脂的有机层形成。绝缘层116可以包括堆积形成的无机层和有机层。
绝缘层116被蚀刻以形成使源电极114和漏电极115之一暴露的孔117。第一电极118被形成以通过孔117且被连接至源电极114和漏电极115之一。第一电极118可以是阳极或阴极。当第一电极118是阳极时,它可由诸如氧化铟锡(ITO)、氧化铟锌(IZO)或氧化铟锡锌(ITZO)之类的透明传导材料形成。当第一电极118是阴极时,它可由Mg、Ca、Al、Ag、Ba或其合金形成。
然后,像素限定层119被形成在第一电极118上。像素限定层119具有使第一电极118的表面暴露的开口。包括发射层的有机层120被形成在第一电极118上。有机层120可以进一步包括由空穴注入层、空穴传输层、空穴阻挡层、电子阻挡层、电子注入层和电子传输层构成的组中选择的至少之一。然后,第二电极121被形成在有机层120上以完成有机发光二极管显示装置。
因为实现了不包括独立基体接触区的基体接触区,根据本发明方面的薄膜晶体管比现有的栅极-基体接触薄膜晶体管具有更小的面积。基体接触区由半导体层的边缘区形成。
尽管已示出和描述了本发明的几个示例性实施例,但本领域技术人员应当理解,可以对这些实施例做出改变而不违背本发明的原理和精神,本发明的范围由权利要求书及其等同物限定。

Claims (6)

1.一种制造薄膜晶体管的方法,该方法包括:
通过利用结晶诱导金属将非晶硅层结晶成多晶硅层来在基板上形成半导体层;
在所述半导体层上形成栅极绝缘层,从而使所述半导体层的边缘暴露;
利用所述栅极绝缘层作为掩模,将N型杂质注入所述半导体层的暴露的边缘;
将所述基板退火,以将保留在所述半导体层中的所述晶体诱导金属吸除到所述半导体层的暴露的边缘中;
在所述栅极绝缘层上形成与所述半导体层的暴露的边缘接触的栅电极;
在所述栅电极上形成层间绝缘层;以及
在所述层间绝缘层上形成分别被电连接至所述半导体层的源极区和漏极区的源电极和漏电极。
2.根据权利要求1所述的制造薄膜晶体管的方法,其中所述半导体层的暴露的边缘被连接至所述半导体层的沟道区。
3.根据权利要求2所述的制造薄膜晶体管的方法,其中所述半导体层的暴露的边缘的宽度不大于0.1μm。
4.根据权利要求1所述的制造薄膜晶体管的方法,其中形成半导体层和栅极绝缘层包括:
在所述基板上形成多晶硅层;
在所述多晶硅层上沉积绝缘层;以及
在所述多晶硅层和所述绝缘层上执行一次图案化工艺以形成所述半导体层和所述栅极绝缘层。
5.根据权利要求4所述的制造薄膜晶体管的方法,其中在所述多晶硅层和所述绝缘层上执行一次图案化工艺包括使所述绝缘层的临界尺寸偏差大于所述多晶硅层的临界尺寸偏差。
6.根据权利要求1所述的制造薄膜晶体管的方法,其中退火在450℃到900℃的温度下执行30秒到10小时。
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