CN101578696B - 减少焊接疲劳的动态焊盘尺寸 - Google Patents
减少焊接疲劳的动态焊盘尺寸 Download PDFInfo
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Abstract
提供一种半导体器件,所述半导体器件包括衬底(501),所述衬底(501)具有在其上设置的多个接合焊盘(503)。每个接合焊盘在与衬底平行的方向上具有长轴和短轴,并且长轴与短轴的比随着接合焊盘距衬底中心的距离而增加。
Description
技术领域
本发明一般涉及焊点,并且更具体而言,涉及能够用于改善焊点完整性的接合焊盘设计。
背景技术
焊点广泛地用于整个半导体技术中,其作为一种用于在器件组件之间形成物理和/或电连接的便捷手段。这些组件可以例如是管芯和IC封装衬底,或IC封装衬底和印刷电路板(PCB)。通常,焊点形成包括在接合焊盘上机械或电化学沉积焊料,随后是回流焊接,所述接合焊盘设置在要接合在一起的组件中的至少一个的表面上。
图1示出在球栅阵列(BGA)衬底103和管芯105之间形成的典型的焊点101。这样的焊点在倒装芯片封装中是常见的,其包括在BGA衬底103上设置的第一接合焊盘109和在管芯105上设置的第二接合焊盘111之间跨接的一部分焊料107。在所说明的特定器件中,BGA衬底103配置有限定第一接合焊盘109的阻焊层113。因而,形成到BGA衬底103的焊点是阻焊层限定的(SMD)。相反,形成到管芯105的焊点是非阻焊层限定的(NSMD)。
在典型的倒装芯片器件中,管芯105和BGA衬底103具有不同的热膨胀系数。因此,当器件经受热循环时,变化的应力和应变量被施加到焊点。随着时间过去,这些力量能够造成焊点破裂,这会导致焊点和/或器件的机械和/或电故障。
一段时间以来,焊点故障以及对缩短包含焊点的半导体器件的寿命的影响是本领域中公认的问题。因此,在本领域中提出了各种方法来使焊点故障最小化,并提高使用焊点的半导体器件的可靠性。然而这些方法中的大部分都是不令人满意的,因为它们使制造工艺变得非常复杂。
因此,在本领域中需要一种用于形成更耐应力和应变并且显示出提高寿命的焊点的简单方法。在本领域中还需要根据这种方法而制备的器件。利用在此公开的器件和方法可以实现这些和其他需求。
附图说明
图1是现有技术焊点的实例;
图2是说明BGA中的布线问题的实例;
图3是描述封装管芯中的应力的实例;
图4是描述封装管芯中的应力的实例;
图5是BGA中的接合焊盘的实例;
图6是描述图5的BGA的中心和末端的焊点的实例;
图7是描述根据本文的教导,已被修改的图5的BGA的中心和末端的焊点的实例;
图8是将图7的BGA中的接合焊盘与图6的BGA中的接合焊盘相比较的实例;
图9是将图7的BGA中的接合焊盘与图6的BGA中的接合焊盘相比较的实例;以及
图10是焊料凸块面积增加的%与阵列尺寸的函数关系的曲线图。
具体实施方式
一方面,提供一种制造半导体器件的方法。根据本方法,提供衬底,以及多个接合焊盘被限定在衬底上。每个接合焊盘在与衬底平行的方向上具有长轴和短轴,并且长轴与短轴的比随着接合焊盘与衬底中心相距的距离而增加。
另一方面,提供一种半导体器件,所述半导体器件包括衬底,该衬底具有在其上设置的多个接合焊盘。每个接合焊盘与衬底平行的方向上具有长轴和短轴,并且长轴与短轴的比随着接合焊盘与衬底中心相距的距离而增加。
图2示出在利用图1所描述类型的焊点的BGA衬底中常用的布线。在此可以看出,其中的BGA衬底201包括一系列接合焊盘203,所述接合焊盘通过一系列互连205与BGA衬底201的电路电接触。每个接合焊盘203配置有相应的阻焊层开口207,其比接合焊盘本身的直径小。需要在一定程度上调节接合焊盘203和阻焊层开口207之间的位置误差,所以阻焊层开口207的较小直径是必要的。
如图2所示,接合焊盘203的尺寸由BGA衬底201中的布线需求而限制,并且因此阻焊层开口207的尺寸由BGA衬底201中的布线需求而限制。特别是,如果在还没有增加BGA衬底201的整个尺寸(并且因此没有增加并入BGA衬底201的器件的整个尺寸)的情况下增加接合焊盘203的尺寸,则减小了相邻接合焊盘203间的距离,并且互连205的布线因此成为更具挑战性的命题。如果相邻接合焊盘203过于紧密地设置在一起,则普通的放置误差会导致接合焊盘与在接合焊盘间延伸的任意互连之间的短路或串扰。
图3-4示出与典型的倒装芯片封装301有关的CTE应力的方向性,倒装芯片封装301包括管芯303、BGA衬底305和位于管芯中心的BGA(未示出)。在倒装芯片封装301中给定点处(并且特别是在倒装芯片封装的BGA中的给定点处)的CTE应力差分ΔCTE主要由公式1给出:
ΔCTE=ΔT*(CTE衬底-CTE管芯)(公式1)
其中:
ΔT是暴露器件的温度范围;
CTE衬底是衬底的热膨胀系数;以及
CTE管芯是管芯的热膨胀系数。
拉伸距离ds由公式2给出:
ds=ΔCTE*L (公式2)
其中:
L是距中性点(通常是距BGA的中心)的距离。
因此,从上述内容可以看出,在应用于倒装芯片封装中的典型矩形BGA中,CTE应力随着与BGA 301中心相距的距离的增加而成比例增加。因此,可以认识到沿BGA中的径向轴的CTE应力将是最大值,因为在那些点处的焊点与在同一行或列中的其他焊点相比,距BGA中心最远。
在图3-4中所描述类型的倒装芯片封装301中,发现在沿着BGA衬底305附近的焊点的一部分更普遍的发生焊点故障,其中,焊点是最窄的并且是阻焊层限定的。此外,已经发现焊接故障在球栅阵列(BGA)中所有焊点之中不是随机分布的。而是,发现当焊点远离BGA的中心时焊点故障更频繁地发生,并且尤其沿着CTE应力为最大值的BGA的径向轴普遍发生。焊点故障的更随机分布是可优选的,此后,故障的焊点将更均匀地分布在BGA上并且能够通过适当的冗余来调整。
抛开理论的束缚,相信焊点故障的分布与CTE应力的相对分布直接相关。以减小焊点故障为目的的许多现有技术方法忽略了这个因素,并且以相同的方式处理在BGA内所有的焊点。这种类型的方法示例包括意图通过采用凸起的接合焊盘来减少焊点疲劳,以由此增加接合焊盘/焊点界面的表面积的方法。从理论上讲,这种方式将最大的CTE应力区域移动得更靠近焊点的中心,其中,焊点较厚并且因此认为能够允许较大的CTE应力水平。然而,虽然这种方法可以增加各个焊点的相对寿命,但是它们导致与如上所述相同的焊点故障的非随机模式。
另一种用于减少焊点故障的可能方法是简单地增加焊点的尺寸。但是,在大部分应用中,这样做是不实用的,因为这需要相应增加接合焊盘的尺寸,这将引起布线问题和/或增加器件的整体尺寸。此外,正如上面描述的方法,尽管这种方法会致使各个焊点的寿命较长,但是其不会产生焊点故障的随机模式。
现在已经发现,上述提到的在本领域中的需求可以通过提供在最大热膨胀和最大CTE应力的方向上拉长的接合焊盘来满足。这可以例如通过将接合焊盘设计成使得每个接合焊盘具有长轴和短轴(在与衬底平行的方向上)以及设计成使得长轴与短轴的比随着接合焊盘与衬底中心相距的距离而增加来实现。可优选地,每个接合焊盘的长轴与在焊盘上形成的焊点的热膨胀(在与衬底平行的方向上)的长轴对准。当然,可以认识到,根据局部CTE应力水平来修改接合焊盘尺寸的其他方法也可用于类似的目的。
在得到的器件中,任何接合焊盘和/或阻焊层开口的最大尺寸与在该位置的焊点经受的相对CTE应力相匹配,并且任何接合焊盘和/或阻焊层开口的最大尺寸可优选与在该位置的焊点经受的相对CTE应力成比例。由于焊点故障最频繁地发生在接合焊盘/焊点界面附近,所以这种方法具有增加接合焊盘和/或相应的阻焊层开口尺寸的效果,并因此在最需要的方向上增加了焊点的尺寸和强度。另一方面,因为接合焊盘的整体尺寸不需要显著增加,即使接合焊盘的整体尺寸根本不增加(接合焊盘的尺寸可以在CTE应力并非很大的其他方向上减小),在对器件中的可布线性影响极小的情况下也可以获得对焊接疲劳的抵抗性。
参照图5-9可以更好地理解本文所描述的方法论。图5描述了传统球栅阵列(BGA)401中的接合焊盘403的布置。图6更加详细地示出在BGA 401的中心和末端位置处的接合焊盘403以及相关的阻焊层开口405。值得注意的是,接合焊盘403以及相关的阻焊层开口405在整个BGA 401的所有位置处具有相同的各个尺寸。
图7示出图5-6的BGA中的接合焊盘可以如何根据本文所教导的方法来改进,以提高它们对CTE应力的抵抗性。正如在此所看到的,在此描述的BGA 501的接合焊盘503以及它们相关的阻焊层开口505沿着从BGA 501的中心径向延伸的轴而被拉长,并且与接合焊盘503距BGA 501的中心的距离成比例。因此,对这些接合焊盘形成的焊点的尺寸沿着最大的CTE应力差分的轴是最大的。
从上述内容可以认识到,在此公开的方法论可以用于在BGA中最需要的地方有效地分配焊点厚度,以调整CTE应力差分。因此,焊点故障不太可能发生,并且当其发生时,趋向于在BGA上随机分布,其中,可以通过在BGA中典型设计的适当的冗余来调整。
图8-9示出图7的BGA 501内的特定接合焊盘的尺寸变化的一个特定的、非限制性的示例。图8示出从图7中描述的BGA 501的顶端中部截取的两个相邻的接合焊盘503(以及它们的有关阻焊层开口505),而图9示出从图7中描述的BGA 501的顶端右部的两个相邻的接合焊盘503(以及它们的有关阻焊层开口505)。在每种情况下,为了对比,将接合焊盘403以及各自的阻焊层开口405的最初尺寸用虚线表示。
在图8所描述的接合焊盘的情形中,接合焊盘在垂直方向上被拉长了16.3微米,因而致使接合焊盘表面积增加了19%(从5674μm2增加到6761μm2)。但是,用于布线的焊盘之间的间隔没有受这种变化的影响,并且仍保持在102.2微米。可以认识到,沿着与BGA一侧平行的任何轴将获得类似的结果(相对于布线来说)。
在图9所描述的接合焊盘的情形中,接合焊盘沿着纵轴被拉长了21.5微米,因而致使接合焊盘表面积增加了25%(从5674μn2增加到7100μm2)。通过该变化,用于布线的接合焊盘之间的间隔略微减小了7.2微米(减小了约7%)。但是,由于它们放置在BGA上,所以这些接合焊盘代表根据该特定实施例中的方法论的布线的最大减小量。因此,大部分BGA中,期望布线间隔的平均减小量远远低于这个量。
图10是当已经以图7中描述的方式拉长的椭圆形接合焊盘代替阵列内的传统圆形接合焊盘时,接合焊盘面积增加的%与阵列尺寸的函数关系的曲线图。在此可以看出,接合焊盘面积增加的%随着阵列尺寸基本呈线性增加。与上文提及的布线面积的适度减小相比,该曲线图表明本文所教导的方法可用于显著增加沿着CTE应力最大(由面积%的显著增加表示)的轴的焊点尺寸,布线面积仅有最小的附带减小。这又会得到焊点寿命的增加并且提高产品耐久性。
本发明的上述描述是说明性的,并且不意图限制本发明。因而,可以认识到,在不脱离本发明范围的情况下,可对上文描述的实施例作出各种附加、替换和改进。因此,应当参照所附的权利要求来理解本发明的范围。
Claims (16)
1.一种制造半导体器件的方法,包括:
提供衬底;以及
在所述衬底上形成多个接合焊盘,其中每个接合焊盘在与所述衬底平行的平面中具有长轴和短轴,并且其中所述长轴与所述短轴的比随着接合焊盘与所述衬底中心相距的距离而增加。
2.根据权利要求1所述的方法,进一步包括:
在所述多个接合焊盘中的每一个上形成焊点。
3.根据权利要求2所述的方法,其中每个接合焊盘的所述长轴在与所述衬底平行的方向上基本平行于所述焊点的热膨胀的长轴。
4.根据权利要求2所述的方法,其中所述衬底具有在其上设置的阻焊剂层,并且其中通过包括选择性去除部分阻焊剂的工艺来形成所述多个接合焊盘。
5.根据权利要求2所述的方法,其中所述衬底是封装衬底,并且其中每个焊点在第一端附着到所述多个接合焊盘之一,并且在第二端附着到半导体管芯。
6.根据权利要求2所述的方法,其中在平面中任何方向上的接合焊盘的尺寸与该方向上焊点所经受的相对应变成比例。
7.根据权利要求1所述的方法,其中所述多个接合焊盘中的每一个的长轴与短轴的比与接合焊盘距所述衬底中心的距离基本成比例。
8.根据权利要求7所述的方法,其中所述衬底具有在其上设置的管芯,并且其中所述多个接合焊盘中的任意一个的长轴与短轴的比ds由下述公式给出:
ds=ΔCTE*L
其中L是与所述衬底中心相距的距离,并且其中ΔCTE是所述管芯和所述衬底之间的CTE应力差分。
9.根据权利要求8所述的方法,其中ΔCTE由下述公式给出:
ΔCTE=ΔT*(CTE衬底-CTE管芯)
其中:
ΔT是暴露所述器件的温度范围;
CTE衬底是所述衬底的热膨胀系数;以及
CTE管芯是所述管芯的热膨胀系数。
10.根据权利要求1所述的方法,其中所述多个接合焊盘中的每一个在沿着与所述衬底平行的平面截取的横截面中基本是椭圆形状。
11.一种半导体器件,包括:
衬底,具有在其上设置的多个接合焊盘;
其中每个接合焊盘在与所述衬底平行的方向上具有长轴和短轴,并且其中所述长轴与所述短轴的比随着接合焊盘与所述衬底中心相距的距离而增加。
12.根据权利要求11所述的器件,其中所述多个接合焊盘中的每一个的所述长轴与所述短轴的比与所述接合焊盘距所述衬底中心的距离基本成比例。
13.根据权利要求12所述的器件,进一步包括在所述衬底上设置的管芯,并且其中所述多个接合焊盘中的任意一个的所述长轴与所述短轴的比ds由下述公式给出:
ds=ΔCTE*L
其中L是距所述衬底中心的距离,并且其中ΔCTE是所述管芯和所述衬底之间的CTE应力差分。
14.根据权利要求13所述的器件,其中ΔCTE由下述公式给出:
ΔCTE=ΔT*(CTE衬底-CTE管芯)
其中:
ΔT是暴露所述器件的温度范围;
CTE衬底是所述衬底的热膨胀系数;以及
CTE管芯是所述管芯的热膨胀系数。
15.根据权利要求11所述的器件,其中所述多个接合焊盘中的每一个基本上是椭圆形状。
16.根据权利要求11所述的器件,其中所述半导体器件是倒装芯片器件。
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US11/701,651 US7772104B2 (en) | 2007-02-02 | 2007-02-02 | Dynamic pad size to reduce solder fatigue |
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PCT/US2008/051780 WO2008097714A1 (en) | 2007-02-02 | 2008-01-23 | Dynamic pad size to reduce solder fatigue |
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Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7361581B2 (en) * | 2004-11-23 | 2008-04-22 | International Business Machines Corporation | High surface area aluminum bond pad for through-wafer connections to an electronic package |
JP5350604B2 (ja) * | 2007-05-16 | 2013-11-27 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US8178392B2 (en) * | 2007-05-18 | 2012-05-15 | Stats Chippac Ltd. | Electronic system with expansion feature |
JP5232460B2 (ja) * | 2007-12-12 | 2013-07-10 | 新光電気工業株式会社 | 半導体パッケージ |
JP5185885B2 (ja) * | 2009-05-21 | 2013-04-17 | 新光電気工業株式会社 | 配線基板および半導体装置 |
US8446007B2 (en) | 2009-10-20 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform alignment of wafer bumps with substrate solders |
CN102208386A (zh) * | 2010-03-29 | 2011-10-05 | 广达电脑股份有限公司 | 具有球形焊点的集成电路封装元件 |
US8394672B2 (en) * | 2010-08-14 | 2013-03-12 | Advanced Micro Devices, Inc. | Method of manufacturing and assembling semiconductor chips with offset pads |
KR20120018894A (ko) * | 2010-08-24 | 2012-03-06 | 삼성전자주식회사 | 패키지 기판 및 이를 갖는 플립 칩 패키지 |
US20120098120A1 (en) * | 2010-10-21 | 2012-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Centripetal layout for low stress chip package |
US8742477B1 (en) * | 2010-12-06 | 2014-06-03 | Xilinx, Inc. | Elliptical through silicon vias for active interposers |
US9053943B2 (en) * | 2011-06-24 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad design for improved routing and reduced package stress |
US20120329263A1 (en) * | 2011-06-24 | 2012-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a bond pad design for improved routing and reduced package stress |
US8598691B2 (en) * | 2011-09-09 | 2013-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing and packaging thereof |
US9564412B2 (en) | 2011-12-06 | 2017-02-07 | Intel Corporation | Shaped and oriented solder joints |
US9233835B2 (en) * | 2011-12-06 | 2016-01-12 | Intel Corporation | Shaped and oriented solder joints |
JP2015053390A (ja) * | 2013-09-06 | 2015-03-19 | 株式会社デンソー | プリント配線板および半導体装置 |
US9070657B2 (en) | 2013-10-08 | 2015-06-30 | Freescale Semiconductor, Inc. | Heat conductive substrate for integrated circuit package |
US9824990B2 (en) | 2014-06-12 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
US9881857B2 (en) * | 2014-06-12 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
WO2015198839A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2015198838A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2015198837A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2015198836A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
US10050003B2 (en) * | 2014-12-08 | 2018-08-14 | Esilicon Corporation | Elongated pad structure |
CN106971945B (zh) * | 2016-01-14 | 2021-01-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
WO2017179574A1 (ja) * | 2016-04-11 | 2017-10-19 | 株式会社村田製作所 | 弾性波素子および弾性波装置 |
US20180047692A1 (en) * | 2016-08-10 | 2018-02-15 | Amkor Technology, Inc. | Method and System for Packing Optimization of Semiconductor Devices |
US9865557B1 (en) | 2016-08-30 | 2018-01-09 | International Business Machines Corporation | Reduction of solder interconnect stress |
US10090271B1 (en) | 2017-06-28 | 2018-10-02 | International Business Machines Corporation | Metal pad modification |
US10818624B2 (en) * | 2017-10-24 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for manufacturing the same |
US10573573B2 (en) | 2018-03-20 | 2020-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package and package-on-package structure having elliptical conductive columns |
US10943880B2 (en) | 2019-05-16 | 2021-03-09 | Advanced Micro Devices, Inc. | Semiconductor chip with reduced pitch conductive pillars |
US10825789B1 (en) | 2019-08-26 | 2020-11-03 | Nxp B.V. | Underbump metallization dimension variation with improved reliability |
US11211319B2 (en) * | 2019-11-21 | 2021-12-28 | Advanced Semiconductor Engineering, Inc. | Device structure |
KR20220065360A (ko) * | 2020-11-13 | 2022-05-20 | 삼성전자주식회사 | 반도체 패키지 |
CN113130430A (zh) * | 2021-04-16 | 2021-07-16 | 南通大学 | 一种适用于lga封装的焊点及包含其的系统级封装结构 |
EP4095898A1 (en) | 2021-05-25 | 2022-11-30 | Mitsubishi Electric R&D Centre Europe B.V. | Thermally improved pcb for semiconductor power die connected by via technique and assembly using such pcb |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859474A (en) * | 1997-04-23 | 1999-01-12 | Lsi Logic Corporation | Reflow ball grid array assembly |
US6268568B1 (en) * | 1999-05-04 | 2001-07-31 | Anam Semiconductor, Inc. | Printed circuit board with oval solder ball lands for BGA semiconductor packages |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5404047A (en) | 1992-07-17 | 1995-04-04 | Lsi Logic Corporation | Semiconductor die having a high density array of composite bond pads |
US5880987A (en) | 1997-07-14 | 1999-03-09 | Micron Technology, Inc. | Architecture and package orientation for high speed memory devices |
DE19839760A1 (de) * | 1998-09-01 | 2000-03-02 | Bosch Gmbh Robert | Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung |
US6445603B1 (en) | 2000-08-21 | 2002-09-03 | Micron Technology, Inc. | Architecture, package orientation and assembly of memory devices |
JP3661693B2 (ja) * | 2003-06-02 | 2005-06-15 | セイコーエプソン株式会社 | 配線基板、積層配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
KR100754069B1 (ko) | 2004-06-02 | 2007-08-31 | 삼성전기주식회사 | 플립칩 실장 기술을 이용한 반도체 패키지 및 패키징 방법 |
JP2006165252A (ja) | 2004-12-07 | 2006-06-22 | Shinko Electric Ind Co Ltd | チップ内蔵基板の製造方法 |
-
2007
- 2007-02-02 US US11/701,651 patent/US7772104B2/en active Active
-
2008
- 2008-01-23 WO PCT/US2008/051780 patent/WO2008097714A1/en active Application Filing
- 2008-01-23 TW TW097102535A patent/TWI445106B/zh not_active IP Right Cessation
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859474A (en) * | 1997-04-23 | 1999-01-12 | Lsi Logic Corporation | Reflow ball grid array assembly |
US6268568B1 (en) * | 1999-05-04 | 2001-07-31 | Anam Semiconductor, Inc. | Printed circuit board with oval solder ball lands for BGA semiconductor packages |
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US8008786B2 (en) | 2011-08-30 |
KR101395365B1 (ko) | 2014-05-14 |
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US20080185735A1 (en) | 2008-08-07 |
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