CN101594129B - Duty cycle correcting circuit and method of correcting duty cycle - Google Patents
Duty cycle correcting circuit and method of correcting duty cycle Download PDFInfo
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- CN101594129B CN101594129B CN2009101186149A CN200910118614A CN101594129B CN 101594129 B CN101594129 B CN 101594129B CN 2009101186149 A CN2009101186149 A CN 2009101186149A CN 200910118614 A CN200910118614 A CN 200910118614A CN 101594129 B CN101594129 B CN 101594129B
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Abstract
The invention discloses a duty cycle correcting circuit and a method of correcting the duty cycle. The duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal. When a first level period of the correction clock signal is wider than a second level period of the correction clock signal, the duty ratio detection signal is kept at an enabled state. When the first level period of the correction clock signal is not wider than the second level period, the duty ratio detection signal is inhibited.
Description
The cross reference of related application
The present invention requires to be committed on May 30th, 2008 priority of korean patent application 10-2008-0051064 number of Korean Patent office, and its full content is herein incorporated by reference.
Technical field
Here described embodiment relates to a kind of semiconductor integrated circuit (IC) devices and methods therefor, more specifically, relates to a kind of method that is included in the duty ratio of duty-cycle correction circuit and position signal in the semiconducter IC device.
Background technology
In general, the semiconducter IC device, for example synchronous DRAM (SDRAM) device is operated the operation rate with raising through using clock signal.For example, the semiconducter IC device comprises clock buffer and cushions external timing signal with portion's use within it.In some cases, the semiconducter IC device uses delay lock loop (DLL) circuit or phase-locked loop (PLL) circuit to produce and use internal clock signal, and the phase difference of this internal clock signal and external timing signal is calibrated.In the internal clock signal that in the semiconducter IC device, uses, high level period and the ratio of low level between the period are that duty ratio preferably remained on predetermined ratio 50: 50.But because the semiconducter IC device comprises multiple delay element, the duty ratio of internal clock signal changes easily.
Because semiconducter IC device high-speed cruising, the utilance of clock signal increases, and wherein need have the clock of stable duty ratio.Therefore, each semiconducter IC device comprises that duty-cycle correction circuit comes the duty ratio of stable clock signal.In order during the high speed operation of semiconducter IC device, to utilize the stable clock signal, it is more and more important that duty-cycle correction circuit becomes.
The kind of duty-cycle correction circuit can be divided into analogue type and numeric type.The benefit of numeric type duty-cycle correction circuit is to use the area of less semiconducter IC device and high operating rate.The numeric type duty-cycle correction circuit comprises multistage driver, and changes the driving force of driver in response to digital code, and adjusts the duty ratio of clock signal.For example, in the two-stage drive device, the driving force of the driving force of the part of boosting of first order driver and the step-down part of second level driver is adjusted, and changes the width of the low level period of clock signal thus.Therefore, this digital code is for producing the binary code and the signal that this binary code produced of decoding through the use universal counter.Therefore, when changing the logical value of digital code, the driving force of each driver of two-stage drive device is sequentially changed.
Duty-cycle correction circuit is configured to make that the driving force of one of a plurality of drivers is changed earlier in response to digital code, and the driving force of other driver also is changed.For example; Duty-cycle correction circuit is operated to such an extent that partly be configured to have maximum driving force based on the step-down of boost part and the second level driver of the default value first order driver of digital code, and the driving force of the part of boosting of first order driver reduces gradually and is minimized.In addition, when digital code changed, the driving force of the step-down of second level driver part reduced gradually and is minimized.But if the driving force of the part of boosting of first order driver is minimized, the driving force of then whole first order driver reduces, and fan-out poor (fanout difference) can increase between the two-stage drive device.As a result, all drivers all can be worked by error.That is to say, only consider that duty cycle correction is operated to design duty-cycle correction circuit, and do not consider the fan-out between the driver.Therefore, the stability of operation reduces.
Summary of the invention
The present invention discloses a kind of duty-cycle correction circuit, and a kind of correction duty ratio method of implementing stable duty cycle correction operation.
On the one hand, a kind of duty-cycle correction circuit comprises: the duty ratio control unit, and it is configured to alternately change the boost logical value of control signal and multidigit step-down control signal of multidigit in response to the duty ratio detection signal; The duty cycle correction unit, it is configured to boost driving force that control signal and multidigit step-down control signal adjust first driver and second driver with the output calibration clock signal in response to multidigit; And duty ratio detecting unit; Its duty ratio that is configured to detect position is to produce the duty ratio detection signal; And be configured to be wider than its second level keeps the duty ratio detection signal during period enabled, and be not wider than second level and forbid the duty ratio detection signal during period when the first level period when the first level period of position signal.
On the other hand; A kind of duty-cycle correction circuit; Comprise: counting unit; It is configured to produce the multidigit count signal that logical value increases with predetermined unit, and is configured to when the duty ratio detection signal is enabled, increase the logical value of multidigit count signal, and when the duty ratio detection signal is under an embargo, locks the logical value of multidigit count signal; Decoding unit, it is configured to logical value according to the least significant bit of multidigit count signal and changes the boost logical value of one of control signal and multidigit step-down control signal of multidigit; And the duty cycle correction unit, it is configured to boost driving force that control signal and multidigit step-down control signal adjust first driver and second driver with the output calibration clock signal in response to multidigit.
On the other hand; A kind of duty ratio correction method; It proofreaies and correct the duty ratio in the duty-cycle correction circuit; Said duty-cycle correction circuit comprises first driver and second driver that is connected in series and the duty ratio of proofreading and correct input clock signal to produce the position signal, and said method comprises: the duty ratio that detects the position signal is to produce the duty ratio detection signal; Change the duty ratio of the driving force of first driver with the corrected clock signal in response to the duty ratio detection signal; The duty ratio that detects the position signal is to produce the duty ratio detection signal; And change the duty ratio of the driving force of second driver with the corrected clock signal in response to the duty ratio detection signal; Wherein be wider than its second level during the period when the first level period of position signal; The step that produces said duty ratio detection signal keeps the enabled of duty ratio detection signal; And be not wider than second level during period when the first level period, the step that produces said duty ratio detection signal is forbidden the duty ratio detection signal.
In duty-cycle correction circuit and method according to the embodiment of the invention, in the multistage driver of the duty ratio of proofreading and correct input clock signal, the driving force of driver alternately changes, and prevents that thus the fan-out difference between the driver from increasing.Therefore, can realize stable duty cycle correction operation.
In addition, in duty-cycle correction circuit and method, can in the stability of each driver in guaranteeing multistage driver, carry out the duty cycle correction operation according to the embodiment of the invention.Therefore, the duty ratio of position signal exactly.
These and other characteristic, aspect and embodiment will explain in following embodiment.
Description of drawings
Accompanying drawings characteristic, aspect and embodiment, wherein:
Fig. 1 is the block schematic diagram according to the exemplary duty-cycle correction circuit device of an embodiment;
Fig. 2 is the sketch map according to the included exemplary decoding unit of the device of Fig. 1 of an embodiment;
Fig. 3 is the sketch map according to the included exemplary duty cycle correction unit of the device of Fig. 1 of an embodiment;
Fig. 4 is the sketch map according to another the exemplary decoding unit in the device that can be used for Fig. 1 of another embodiment; And
Fig. 5 is the sketch map according to another the exemplary duty cycle correction unit in the device that can be used for Fig. 1 of another embodiment.
Embodiment
Fig. 1 is the block schematic diagram according to the exemplary duty-cycle correction circuit device of an embodiment.In Fig. 1, duty-cycle correction circuit 1 can be configured to comprise: counting unit 10, decoding unit 20, duty cycle correction unit 30 and duty ratio detecting unit 40.
Decoding unit 20 decodable code n position count signal cnt < 1:n>are to produce (n-1) position boost control signal plup < 1:n-1>and (n-1) potential drop pressure-controlled signal pldn < 1:n-1 >.In addition, decoding unit 20 can be confirmed the logical value of the least significant bit of n position count signal cnt < 1:n >, can change (n-1) position the boost logical value of control signal plup < 1:n-1>or (n-1) logical value of potential drop pressure-controlled signal pldn < 1:n-1>then.For example, when the logical value of the least significant bit of n position count signal cnt < 1:n>was 0, decoding unit 20 can change 1 with the boost logical value of control signal plup < 1:n-1>of (n-1) position.When the logical value of the least significant bit of n position count signal cnt < 1:n>was 1, decoding unit 20 can change 1 with the logical value of (n-1) potential drop pressure-controlled signal pldn < 1:n-1 >.
When counting unit 10 is unit when changing logical value with 1, can produce n position count signal cnt < 1:n >, so the logical value of the least significant bit of n position count signal cnt < 1:n>alternately has 0 or 1 value.Therefore, (n-1) the position logical value of control signal plup < 1:n-1>of boosting alternately changes with (n-1) logical value of potential drop pressure-controlled signal pldn < 1:n-1 >.In this case, decoding unit 20 can be confirmed the logical value of the least significant bit of n position count signal cnt < 1:n >.Decoding unit 20 also can be confirmed the logical value of second low level.
Duty cycle correction unit 30 can boost duty ratio that the logical value of control signal plup < 1:n-1>and (n-1) logical value of potential drop pressure-controlled signal pldn < 1:n-1>proofread and correct input clock signal clk_in with output calibration clock signal clk_crt in response to (n-1) position.
Duty cycle correction unit 30 can be configured to comprise the multistage driver with in following detailed description.Duty cycle correction unit 30 can use first driver and second driver that is connected in series, and the duty ratio of recoverable input clock signal clk_in is with output calibration clock signal clk_crt.At this, each in first driver and second driver can comprise boost part and step-down part.
The driving force of the part of boosting of first driver can be boosted control signal plup < 1:n-1>and changes in response to (n-1) position, and the driving force of the step-down of second driver part can change in response to (n-1) potential drop pressure-controlled signal pldn < 1:n-1 >.(n-1) the position control signal plup < 1:n-1>that boosts can be imported into the part of boosting of second driver, and (n-1) potential drop pressure-controlled signal pldn < 1:n-1>can be imported into the step-down part of first driver.
As stated, (n-1) the position logical value of control signal plup < 1:n-1>of boosting alternately changes through 1 with (n-1) logical value of potential drop pressure-controlled signal pldn < 1:n-1 >.Therefore; Can alternately change in response to the boost driving force of step-down part of the boost driving force of part and second driver that can operate in response to the logical value of (n-1) potential drop pressure-controlled signal pldn < 1:n-1>of first driver of control signal plup < 1:n-1>and operation of (n-1) position.Therefore, boosting of first driver partly alternately changes their driving force with the step-down part of second driver.Therefore, the fan-out difference between first driver and second driver is configured to be no more than preset range, improves the stability of operation thus.
The duty that duty ratio detecting unit 40 can detect position signal clk_crt recently produces duty ratio detection signal dtdet.When the initial operation of duty-cycle correction circuit 1, first period of position signal clk_crt is that can be wider than for second period low level period be the high level period.If first period of position signal clk_crt was not wider than for second period when carrying out above-mentioned duty cycle correction operation significantly; Then duty ratio detecting unit 40 can be forbidden duty ratio detection signal dtdet, and duty-cycle correction circuit 1 can stop to change the duty ratio of position signal clk_crt.The structure of duty ratio detecting unit 40 can comprise for example duty ratio accumulator (duty accumulator).
In Fig. 1, counting unit 10 and decoding unit 20 can be represented as duty ratio control unit 50.For example, duty ratio control unit 50 alternately changes (n-1) position the boost logical value of control signal plup < 1:n-1>and (n-1) logical value of potential drop pressure-controlled signal pldn < 1:n-1>in response to duty ratio detection signal dtdet.
Fig. 2 is the sketch map according to the included exemplary decoding unit of the device of Fig. 1 of an embodiment, and Fig. 3 is the sketch map according to the included exemplary duty cycle correction unit of the device of Fig. 1 of an embodiment.In order to make an explanation, variable n representes that the figure place of each n position signal is 5.Then, the highest significant position of 5 count signal cnt < 1:5>is expressed as count signal cnt < 1 >, and its least significant bit is expressed as count signal cnt < 5 >.In the same way; The highest significant position that all is implemented to 4 boost control signal plup < 1:4>and step-down control signal pldn < 1:4>be expressed as respectively boosting control signal plup < 1>and step-down control signal pldn < 1 >, control signal plup < 4>and step-down control signal pldn < 4>and their least significant bit is expressed as respectively boosting.
As shown in Figure 2, decoding unit 20a can be configured to comprise first to the 8th trigger FF1 to FF8 and first to the 5th reverser IV1 to IV5.The first reverser IV1 count signal cnt < 5>that can reverse produces reverse count signal/cnt < 5 >.
The first trigger FF1 can be reset by reset signal rst, and can come breech lock count signal cnt < 1>with the generation control signal plup < 1>that boosts in response to reverse count signal/cnt < 5 >.But the second reverser IV2 count pick up signal 1cnt < 1 >.The second trigger FF2 can be reset by reset signal rst, and the output signal that can come the breech lock second reverser IV2 in response to count signal cnt < 5>is with output buck control signal pldn < 1 >.
The 3rd trigger FF3 can be reset by reset signal rst, and can come breech lock count signal cnt < 2>with the generation control signal plup < 2>that boosts in response to reverse count signal/cnt < 5 >.But the 3rd reverser IV3 count pick up signal cnt < 2 >.
The 4th trigger FF4 can be reset by reset signal rst, and the output signal that can come breech lock the 3rd reverser IV3 in response to count signal cnt < 5>is with output buck control signal pldn < 2 >.
The 5th trigger FF5 can be reset by reset signal rst, and can come breech lock count signal cnt < 3>with the generation control signal plup < 3>that boosts in response to reverse count signal/cnt < 5 >.But the 4th reverser IV4 count pick up signal cnt < 3 >.
The 6th trigger FF6 can be reset by reset signal rst, and the output signal that can come breech lock the 4th reverser IV4 in response to count signal cnt < 5>is with output buck control signal pldn < 3 >.
The 7th trigger FF7 can be reset by reset signal rst, and can come breech lock count signal cnt < 4>with the generation control signal plup < 4>that boosts in response to reverse count signal/cnt < 5 >.But the 5th reverser IV5 count pick up signal cnt < 4 >.
The 8th trigger FF8 can be reset by reset signal rst, and the output signal that can come breech lock the 5th reverser IV5 in response to count signal cnt < 5>is with output buck control signal pldn < 4 >.
According to decoding unit 20a, the logical value of four control signal plup < 1:4>that boost and the logical value of four potential drop pressure-controlled signal pldn < 1:4>alternately change.The change of the logical value of five count signal cnt < 1:5 >, four boost control signal plup < 1:4>and four potential drop pressure-controlled signal pldn < 1:4>can be understood with reference to following table 1.
[table 1]
| Decimal | ?cnt<1:5> | ?plup<1> | ?plup<2> | ?plup<3> | ?plup<4> | ?pldn<1> | ?pldn<2> | ?pldn<3> | ?pldn<4> |
| 0 | 00000 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 1 | 00001 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 2 | 00010 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| 3 | 00011 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
| 4 | 00100 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
| 5 | 00101 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 6 | 00110 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 |
| 7 | 00111 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| 8 | 01000 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| 9 | 01001 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 10 | 01010 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 11 | 01011 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 12 | 01100 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |
| 13 | 01101 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
| 14 | 01110 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 15 | 01111 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| 16 | 10000 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 17 | 10001 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 18 | 10010 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
| 19 | 10011 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| 20 | 10100 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |
| 21 | 10101 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| 22 | 10110 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 23 | 10111 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| 24 | 11000 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 25 | 11001 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| 26 | 11010 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| 27 | 11011 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 28 | 11100 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| 29 | 11101 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| 30 | 11110 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 31 | 11111 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
As shown in table 1, when the logical value of count signal cnt < 5>of least significant bit with count signal cnt < 1:5>of five was 0, the logical value of four control signal plup < 1:4>that boost can increase by 1.When the logical value of count signal cnt < 5>was 1, the logical value of four control signal pldn < 1:4>that boost can reduce 1.That is to say that decoding unit 20a can receive five count signal cnt < 1:5>and produce four boost control signal plup < 1:4>and four potential drop pressure-controlled signal pldn < 1:4 >.Therefore, the logical value of the logical value of four control signal plup < 1:4>that boost and four potential drop pressure-controlled signal pldn < 1:4>alternately changes.Therefore; If the logical value of four control signal plup < 1:4>that boost and the logical value of four potential drop pressure-controlled signal pldn < 1:4>alternately change; Then duty cycle correction unit 30 can prevent that this is with explanation once more hereinafter owing to the faulty operation that increase caused in duty cycle correction operating period fan-out difference.
In Fig. 3, duty cycle correction unit 30a can comprise the first driver 310a and the second driver 320a.The first driver 310a drives input clock signal clk_in with output drive clock signal clk_drv in response to four control signal plup < 1:4>that boost.At this, the first driver 310a can comprise first output node (Nout1), first default drive 312, first boost the part 314a and the first step-down part 316a.The exportable drive clock clk_drv of first output node (Nout1).In addition, first default drive 312 can drive input clock signal clk_in, and can transmit input clock signal clk_in to first output node (Nout1).
The first part 314a that boosts can draw high the voltage level of first output node (Nout1) in response to input clock signal clk_in and four control signal plup < 1:4>that boost.The first part 314a that boosts can comprise four group of the 5th transistor T R5a < 1:4>and four group of the 6th transistor T R6a < 1:4 >.
In Fig. 3, the gate terminal of each the comprised reception input clock signal clk_in among four group of the 5th transistor T R5a < 1:4 >, and can be provided the source terminal of external voltage VDD.Boost among the control signal plup < 1:4>every gate terminal of four of each comprised receptions among four group of the 6th transistor T R6a < 1:4 >; The source terminal of each can be connected in the drain terminal of four group of the 5th transistor T R5a < 1:4 >, and the drain terminal of first output node (Nout1) can be connected to.
The first step-down part 316a can be in response to external voltage VDD and input clock signal clk in and is reduced by the voltage level of first output node (Nout1).The first step-down part 316a can be configured to comprise four group of the 7th transistor T R7a < 1:4>and four group of the 8th transistor T R8a < 1:4 >.
Among four group of the 7th transistor T R7a < 1:4>each can comprise the gate terminal that is provided external voltage VDD, and can be connected to the drain terminal of first output node (Nout1).In addition; The gate terminal of each comprised reception input clock signal clk among four group of the 8th transistor T R8a < 1:4 >; Each the drain terminal of source terminal among four group of the 7th transistor T R7a < 1:4>can be connected to, and the source terminal of ground connection can be connected to.
The second driver 320a drives drive clock signal clk_drv to produce position signal clk_crt in response to four potential drop pressure-controlled signal pldn < 1:4 >.In addition, the second driver 320a can comprise second output node (Nout2), second default drive 322, second boost the part 324a and the second step-down part 326a.The exportable position signal of second output node (Nout2) clk_crt.
The 9th transistor T R9 can comprise the gate terminal that receives drive clock signal clk_drv, and is provided the source terminal of external voltage VDD.The tenth transistor T R10 can comprise the gate terminal that is provided earthed voltage VSS, is connected to the source terminal of the drain terminal of the 9th transistor T R9, and is connected to the drain terminal of second output node (Nout2).The 11 transistor T R11 can comprise the gate terminal that is provided external voltage VDD, and is connected to the drain terminal of second output node (Nout2).The tenth two-transistor TR12 can comprise the gate terminal that receives drive clock signal clk_drv, is connected to the drain terminal of the source terminal of the 11 transistor T R11, and can be connected to the source terminal of ground connection.
In Fig. 3, the gate terminal of each the comprised reception drive clock signal clk_drv among four group of the 13 transistor T R13a < 1:4 >, and can be provided the source terminal of external voltage VDD.Among four group of the 14 transistor T R14a < 1:4>each can comprise the gate terminal that is provided earthed voltage VSS; Be connected to each the source terminal in the drain terminal of four group of the 13 transistor T R13a < 1:4 >, and can be connected to the drain terminal of second output node (Nout2).
The second step-down part 326a can be in response to four potential drop pressure-controlled signal pldn < 1:4>and drive clock signal clk_drv and is reduced by the voltage level of second output node (Nout2).In addition, the second step-down part 326a can be configured to comprise four group of the 15 transistor T R15a < 1:4>and four group of the 16 transistor T R16a < 1:4 >.
In Fig. 3, each among four group of the 15 transistor T R15a < 1:4>can comprise the gate terminal that is provided external voltage VDD, and can be connected to the drain terminal of second output node (Nout2).The gate terminal of each comprised reception drive clock signal clk_drv among four group of the 16 transistor T R16a < 1:4 >; The drain terminal of each source terminal among four group of the 15 transistor T R15a < 1:4>can be connected to, and the source terminal of ground connection can be connected to.
In the duty cycle correction unit of exemplary configurations 30a with above detailed description; If the logical value of four boost control signal plup < 1:4>and four potential drop pressure-controlled signal pldn < 1:4>is as shown in table 1, then the low level period is wider than the high level period in the initial waveform of position signal clk_crt.Then; When the logical value of four boost control signal plup < 1:4>and four potential drop pressure-controlled signal pldn < 1:4>changes in proper order; The driving force of the second step-down part 326a of driving force and the second driver 320a of part 314a of boosting first of the first driver 310a can alternately reduce, and this can cause the low level period of position signal clk_crt is narrowed down.If the low level period of position signal clk_crt obviously is not wider than its high level period, then first of the first driver 310a boost part 314a the driving force of the second step-down part 326a of driving force and the second driver 320a can be locked.
Fig. 4 is the sketch map according to another the exemplary decoding unit in the device that can be used for Fig. 1 of another embodiment, and Fig. 5 is the sketch map according to another the exemplary duty cycle correction unit in the device that can be used for Fig. 1 of another embodiment.In Fig. 4 and Fig. 5, each among the control signal of boosting plup and the step-down control signal pldn can be implemented to four.In addition, the control signal plup that boosts can comprise first control signal plup1 < 1:4>and the second control signal plup2 < 1:4>that boosts that boosts.Similarly, step-down control signal pldn can comprise the first step-down control signal pldn1 < 1:4>and the second step-down control signal pldn2 < 1:4 >.Therefore, count signal cnt < 1:n>can be implemented to six signal, and wherein highest significant position can be expressed as count signal cnt < 1:n>and least significant bit can be expressed as count signal cnt < 6 >.
In Fig. 4, decoding unit 20b can be configured to and comprise decoder DEC, and the 9th to the 24 trigger FF9 is to FF24, and the 6th to the 9th reverser IV6 is to IV9.
Decoder DEC decodable code count signal cnt < 5>and count signal cnt < 6>produce first to the 4th breech lock control signal lat < 1:4 >.First to the 4th breech lock control signal lat < 1:4>can sequentially be enabled according to the variation in the logical value of count signal cnt < 1:6 >.
The 9th trigger FF9 can be reset by reset signal rst, and can come breech lock count signal cnt < 1>to produce the first control signal plup1 < 1>that boosts in response to the first breech lock control signal lat < 1 >.The tenth trigger FF10 can be reset by reset signal rst, and produces the first control signal plup1 < 1>that boosts in response to the 3rd breech lock control signal lat < 3 >.But the 6th reverser IV6 count pick up signal cnt < 1 >.The 11 trigger FF11 can be reset by reset signal rst, and the output signal that can come breech lock the 6th reverser IV6 in response to the second breech lock control signal lat < 2>is to export the second step-down control signal pldn2 < 1 >.The 12 trigger FF12 can be reset by reset signal rst, and can come the breech lock second step-down control signal pldn2 < 1>to export the second control signal plup2 < 1>that boosts in response to the 4th breech lock control signal lat < 4 >.
The 13 trigger FF13 can be reset by reset signal rst, and can come breech lock count signal cnt < 2>to produce the first control signal plup1 < 2>that boosts in response to the first breech lock control signal lat < 1 >.The 14 trigger FF14 can be reset by reset signal rst, and produces the first control signal plup1 < 2>that boosts in response to the 3rd breech lock control signal lat < 3 >.But the 7th reverser IV7 count pick up signal cnt < 2 >.The 15 trigger FF15 can be reset by reset signal rst, and the output signal that can come breech lock the 7th reverser IV7 in response to the second breech lock control signal lat < 2>is to export the second step-down control signal pldn2 < 2 >.The 16 trigger FF16 can be reset by reset signal rst, and can come the breech lock second step-down control signal pldn2 < 2>to export the second control signal plup2 < 2>that boosts in response to the 4th breech lock control signal lat < 4 >.
The 17 trigger FF17 can be reset by reset signal rst, and can come breech lock count signal cnt < 3>to produce the first control signal plup1 < 3>that boosts in response to the first breech lock control signal lat < 1 >.The 18 trigger FF18 can be reset by reset signal rst, and produces the first control signal plup1 < 3>that boosts in response to the 3rd breech lock control signal lat < 3 >.But the 8th reverser IV8 count pick up signal cnt < 3 >.The 19 trigger FF19 can be reset by reset signal rst, and the output signal that can come breech lock the 8th reverser IV8 in response to the second breech lock control signal lat < 2>is to export the second step-down control signal pldn2 < 3 >.The 20 trigger FF20 can be reset by reset signal rst, and can come the breech lock second step-down control signal pldn2 < 3>to export the second control signal plup2 < 3>that boosts in response to the 4th breech lock control signal lat < 4 >.
The 21 trigger FF21 can be reset by reset signal rst, and can come breech lock count signal cnt < 4>to produce the first control signal plup1 < 4>that boosts in response to the first breech lock control signal lat < 1 >.The 22 trigger FF22 can be reset by reset signal rst, and produces the first control signal plup1 < 4>that boosts in response to the 3rd breech lock control signal lat < 3 >.But the 9th reverser IV9 count pick up signal cnt < 4 >.The 23 trigger FF23 can be reset by reset signal rst, and the output signal that can come breech lock the 9th reverser IV9 in response to the second breech lock control signal lat < 2>is to export the second step-down control signal pldn2 < 4 >.The 24 trigger FF24 can be reset by reset signal rst, and can come the breech lock second step-down control signal pldn2 < 4>to export the second control signal plup2 < 4>that boosts in response to the 4th breech lock control signal lat < 4 >.
Exemplary configurations according to decoding unit 20b; Selecting its logical value to boost control signal plup1 < 1:4 >, the first step-down control signal pldn1 < 1:4 >, second when boosting the signal that changes in the middle of the control signal plup2 < 1:4>and the second step-down control signal pldn2 < 1:4 >, can use among six count signal cnt < 1:6>two than low level first.First boost control signal plup1 < 1:4>and the first step-down control signal pldn1 < 1:4>can be implemented to and make that their logical value is identical at initial waveform, and can increase by 1.In addition, second boost control signal plup2 < 1:4>and the second step-down control signal pldn2 < 1:4>can be implemented to and make that their logical value can be identical at initial waveform, and can reduce 1.Therefore; When two among six count signal cnt < 1:6>change than the logical values of low level, change their logical value with first boost the order that control signal plup1 < 1:4 >, the second step-down control signal pldn2 < 1:4 >, the first step-down control signal pldn1 < 1:4>and second boost control signal plup2 < 1:4 >.
In Fig. 5, duty cycle correction unit 30b can be configured to be substantially similar to the configuration of duty cycle correction unit 30a shown in Figure 3.But; Difference among duty cycle correction unit 30b and the duty cycle correction unit 30a can be; The boost driving force of part 314b of first of the first driver 310b can change in response to the first control signal plup1 < 1:4>that boosts; The driving force of the first step-down part 316b can change in response to the first step-down control signal pldn1 < 1:4 >; The boost driving force of part 324b of second of the second driver 320b can change in response to the second control signal plup2 < 1:4>that boosts, and the driving force of the second step-down part 326b can change in response to the second step-down control signal pldn2 < 1:4 >.
The first part 314b that boosts can comprise four group of the 5th transistor T R5b < 1:4>and four group of the 6th transistor T R6b < 1:4 >.The gate terminal of each comprised reception input clock signal clk_in among four group of the 5th transistor T R5b < 1:4>and can be provided the source terminal of external voltage VDD.Four first of each comprised receptions among four group of the 6th transistor T R6b < 1:4>gate terminal of every among the control signal plup1 < 1:4>that boosts; The source terminal of each drain terminal among four group of the 5th transistor T R5b < 1:4>can be connected to, and the drain terminal of first output node (Nout1) can be connected to.
The first step-down part 316b can be configured to comprise four group of the 7th transistor T R7b < 1:4>and four group of the 8th transistor T R8b < 1:4 >.Every gate terminal among four first step-down control signals of each the comprised reception pldn1 < 1:4>among four group of the 7th transistor T R7b < 1:4 >, and can be connected to the drain terminal of first output node (Nout1).The gate terminal of each comprised reception input clock signal clk_in among four group of the 8th transistor T R8b < 1:4>can be connected to the drain terminal of each source terminal among four group of the 7th transistor T R7b < 1:4 >, and can be connected to the source terminal of ground connection.
The second part 324b that boosts can be configured to comprise four group of the 13 transistor T R13b < 1:4 >, and four group of the 14 transistor T R14b < 1:4 >.The gate terminal of each comprised reception drive clock signal clk_drv among four group of the 13 transistor T R13b < 1:4 >, and can be provided the source terminal of external voltage VDD.Boost among the control signal plup2 < 1:4>every gate terminal of four second of each comprised receptions among four group of the 14 transistor T R14b < 1:4 >; The source terminal of the drain terminal of each among four group of the 13 transistor T R13b < 1:4>can be connected to, and the drain terminal of second output node (Nout2) can be connected to.
The second step-down part 326b can be configured to comprise four group of the 15 transistor T R15b < 1:4 >, and four group of the 16 transistor T R16b < 1:4 >.Every the gate terminal of four second step-down control signals of each comprised reception pldn2 < 1:4>among four group of the 15 transistor T R15b < 1:4 >, and can be connected to the source terminal of second output node (Nout2).The gate terminal of each comprised reception drive clock signal clk_drv among four group of the 16 transistor T R16b < 1:4>can be connected to the drain terminal of each source terminal of four group of the 15 transistor T R15b < 1:4 >, and can be connected to the source terminal of ground connection.
When first the boost control signal plup < 1:4 >, the second step-down control signal pldn2 < 1:4 >, the first step-down control signal pldn1 < 1:4>and second boosts ground of logical value of control signal plup2 < 1:4>when alternately changing; With first of first driver 310 boost part 314, second driver 320 the second step-down part 326, first driver 310 the first step-down part 316 and second driver 320 second boost part 324 order, its driving force changes.Therefore, duty cycle correction unit 30b can be little by little narrows down low level period of position signal clk_crt, proofreaies and correct duty ratio thus.Therefore, compared to Fig. 2 and configuration shown in Figure 3, can carry out accurate duty cycle correction operation.
As stated; In the method for duty-cycle correction circuit and correction duty ratio; When the driving force of driver alternately changes, can use multistage driver to proofread and correct the duty ratio of input clock signal, prevent thus owing to the fan-out difference between the driver increases the misoperation that causes.Thus, driver is distinguished each other than low level through when the count signal that its logical value is increased by 1 is decoded, using, the operational stability of duty-cycle correction circuit can be improved, and can stably carry out duty cycle correction.
Although more than described specific embodiment, it should be understood that said embodiment is an example.Thereby apparatus and method described herein can not only limit to described embodiment.On the contrary, can only and combine above-mentioned specification and accompanying drawing to limit apparatus and method described herein according to claim.
Claims (23)
1. duty-cycle correction circuit comprises:
The duty ratio control unit, it is configured to alternately change the boost logical value of control signal and multidigit step-down control signal of multidigit in response to the duty ratio detection signal;
The duty cycle correction unit, it is configured to boost driving force that control signal and said multidigit step-down control signal adjust first driver and second driver with the output calibration clock signal in response to said multidigit; And
The duty ratio detecting unit; Its duty ratio that is configured to detect said position is to produce said duty ratio detection signal; And be configured to be wider than its second level keeps said duty ratio detection signal during the period enabled, and be not wider than said second level and forbid said duty ratio detection signal during the period when the said first level period when the first level period of said position signal.
2. duty-cycle correction circuit as claimed in claim 1, wherein said duty ratio control unit comprises:
Counting unit, it is configured to produce the multidigit count signal in response to said duty ratio detection signal; And
Decoding unit, its said multidigit count signal that is configured to decode is to produce said multidigit boost control signal and said multidigit step-down control signal.
3. duty-cycle correction circuit as claimed in claim 2; Wherein said counting unit is configured to when said duty ratio detection signal is enabled to increase with predetermined unit the logical value of said multidigit count signal, and when said duty ratio detection signal is under an embargo, locks the logical value of said multidigit count signal.
4. duty-cycle correction circuit as claimed in claim 2, wherein said decoding unit are configured to logical value according to the least significant bit of said multidigit count signal and change the boost logical value of one of control signal and said multidigit step-down control signal of said multidigit.
5. duty-cycle correction circuit as claimed in claim 2, wherein said decoding unit are configured to logical value according to the first anteposition of the least significant bit of said multidigit count signal and change the boost logical value of one of control signal and said multidigit step-down control signal of said multidigit.
6. like the duty-cycle correction circuit of claim 4 or 5; In wherein said first driver and said second driver each comprises boost part and step-down part; The driving force of the part of boosting of said first driver is boosted control signal in response to said multidigit and is changed, and the driving force of the step-down part of said second driver changes in response to said multidigit step-down control signal.
7. duty-cycle correction circuit as claimed in claim 6, wherein said first driver comprises:
Output node;
Default drive, it is configured to drive input clock signal and transmits driven input clock signal to said output node;
The part of boosting, it is configured to boost control signal in response to said input clock signal and said multidigit and draws high the voltage level of said output node; And
The step-down part, it is configured to reduce in response to said input clock signal the voltage level of said output node.
8. duty-cycle correction circuit as claimed in claim 6, wherein said second driver comprises:
Output node, it is configured to export said position signal;
Default drive, it is configured to drive the output signal of said first driver and transmits driven output signal to said output node;
The part of boosting, it is configured to draw high in response to the output signal of said first driver voltage level of said output node; And
The step-down part, it is configured in response to the output signal of said first driver and said multidigit step-down control signal and reduces the voltage level of said output node.
9. duty-cycle correction circuit comprises:
Counting unit; It is configured to produce the multidigit count signal that logical value increases with predetermined unit; And be configured to when the duty ratio detection signal is enabled, increase the logical value of said multidigit count signal, and when said duty ratio detection signal is under an embargo, lock the logical value of said multidigit count signal;
Decoding unit, it is configured to logical value according to the least significant bit of said multidigit count signal and changes the boost logical value of one of control signal and multidigit step-down control signal of multidigit; And
The duty cycle correction unit, it is configured to boost driving force that control signal and said multidigit step-down control signal come alternately to adjust first driver and second driver with the output calibration clock signal in response to said multidigit.
10. duty-cycle correction circuit as claimed in claim 9; Wherein said decoding unit is configured to when the logical value of the least significant bit of said multidigit count signal is first logical value, to change the boost logical value of control signal of said multidigit, and when the logical value of the least significant bit of said multidigit count signal is second logical value, changes the logical value of said multidigit step-down control signal.
11. like the duty-cycle correction circuit of claim 10, wherein said first driver comprises:
Output node;
Default drive, it is configured to drive input clock signal and transmits driven input clock signal to said output node;
First part of boosting, it is configured to boost control signal in response to said input clock signal and said multidigit and draws high the voltage level of said output node; And
The first step-down part, it is configured to reduce in response to said input clock signal the voltage level of said output node.
12. like the duty-cycle correction circuit of claim 10, wherein said second driver comprises:
Output node, it is configured to export said position signal;
Default drive, it is configured to drive the output signal of said first driver and transmits driven output signal to said output node;
Second part of boosting, it is configured to draw high in response to the output signal of said first driver voltage level of said output node; And
The second step-down part, it is configured in response to the output signal of said first driver and said multidigit step-down control signal and reduces the voltage level of said output node.
13. like the duty-cycle correction circuit of claim 2 or 9, the wherein said control signal of boosting comprises first control signal and second control signal of boosting of boosting, and said step-down control signal comprises the first step-down control signal and the second step-down control signal.
14. like the duty-cycle correction circuit of claim 13, wherein said decoding unit is configured to alternately change said first boost control signal, said second step-down control signal, said first step-down control signal and said second the boost logical value of control signal than the logical value of low level with predetermined unit according to two of said multidigit count signal.
15. duty-cycle correction circuit like claim 14; First driver of wherein said duty cycle correction unit comprises that first boosts partly and the first step-down part, and second driver of said duty cycle correction unit comprises that second boosts partly and the second step-down part.
16. like the duty-cycle correction circuit of claim 15, wherein said first the boost driving force of part and said second step-down part of part, said first step-down part, said second of boosting is boosted control signal and the said second step-down control signal and is changed in response to said first the boost control signal, the said first step-down control signal, said second.
17. like the duty-cycle correction circuit of claim 16, wherein said first driver comprises:
Output node;
Default drive, it is configured to drive input clock signal and transmits driven input clock signal to said output node;
Said first part of boosting, it is configured to draw high in response to said input clock signal and said first boosts control signal the voltage level of said output node; And
The said first step-down part, it is configured in response to said input clock signal and the said first step-down control signal and reduces the voltage level of said output node.
18. like the duty-cycle correction circuit of claim 16, wherein said second driver comprises:
Output node, it is configured to export said position signal;
Default drive, it is configured to drive the output signal of said first driver and transmits driven output signal to said output node;
Said second part of boosting, it is configured to draw high in response to the output signal of said first driver and said second boosts control signal the voltage level of said output node; And
The said second step-down part, it is configured in response to the output signal of said first driver and the said second step-down control signal and reduces the voltage level of said output node.
19. duty ratio correction method; It proofreaies and correct the duty ratio in the duty-cycle correction circuit; Said duty-cycle correction circuit comprises first driver and second driver that is connected in series and the duty ratio of proofreading and correct input clock signal to produce the position signal, and said method comprises:
The duty ratio that detects said position signal is to produce the duty ratio detection signal;
The driving force that changes said first driver in response to said duty ratio detection signal is to proofread and correct the duty ratio of said position signal;
The duty ratio that detects said position signal is to produce said duty ratio detection signal; And
The driving force that changes said second driver in response to said duty ratio detection signal to be proofreading and correct the duty ratio of said position signal,
Wherein be wider than its second level during the period when the first level period of said position signal; The step of the said duty ratio detection signal of said generation keeps the enabled of said duty ratio detection signal; And be not wider than said second level during period when the said first level period, the step of the said duty ratio detection signal of said generation is forbidden said duty ratio detection signal.
20. like the duty ratio correction method of claim 19, the driving force of said first driver of wherein said change comprises with the step of the duty ratio of proofreading and correct said position signal:
When detecting said duty ratio detection signal and be enabled, carry out counting operation to increase the logical value of multidigit count signal;
Change the boost logical value of control signal of multidigit according to the logical value of the least significant bit of said multidigit count signal; And
In response to said multidigit boost control signal and change said first driver boost the part driving force.
21. like the duty ratio correction method of claim 19, the driving force of said second driver of wherein said change comprises with the step of the duty ratio of proofreading and correct said position signal:
When detecting said duty ratio detection signal and be enabled, carry out counting operation to increase the logical value of multidigit count signal;
The logical value of least significant bit of confirming said multidigit count signal is to change the logical value of multidigit step-down control signal according to determined logical value; And
Change the driving force of the step-down part of said second driver in response to said multidigit step-down control signal.
22. like the duty ratio correction method of claim 19, the driving force of said first driver of wherein said change comprises with the step of the duty ratio of proofreading and correct said position signal:
When detecting said duty ratio detection signal and be enabled, carry out counting operation to increase the logical value of multidigit count signal;
Change the logical value of multidigit step-down control signal according to two logical values of said multidigit count signal than low level; And
Change the driving force of the step-down part of said first driver in response to said multidigit step-down control signal.
23. like the duty ratio correction method of claim 19, the driving force of said second driver of wherein said change comprises with the step of the duty ratio of proofreading and correct said position signal:
When detecting said duty ratio detection signal and be enabled, carry out counting operation to increase the logical value of multidigit count signal;
Change the boost logical value of control signal of multidigit according to two logical values of said multidigit count signal than low level; And
In response to said multidigit boost control signal and change said second driver boost the part driving force.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080051064A KR100945797B1 (en) | 2008-05-30 | 2008-05-30 | Duty Cycle Correcting Circuit and Method |
| KR1020080051064 | 2008-05-30 | ||
| KR10-2008-0051064 | 2008-05-30 |
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| Publication Number | Publication Date |
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| CN101594129A CN101594129A (en) | 2009-12-02 |
| CN101594129B true CN101594129B (en) | 2012-12-12 |
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| CN2009101186149A Expired - Fee Related CN101594129B (en) | 2008-05-30 | 2009-02-26 | Duty cycle correcting circuit and method of correcting duty cycle |
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| US (1) | US8228104B2 (en) |
| JP (1) | JP2009290859A (en) |
| KR (1) | KR100945797B1 (en) |
| CN (1) | CN101594129B (en) |
| TW (1) | TW200949853A (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2009290859A (en) | 2009-12-10 |
| KR20090124706A (en) | 2009-12-03 |
| US8228104B2 (en) | 2012-07-24 |
| CN101594129A (en) | 2009-12-02 |
| KR100945797B1 (en) | 2010-03-08 |
| US20090295446A1 (en) | 2009-12-03 |
| TW200949853A (en) | 2009-12-01 |
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