CN101656234B - 先进四方扁平无引脚封装结构及其制造方法 - Google Patents

先进四方扁平无引脚封装结构及其制造方法 Download PDF

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CN101656234B
CN101656234B CN2009101522811A CN200910152281A CN101656234B CN 101656234 B CN101656234 B CN 101656234B CN 2009101522811 A CN2009101522811 A CN 2009101522811A CN 200910152281 A CN200910152281 A CN 200910152281A CN 101656234 B CN101656234 B CN 101656234B
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CN101656234A (zh
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林俊宏
张简宝徽
胡平正
郑维伦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

本发明公开了一种先进四方扁平无引脚封装结构及其制造方法。此先进四方扁平无引脚封装结构包括承载器、芯片与封装胶体。承载器包括芯片座与多个引脚。芯片座具有中央部分、周边部分与多个连接部分。周边部分配置于中央部分周围。连接部分连接中央部分与周边部分。周边部分、连接部分与中央部分定义出至少两个中空区域。引脚配置于芯片座周围。芯片位于芯片座的中央部分，且经由多个导线而电性连接至引脚。封装胶体包覆芯片、导线、引脚与部分承载器。

Description

先进四方扁平无引脚封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，且特别是涉及一种先进四方扁平无引脚(advanced quad flat non-leaded，a-QFN)封装结构及其制造方法。
背景技术
根据导线架(leadframe)的引脚(lead)的形状，四方扁平封装(quad flatpackage，QFP)可以分为I型(QFI)、J型(QFJ)与无引脚型(QFN)封装。由于QFN封装结构具有相对较短的信号线(signal trace)以及较快的信号传输速率，因此成为一种普遍的具有低脚数(pin count)封装结构，且适用于具有高频率(例如，射频频宽(radio frequency bandwidth))传输的芯片封装。
一般来说，在QFN封装结构的工艺中，将多个芯片配置于导线架上，且通过多个焊线(bonding wire)而电性连接至导线架。然后，形成封装胶体(molding compound)，以包覆导线架、芯片与焊线。最后，通过切割工艺(singulation process)来形成多个QFN封装结构。
发明内容
本发明提供一种先进四方扁平无引脚封装结构及其制造方法，其减少了芯片座(die pad)暴露面积，以降低剥离(delamination)的风险。
为了达成上述目的，本发明提出一种先进四方扁平无引脚封装结构。此先进四方扁平无引脚封装结构包括承载器(carrier)、芯片与封装胶体。承载器具有上表面与相对于上表面的下表面。承载器包括芯片座与多个引脚。芯片座具有中央部分、周边部分与多个连接部分。周边部分配置于中央部分周围。连接部分连接中央部分与周边部分。连接部分彼此分离。周边部分、连接部分与中央部分定义出至少两个中空区域(hollow region)。引脚配置于芯片座周围，其中每一个引脚包括配置于上表面上的内引脚与配置于下表面上的外引脚。芯片配置于承载器的上表面上，且位于芯片座的中央部分中，其中芯片经由多个导线(wire)而电性连接至内引脚。封装胶体包覆芯片、导线、内引脚与部分承载器。
根据本发明的实施例，芯片座的周边部分作为接地环(ground ring)之用，其中芯片座的周边部分经由导线而电性连接至芯片。
根据本发明的实施例，承载器还包括至少一个电源环(power ring)，其中电源环配置于引脚与芯片座的周边部分之间，并经由导线而电性连接至芯片，且电源环与接地环电性绝缘。
根据本发明的实施例，先进四方扁平无引脚封装结构还包括粘着层，其配置于芯片与芯片座的中央部分之间。
根据本发明的实施例，芯片座的中央部分具有多边形(polygonal)的形状。
根据本发明的实施例，周边部分经由连接部分而与中央部分的至少一侧连接。
根据本发明的实施例，周边部分经由连接部分而与中央部分的至少一个角落连接。
根据本发明的实施例，引脚的材料包括金(gold)或钯(palladium)。
根据本发明的实施例，任何两个相邻的引脚之间的距离大于或等于400微米。
根据本发明的实施例，中央部分的底部表面与周边部分的底部表面共平面(coplanar)，而中央部分的上表面与周边部分的上表面不共平面。
根据本发明的实施例，芯片的边缘与中央部分的边缘之间的距离大于或等于300微米。
本发明另提出一种先进四方扁平无引脚封装结构的制造方法，其包括以下步骤。首先，提供承载器，其中第一图案化金属层形成于承载器的上表面上，且第二图案化金属层形成于承载器的下表面上。承载器包括至少一个容置凹穴(accommodating cavity)与多个第一开口。然后，提供芯片。芯片配置于容置凹穴的中央部分上，且经由多个导线而电性连接至承载器的第一图案化金属层。接着，形成封装胶体，以包覆芯片、导线、承载器的第一图案化金属层，并填满容置凹穴与第一开口。而后，以第二图案化金属层为掩模，对承载器的下表面进行蚀刻工艺，以蚀刻穿过承载器而暴露出填入第一开口中的封装胶体，且同时形成多个第二开口与多个第三开口。
根据本发明的实施例，在蚀刻工艺之后，承载器通过第二开口而定义出多个引脚与芯片座。
根据本发明的实施例，芯片座通过第三开口同时定义出中央部分、周边部分与多个连接部分。
根据本发明的实施例，在提供芯片之前，还包括在容置凹穴的中央部分上形成粘着层。
综上所述，根据本发明，承载器的芯片座中具有多个中空区域，且中空区域暴露出封装胶体。因此，封装胶体与芯片座的接触面积可以减少，且由于不同材料之间的不均匀应力所导致的封装胶体与芯片座之间的剥离问题可以减轻。另一方面，位于芯片座的中央部分上的芯片可以被封装胶体包覆且保护。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A为根据本发明的实施例所绘示的先进四方扁平无引脚封装结构的底部示意图。
图1B为沿图1A中的I-I’剖面所绘示的剖面示意图。
图1C为沿图1A中的II-II’剖面所绘示的剖面示意图。
图2为根据本发明的另一实施例所绘示的先进四方扁平无引脚封装结构的底部示意图。
图3A至图3I为根据本发明的实施例所绘示的先进四方扁平无引脚封装结构的制造流程剖面图，其中图3H的次图(a)为沿图1A中的I-I’剖面所绘示的剖面示意图，而图3H的次图(b)为沿图1A中的II-II’剖面所绘示的剖面示意图。
附图标记说明
100、100a：先进四方扁平无引脚封装结构
200：承载器
210a、222a、224a、226a：上表面
210b、212b：下表面
214a、218a：第一图案化光致抗蚀剂层
214b、218a：第二图案化光致抗蚀剂层
216a：第一金属层
216b：第二金属层
220：芯片座
220a：容置凹穴
222：中央部分
224：周边部分
224b、222b、226b：底部表面
226：连接部分
230：引脚
232：内引脚
234：外引脚
240：电源环
300：芯片
400：导线
500：封装胶体
600：粘着层
d：距离
S：中空区域
SI：第一开口
S2：第二开口
S3：第三开口
具体实施方式
图1A为根据本发明的实施例所绘示的先进四方扁平无引脚封装结构的底部示意图。图1B为沿图1A中的I-I’剖面所绘示的剖面示意图。图1C为沿图1A中的II-II’剖面所绘示的剖面示意图。请同时参照图1A、图1B与图1C，在本实施例中，先进四方扁平无引脚(a-QFN)封装结构100包括承载器200、芯片300与封装胶体500。
在本实施例中，承载器200例如为导线架。详细地说，承载器200具有上表面210a与相对于上表面210a的下表面210b。承载器200包括芯片座220与多个引脚230，其中芯片座220具有中央部分222、周边部分224与多个连接部分226。在图1A中，绘示出四个连接部分226。然而，芯片座220可以包括一个或多个连接部分226，且连接部分226的数目在此并不限定。周边部分224围绕中央部分222。连接部分226连接中央部分222与周边部分224。由于连接部分226彼此分离，因此周边部分224、连接部分226与中央部分222定义出了四个中空区域S。中空区域S的数目在此并不限定，但通过承载器200中连接部分226的数目来决定。
详细地说，在本实施例中，芯片座220的中央部分222具有矩形的形状。中央部分222的底部表面222b与周边部分224的底部表面224b共平面，而中央部分222的上表面222a与周边部分224的上表面224a不共平面。如图1C所示，周边部分224的上表面224a高于中央部分222的上表面222a。然而，芯片座220的中央部分222可以是多边形的形状。连接部分226配置于中央部分222的一侧或角落。特别是，在本实施例中，连接部分226连接中央部分222的四侧与周边部分224。值得注意的事，连接部分226的位置、排列或数量可以依据封胶工艺(molding process)的需求而调整。在本发明的另一实施例中，芯片座220仅具有两个连接部分226，且周边部分224经由连接部分226而连接至中央部分222的两个角落，如图2所示。
请参照图1A与图1B，引脚230配置于芯片座220周围，其中每一个引脚230包括内引脚232与外引脚234。举例来说，引脚230可以沿着芯片座220的两侧来配置，或配置于芯片座220的周围。引脚230的配置方式例如是阵列(array)、多行或多列，或配置成环状。引脚230的配置方式可以依据客户需求或产品需求而客制化(customized)。引脚230的材料例如为金或钯。
此外，任何两个相邻的引脚230之间的距离大于或等于400微米。
芯片300配置于芯片座220的中央部分222，且位于承载器200的上表面210a上。芯片300经由多个导线400而电性连接至内引脚232与周边部分224。此外，芯片300的边缘与中央部分222的边缘之间的距离d大于或等于300微米。
封装胶体500包覆芯片300、导线400、内引脚232、一部分的芯片座220。换句话说，外引脚234与芯片座220的底部表面未被封装胶体500覆盖。此外，芯片座220的中空区域S与引脚230之间的间隙暴露出封装胶体500。由于芯片座220的中空区域S，因此封装胶体500与芯片座220之间的剥离现象可以减少。封装胶体500的材料例如为环氧树脂(epoxy resin)或其他可应用的聚合物材料(polymer material)。
此外，在本实施例中，在a-QFN封装结构100中，芯片座220的周边部分224例如可以作为接地环之用。另外，承载器200还可以包括至少一个电源环240。电源环240配置于引脚230与芯片座220的周边部分224之间，且经由导线400而电性连接至芯片300。电源环240与接地环224电性绝缘。
再者，在本实施例中，a-QFN封装结构100还包括粘着层600。粘着层600配置于芯片300与芯片座220的中央部分222之间，以将芯片300固定于中央部分222。
简言之，在本发明的实施例中，a-QFN封装结构100/100a具有至少两个位于芯片座220的周边部分224与中央部分222之间的中空区域S，且中空区域S暴露出封装胶体500。因此，可以减少由于金属氧化或不均匀应力所导致的封装胶体500与芯片座220之间的剥离问题。
以下将以图3A至图3I来说明本发明的a-QFN封装结构100的制作流程。
图3A至图3I为根据本发明的实施例所绘示的先进四方扁平无引脚封装结构的制造流程剖面图，其中图3H的次图(a)为沿图1A中的I-I’剖面所绘示的剖面示意图，而图3H的次图(b)为沿图1A中的II-II’剖面所绘示的剖面示意图。为了方便说明，在本实施例中将省略电源环。
首先，请参照图3A，提供具有上表面210a与下表面210b的基底210。基底210的材料例如为铜、铜合金或其他可应用的金属材料。然后，在基底210的上表面210a上形成第一图案化光致抗蚀剂层214a，且于基底210的下表面212b上形成第二图案化光致抗蚀剂层214b。
然后，请参照图3B，在暴露出来的基底210的上表面210a上形成第一金属层216a，且在暴露出来的基底210的下表面210b上形成第二金属层216b。在本实施例中，形成第一金属层216a与第二金属层216b的方法例如为电镀(plating)。
接着，请参照图3C，移除第一图案化光致抗蚀剂层214a，以在基底210的上表面210a上形成第一图案化金属层218a。
而后，请参照图3D，以第一图案化金属层218a作为蚀刻掩模，进行蚀刻工艺来移除一部分的基底210，以形成至少一个容置凹穴220a与多个第一开口S1。然后，移除第二图案化光致抗蚀剂层214b，以在基底210的下表面210b上形成第二图案化金属层218b。通过第一开口S1而彼此分离的第一图案化金属层218a将在后续步骤中形成内引脚232。第一图案化金属层218a的图案与第二图案化金属层218b的图案不相同或不对称。在此阶段，约略形成了承载器200。
继之，请参照图3E，将芯片300提供至每一个容置凹穴220a的中央部分222，且在芯片300与容置凹穴220a的中央部分222之间形成粘着层600。配置于芯片300与容置凹穴220a的中央部分222之间的粘着层600有助于将芯片300固定于中央部分222。
随后，请参照图3F，经由导线400将芯片300电性连接至即将形成的内引脚232。
然后，请参照3G，形成封装胶体500，以包覆芯片300、导线400、即将形成的内引脚232，且填入容置凹穴220a与第一开口S1。
之后，请参照图3H(a)与图3H(b)，以第二图案化金属层218b作为掩模，对暴露出来的承载器200的下表面210b(如图3G所示)进行蚀刻工艺，以蚀刻穿过暴露的基底210(例如，导线架)。因此，第一开口S1中的封装胶体500被暴露出来，且同时形成了多个第二开口S2与多个第三开口S3。
特别地，由于第二开口S2的形成，基底210被蚀刻穿，且定义出了内引脚232与外引脚234。内引脚232通过第一开口S1而彼此物理分离与电性分离。外引脚234通过第二开口S2而彼此物理分离与电性分离。第三开口S3定义容置凹穴220a中的基底210，以形成具有中央部分222、围绕中央部分222的周边部分224与多个连接部分226的芯片座220。连接部分226通过第三开口S3而彼此分离。
详细地说，芯片座220的中央部分222被周边部分224围绕，且连接部分226连接中央部分222与周边部分224。如图1C所示，中央部分222的底部表面222b与周边部分224的底部表面224b以及连接部分226的底部表面226b共平面，且中央部分222的上表面222a与连接部分226的上表面226a共平面，但是不与周边部分224的上表面224a共平面。芯片300的边缘与中央部分222的边缘之间的距离大于或等于300微米。
之后，请参照图3I，通过锯开工艺(sawing process)来进行切割工艺。切割工艺还可以包括冲压工艺(punch process)。切割的目的在于完全切断承载器200与封装胶体500，以得到多个a-QFN封装结构100。在图3I中，仅绘示出两个a-QFN封装结构100。
简言之，通过对基底的下表面进行蚀刻工艺来同时形成第二开口与第三开口，而封装胶体经由第二开口与第三开口而被暴露出来。此外，由于开口的形成，导线架(芯片座)与封装胶体之间的接触面积可以减小，因此可以避免剥离的问题，以及增进工艺品质与产品良率。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定为准。

Claims (14)

1.一种先进四方扁平无引脚封装结构，包括：
承载器，具有上表面与下表面，其中该承载器包括：
芯片座，具有中央部分、周边部分与多个连接部分，其中该周边部分环绕该中央部分，而多个连接部分连接该中央部分与该周边部分，多个连接部分彼此分离，且该中央部分、该周边部分与多个连接部分定义出至少两个中空区域；以及
多个引脚，配置于该芯片座周围，其中每一引脚包括配置于该上表面上的内引脚与配置于该下表面上的外引脚；
芯片，配置于该承载器的该上表面上，且位于该芯片座的该中央部分，其中该芯片经由多个导线而电性连接至多个内引脚；以及
封装胶体，包覆该芯片、多个导线、多个内引脚与部分该承载器，
其中该中央部分的底部表面与该周边部分的底部表面共平面，而该中央部分的上表面与该周边部分的上表面不共平面。
2.如权利要求1所述的先进四方扁平无引脚封装结构，其中该芯片座的该周边部分作为接地环，其中该芯片座的该周边部分经由多个导线而电性连接至该芯片。
3.如权利要求2所述的先进四方扁平无引脚封装结构，其中该承载器还包括至少一电源环，其中所述电源环配置于多个引脚与该芯片座的该周边部分之间，且经由多个导线而电性连接至该芯片，且该至少一电源环与该接地环电性绝缘。
4.如权利要求1所述的先进四方扁平无引脚封装结构，还包括粘着层，配置于该芯片与该芯片座的该中央部分之间。
5.如权利要求1所述的先进四方扁平无引脚封装结构，其中该芯片座的该中央部分具有多边形的形状。
6.如权利要求5所述的先进四方扁平无引脚封装结构，其中该周边部分经由多个连接部分而连接至该中央部分的至少一侧。
7.如权利要求5所述的先进四方扁平无引脚封装结构，其中该周边部分经由多个连接部分而连接至该中央部分的至少一角落。
8.如权利要求1所述的先进四方扁平无引脚封装结构，其中多个引脚的材料包括金或钯。
9.如权利要求1所述的先进四方扁平无引脚封装结构，其中任何两个相邻的多个引脚之间的距离大于或等于400微米。
10.如权利要求1所述的先进四方扁平无引脚封装结构，其中该芯片的边缘与该中央部分的边缘之间的距离大于或等于300微米。
11.一种先进四方扁平无引脚封装结构的制造方法，包括：
提供承载器，第一图案化金属层形成于该承载器的上表面上，且第二图案化金属层形成于该承载器的下表面上，其中该承载器包括至少一容置凹穴与多个第一开口；
提供芯片，并将该芯片配置于该容置凹穴的中央部分，且经由多个导线而电性连接至该承载器的该第一图案化金属层；
形成封装胶体，以包覆该芯片、多个导线、该承载器的该第一图案化金属层，且填入该容置凹穴与多个第一开口；以及
以该第二图案化金属为掩模，对该承载器的该下表面进行蚀刻工艺，以蚀刻穿过该承载器而暴露出填入多个第一开口中的该封装胶体，且同时形成多个第二开口与多个第三开口。
12.如权利要求11所述的先进四方扁平无引脚封装结构的制造方法，其中在进行该蚀刻工艺之后，该承载器通过多个第二开口而被定义出多个引脚与芯片座。
13.如权利要求12所述的先进四方扁平无引脚封装结构的制造方法，其中该芯片座通过多个第三开口而同时被定义出该中央部分、周边部分与多个连接部分。
14.如权利要求11所述的先进四方扁平无引脚封装结构的制造方法，其中在提供该芯片之前，还包括在该容置凹穴的该中央部分上形成粘着层。
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Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
KR100935854B1 (ko) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
KR100950511B1 (ko) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
JP2010238693A (ja) * 2009-03-30 2010-10-21 Toppan Printing Co Ltd 半導体素子用基板の製造方法および半導体装置
US8575742B1 (en) * 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110115063A1 (en) * 2009-11-18 2011-05-19 Entropic Communications, Inc. Integrated Circuit Packaging with Split Paddle
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
CN102194775B (zh) * 2010-03-03 2013-04-17 南茂科技股份有限公司 四边扁平无接脚封装结构
US8241956B2 (en) * 2010-03-08 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level multi-row etched lead package
TWI479580B (zh) * 2010-03-12 2015-04-01 矽品精密工業股份有限公司 四方平面無導腳半導體封裝件及其製法
US8203201B2 (en) * 2010-03-26 2012-06-19 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
US8917521B2 (en) 2010-04-28 2014-12-23 Advanpack Solutions Pte Ltd. Etch-back type semiconductor package, substrate and manufacturing method thereof
CN102244063A (zh) * 2010-05-14 2011-11-16 矽品精密工业股份有限公司 具有多边形芯片座的半导体封装件及其制法
KR101128999B1 (ko) * 2010-07-08 2012-03-23 엘지이노텍 주식회사 칩 패키지 제조 방법 및 이에 의해 제조된 칩 패키지
US8669654B2 (en) * 2010-08-03 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with die paddle and method of manufacture thereof
TWI401755B (zh) * 2010-08-10 2013-07-11 Adl Engineering Inc 四邊扁平無接腳封裝方法
CN104658923B (zh) * 2010-09-01 2018-08-14 群成科技股份有限公司 四边扁平无接脚封装方法及其制成的结构
US8304277B2 (en) 2010-09-09 2012-11-06 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
US8476772B2 (en) * 2010-09-09 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
TWI420630B (zh) 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8519518B2 (en) * 2010-09-24 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with lead encapsulation and method of manufacture thereof
US8546903B2 (en) * 2010-10-07 2013-10-01 Texas Instruments Incorporated Ionic isolation ring
US8912046B2 (en) * 2010-10-28 2014-12-16 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
TWI419290B (zh) 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
US20120140427A1 (en) * 2010-12-01 2012-06-07 Mediatek Inc. Printed circuit board (pcb) assembly with advanced quad flat no-lead (a-qfn) package
CN102487019B (zh) * 2010-12-02 2016-06-22 三星半导体(中国)研究开发有限公司 制造芯片封装件的方法
US8735224B2 (en) * 2011-02-14 2014-05-27 Stats Chippac Ltd. Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US20120241926A1 (en) * 2011-03-23 2012-09-27 Zigmund Ramirez Camacho Integrated circuit packaging system with leveling standoff and method of manufacture thereof
CN102214635A (zh) * 2011-05-27 2011-10-12 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
US9142426B2 (en) * 2011-06-20 2015-09-22 Cyntec Co., Ltd. Stack frame for electrical connections and the method to fabricate thereof
US8502363B2 (en) 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
US8513787B2 (en) * 2011-08-16 2013-08-20 Advanced Analogic Technologies, Incorporated Multi-die semiconductor package with one or more embedded die pads
CN102354689B (zh) * 2011-11-04 2013-12-04 北京工业大学 一种面阵引脚排列四边扁平无引脚封装及制造方法
US9219029B2 (en) 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
CN102522391B (zh) * 2011-12-31 2014-11-05 天水华天科技股份有限公司 一种具有接地环的e/LQFP堆叠封装件及其生产方法
TWI462255B (zh) * 2012-02-29 2014-11-21 矽品精密工業股份有限公司 封裝結構、基板結構及其製法
US8674487B2 (en) * 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
CN102629599B (zh) * 2012-04-06 2014-09-03 天水华天科技股份有限公司 四边扁平无引脚封装件及其生产方法
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
US9324584B2 (en) * 2012-12-14 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with transferable trace lead frame
CN103065975B (zh) * 2012-12-17 2015-05-13 北京工业大学 一种再布线qfn封装器件的制造方法
US9368423B2 (en) * 2013-06-28 2016-06-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package
US9570381B2 (en) * 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US9515032B1 (en) * 2015-08-13 2016-12-06 Win Semiconductors Corp. High-frequency package
CN105355619B (zh) * 2015-12-03 2018-11-02 日月光封装测试(上海)有限公司 导线框架条
CN105789072B (zh) * 2016-05-04 2018-06-08 天水华天科技股份有限公司 一种面阵列无引脚csp封装件及其制造方法
TWI604585B (zh) * 2016-12-23 2017-11-01 恆勁科技股份有限公司 基板結構的製造方法
JP6857035B2 (ja) * 2017-01-12 2021-04-14 ローム株式会社 半導体装置
US10134660B2 (en) * 2017-03-23 2018-11-20 Nxp Usa, Inc. Semiconductor device having corrugated leads and method for forming
TW201916182A (zh) * 2017-09-14 2019-04-16 矽品精密工業股份有限公司 電子封裝件
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
CN113035721A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096790A1 (en) * 2000-10-23 2002-07-25 Rohm Co., Ltd. Semiconductor device and method of making the same

Family Cites Families (143)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0476664B1 (en) 1990-09-20 1995-07-05 Dainippon Screen Mfg. Co., Ltd. Method of forming small through-holes in thin metal plate
US5389739A (en) 1992-12-15 1995-02-14 Hewlett-Packard Company Electronic device packaging assembly
US5497032A (en) * 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR0185512B1 (ko) 1996-08-19 1999-03-20 김광호 칼럼리드구조를갖는패키지및그의제조방법
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JP2928190B2 (ja) 1997-04-09 1999-08-03 九州日本電気株式会社 テーピングリードフレーム
KR100235308B1 (ko) 1997-06-30 1999-12-15 윤종용 2중 굴곡된 타이바와 소형 다이패드를 갖는 반도체 칩 패키지
US6132593A (en) 1998-06-08 2000-10-17 Tan; Yong-Jun Method and apparatus for measuring localized corrosion and other heterogeneous electrochemical processes
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7226811B1 (en) 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7247526B1 (en) * 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
JP3764587B2 (ja) 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
JP4030200B2 (ja) * 1998-09-17 2008-01-09 株式会社ルネサステクノロジ 半導体パッケージおよびその製造方法
US6667541B1 (en) 1998-10-21 2003-12-23 Matsushita Electric Industrial Co., Ltd. Terminal land frame and method for manufacturing the same
US6303985B1 (en) 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
JP4097403B2 (ja) 1998-12-02 2008-06-11 株式会社ルネサステクノロジ 半導体装置
SG75154A1 (en) 1999-02-23 2000-09-19 Inst Of Microelectronics Plastic ball grid array package
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
TW423133B (en) 1999-09-14 2001-02-21 Advanced Semiconductor Eng Manufacturing method of semiconductor chip package
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6333252B1 (en) 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6261864B1 (en) 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6342730B1 (en) 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
EP1122778A3 (en) 2000-01-31 2004-04-07 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7091606B2 (en) 2000-01-31 2006-08-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device and semiconductor module
JP3706533B2 (ja) 2000-09-20 2005-10-12 三洋電機株式会社 半導体装置および半導体モジュール
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6562660B1 (en) 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
US6242284B1 (en) 2000-05-05 2001-06-05 Advanced Semiconductor Engineering, Inc. Method for packaging a semiconductor chip
JP3883784B2 (ja) 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
JP2001338947A (ja) 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
TW506236B (en) 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
US6683368B1 (en) 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
TW507482B (en) 2000-06-09 2002-10-21 Sanyo Electric Co Light emitting device, its manufacturing process, and lighting device using such a light-emitting device
JP3650001B2 (ja) 2000-07-05 2005-05-18 三洋電機株式会社 半導体装置およびその製造方法
US6429536B1 (en) 2000-07-12 2002-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device
TW473965B (en) 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
TW497371B (en) 2000-10-05 2002-08-01 Sanyo Electric Co Semiconductor device and semiconductor module
US6762118B2 (en) * 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
JP3653460B2 (ja) 2000-10-26 2005-05-25 三洋電機株式会社 半導体モジュールおよびその製造方法
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
JP3895570B2 (ja) 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6720207B2 (en) 2001-02-14 2004-04-13 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US6661083B2 (en) 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
JP3609737B2 (ja) 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
KR100393448B1 (ko) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP4034073B2 (ja) 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003017646A (ja) * 2001-06-29 2003-01-17 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置およびその製造方法
TWI264099B (en) 2001-07-09 2006-10-11 Sumitomo Metal Mining Co Lead frame and manufacturing method therefor
TW538658B (en) 2001-08-27 2003-06-21 Sanyo Electric Co Manufacturing method for circuit device
JP2003124421A (ja) 2001-10-15 2003-04-25 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
US7001798B2 (en) 2001-11-14 2006-02-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
JP4173346B2 (ja) 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
EP1500137A1 (en) 2002-04-11 2005-01-26 Koninklijke Philips Electronics N.V. Carrier, method of manufacturing a carrier and an electronic device
US6777265B2 (en) 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2004063615A (ja) 2002-07-26 2004-02-26 Nitto Denko Corp 半導体装置の製造方法、半導体装置製造用接着シートおよび半導体装置
KR20040030283A (ko) 2002-09-05 2004-04-09 신꼬오덴기 고교 가부시키가이샤 리드 프레임 및 그 제조 방법
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
JP4159431B2 (ja) * 2002-11-15 2008-10-01 株式会社ルネサステクノロジ 半導体装置の製造方法
CN100382298C (zh) 2002-12-20 2008-04-16 Nxp股份有限公司 电子器件及其制造方法
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
TW200425427A (en) 2003-05-02 2004-11-16 Siliconware Precision Industries Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
TWI233674B (en) 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
EP1654753A4 (en) 2003-08-14 2009-01-21 Advanced Interconnect Tech Ltd SEMICONDUCTOR APPARATUS HOUSING AND METHOD OF MANUFACTURING THE SAME
TWI257693B (en) 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
US7060535B1 (en) 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
KR100568225B1 (ko) 2003-11-06 2006-04-07 삼성전자주식회사 리드 프레임 및 이를 적용한 반도체 패키지 제조방법
JP2005191240A (ja) 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP2005191342A (ja) * 2003-12-26 2005-07-14 Renesas Technology Corp 半導体装置およびその製造方法
TWI254437B (en) 2003-12-31 2006-05-01 Advanced Semiconductor Eng Leadless package
US7122406B1 (en) 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
JP2005203390A (ja) 2004-01-13 2005-07-28 Seiko Instruments Inc 樹脂封止型半導体装置の製造方法
US7009286B1 (en) * 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7494557B1 (en) 2004-01-30 2009-02-24 Sandia Corporation Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures
US7215009B1 (en) * 2004-02-23 2007-05-08 Altera Corporation Expansion plane for PQFP/TQFP IR—package design
US7008820B2 (en) * 2004-06-10 2006-03-07 St Assembly Test Services Ltd. Chip scale package with open substrate
CN2726111Y (zh) 2004-06-22 2005-09-14 胜开科技股份有限公司 堆叠集成电路封装组件
US7545026B2 (en) 2004-07-13 2009-06-09 Nxp B.V. Electronic device comprising an integrated circuit
US7087461B2 (en) * 2004-08-11 2006-08-08 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
TWI256096B (en) 2004-10-15 2006-06-01 Advanced Semiconductor Eng Method for fabricating quad flat non-leaded package
US7598606B2 (en) * 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
US7087462B1 (en) * 2005-06-07 2006-08-08 Advanced Semiconductor Engineering, Inc. Method for forming leadless semiconductor packages
US7348663B1 (en) 2005-07-15 2008-03-25 Asat Ltd. Integrated circuit package and method for fabricating same
TWI287275B (en) * 2005-07-19 2007-09-21 Siliconware Precision Industries Co Ltd Semiconductor package without chip carrier and fabrication method thereof
JP3947750B2 (ja) 2005-07-25 2007-07-25 株式会社三井ハイテック 半導体装置の製造方法及び半導体装置
KR101089449B1 (ko) 2005-08-10 2011-12-07 가부시키가이샤 미츠이하이테크 반도체 장치 및 그 제조 방법
US7262491B2 (en) 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
TWI264091B (en) * 2005-09-15 2006-10-11 Siliconware Precision Industries Co Ltd Method of manufacturing quad flat non-leaded semiconductor package
US8163604B2 (en) 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7372133B2 (en) * 2005-12-01 2008-05-13 Intel Corporation Microelectronic package having a stiffening element and method of making same
TW200729429A (en) 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
TW200729444A (en) 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
JP2007221045A (ja) 2006-02-20 2007-08-30 Oki Electric Ind Co Ltd マルチチップ構造を採用した半導体装置
US7301225B2 (en) 2006-02-28 2007-11-27 Freescale Semiconductor, Inc. Multi-row lead frame
TWI286375B (en) * 2006-03-24 2007-09-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same
US7683461B2 (en) * 2006-07-21 2010-03-23 Stats Chippac Ltd. Integrated circuit leadless package system
US20080029855A1 (en) 2006-08-04 2008-02-07 Yi-Ling Chang Lead Frame and Fabrication Method thereof
US9281218B2 (en) * 2006-08-30 2016-03-08 United Test And Assembly Center Ltd. Method of producing a semiconductor package
JP4533875B2 (ja) 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
US20080079124A1 (en) 2006-10-03 2008-04-03 Chris Edward Haga Interdigitated leadfingers
US7741704B2 (en) 2006-10-18 2010-06-22 Texas Instruments Incorporated Leadframe and mold compound interlock in packaged semiconductor device
WO2008057770A2 (en) * 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7608484B2 (en) * 2006-10-31 2009-10-27 Texas Instruments Incorporated Non-pull back pad package with an additional solder standoff
US7608482B1 (en) 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
US7605477B2 (en) 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US7800211B2 (en) 2007-06-29 2010-09-21 Stats Chippac, Ltd. Stackable package by using internal stacking modules
US7675146B2 (en) 2007-09-07 2010-03-09 Infineon Technologies Ag Semiconductor device with leadframe including a diffusion barrier
US20090127682A1 (en) 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US7808089B2 (en) 2007-12-18 2010-10-05 National Semiconductor Corporation Leadframe having die attach pad with delamination and crack-arresting features
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
TWI368983B (en) 2008-04-29 2012-07-21 Advanced Semiconductor Eng Integrated circuit package and manufacturing method thereof
TW200947654A (en) 2008-05-12 2009-11-16 Advanced Semiconductor Eng Stacked type chip package structure and method of fabricating the same
TWI372458B (en) 2008-05-12 2012-09-11 Advanced Semiconductor Eng Stacked type chip package structure
US7786557B2 (en) 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
CN101442035B (zh) 2008-12-14 2011-03-16 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110163430A1 (en) 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096790A1 (en) * 2000-10-23 2002-07-25 Rohm Co., Ltd. Semiconductor device and method of making the same

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