CN101661797B - Manufacturing method of nonvolatile memory, writing method and reading method thereof - Google Patents
Manufacturing method of nonvolatile memory, writing method and reading method thereof Download PDFInfo
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- CN101661797B CN101661797B CN 200910177543 CN200910177543A CN101661797B CN 101661797 B CN101661797 B CN 101661797B CN 200910177543 CN200910177543 CN 200910177543 CN 200910177543 A CN200910177543 A CN 200910177543A CN 101661797 B CN101661797 B CN 101661797B
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Abstract
The invention provides a method for manufacturing a nonvolatile memory, comprising: first, a waiting coding memory is provided, and a memory bank of the waiting coding memory has a first state after being programmed and a second state before being programmed; then, the number of the first states and the second states in program data to be coded can be calculated; when the number of the first states is more than that of the second states, the program data to be coded is reversely defined; and finally, after being reversely defined, the program data to be coded is written into the waiting coding memory.
Description
The application be that March 29, application number in 2007 are 200710088991.3 the applying date, denomination of invention divides an application for the application for a patent for invention of " manufacture method of nonvolatile memory, wiring method and read method ".
Technical field
The present invention relates to a kind of manufacture method, wiring method and read method of nonvolatile memory, and be particularly related to a kind of manufacture method that causes the nonvolatile memory of implanted ions failure because of foreign matter that reduces, and wiring method and the corresponding read method that can reduce the sequencing time of nonvolatile memory.
Background technology
Along with the arriving in digital and electronic epoch, also day by day ardent for the demand of data storage medium, therefore for can also constantly seeking the mode that improves with the semiconductor technology of a large amount of mediums of cheap cost production.
In the medium of being produced with semiconductor technology, the most extensive not need electric power can keep the nonvolatile memory of state data memory (non-volatile memory, NVM) range of application.Nonvolatile memory can be divided into the shielded read-only memory (maskread-only memory, MROM) with implanted ions definition data; And can a secondary program (one time program, OTP) reach repeatedly program (multi-time program, MTP) storer, for example ROM-BIOS of computing machine (basic input/output system, BIOS).And the user can carry out repeatedly the storer of program-erase, for example flash memory (flash memory).Wherein, shielded read-only memory and a program storage can low cost be produced in a large number because technique is comparatively simple, therefore are fit to a large amount of software product that copies, for example game card boxes produced of needs.
Take shielded read-only memory as example, its program coding mode is the waiting coding memory of completing in advance with implanted ions one.As shown in Figure 1, it shows the partial structurtes schematic diagram of waiting coding memory.Waiting coding memory 10 has the bit line 1 of many arrangements parallel to each other, and vertical with bit line 1 and be arranged on the top character line 2.Character line 2 between any two bit lines 1 is the position of memory bank 3 to be encoded, and mode that can implanted ions defines different position states, will want coded program and be recorded on waiting coding memory 10.
Yet, because implanted ions must expose the memory bank to be encoded 3 that wish is implanted, might be because foreign matter hides resistance or implants the inaccurate graft failure that causes of impedance layer contraposition.Therefore in the situation that the memory bank to be encoded that exposes is relatively many, because causing the probability of defective, also relatively improves graft failure.
In addition, the present repeatedly program storage that once reaches too much the time, needs the expensive time carry out electric sequencing when data meta state 0.Add memory bank that residue not have use when too much, also need spended time that the memory bank program of correspondence is turned to 0, virtually waste many time costs.
Summary of the invention
In view of this, the invention provides a kind of method of operating of nonvolatile memory, is the reverse definition that changes the memory bank to be encoded of implantation and coordinate storer, improves the yield rate that nonvolatile memory is produced.Be applied in simultaneously in the sequencing of nonvolatile memory, can also reduce the required production time.
According to the present invention, a kind of method of operating of nonvolatile memory is proposed, comprise the following steps: at first, a waiting coding memory is provided, and the memory bank of this waiting coding memory has the second state have first state and sequencing after sequencing before.Then, calculate to want in the coded program data quantity of first state and second state.Then, during greater than the quantity of second state, oppositely the coded program data are wanted in definition when the quantity of first state.Then, the wish coded program data after this reverse definition are write in waiting coding memory.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below.
Description of drawings
Fig. 1 shows the partial structurtes schematic diagram of waiting coding memory;
Fig. 2 shows the manufacture method process flow diagram of nonvolatile memory of the present invention;
Fig. 3 A shows the partial structurtes schematic diagram of waiting coding memory;
Fig. 3 B shows the vertical view of shielding;
Fig. 3 C shows has the vertical view that patterning is implanted the waiting coding memory of impedance layer;
Fig. 3 D shows in Fig. 3 C the sectional view along profile line AA ';
Fig. 4 shows the read functions calcspar of nonvolatile memory of the present invention;
Fig. 5 A shows the generation circuit diagram of the control signal of the first multiplexer of the present invention;
Fig. 5 B shows the generation circuit diagram of the control signal of the second multiplexer of the present invention;
Fig. 6 shows writing of nonvolatile memory of the present invention and reading circuit functional schematic;
Fig. 7 shows the process flow diagram that writes of nonvolatile memory of the present invention; And
Fig. 8 shows the process flow diagram that reads of nonvolatile memory of the present invention.
The reference numeral explanation
1,110: bit line
2,120: character line
3,130: memory bank to be encoded
10,100: waiting coding memory
20: shielding
21,22,23: perforate
130a: the first memory bank
130b: the second memory bank
140: insulation course
150: ground
210～270: step
300: patterning is implanted impedance layer
310,320,330: notch
400,600: nonvolatile memory
410,602: the non-volatile memories volume array
420,604: induction amplifier
425: phase inverter
430: multiplexer
440,650: output port
610: the 1 group of data input channels
612: the 1 buffer registers
613: the 1 input multiplexers
614: the 1 input inverters
620: the n group data input channels
622: the n buffer registers
623: the n input multiplexers
624: the n input inverters
NM0, NM1:N type metal oxide semiconductor
PM0, PM1:P type metal oxide semiconductor
630: the 1 group of data delivery channels
632: the 1 output multi-channel multiplexers
634: the 1 output phase inverters
640: the n group data delivery channels
642: the n output multi-channel multiplexers
644: the n output phase inverters
Embodiment
Please refer to Fig. 2, it shows the manufacture method process flow diagram of nonvolatile memory of the present invention.And please be simultaneously with reference to the 3A～Fig. 3 D.Fig. 3 A shows the partial structurtes schematic diagram of waiting coding memory.Fig. 3 B shows the vertical view of shielding.Fig. 3 C shows has the vertical view that patterning is implanted the waiting coding memory of impedance layer.Fig. 3 D shows in Fig. 3 C the sectional view along profile line AA '.
At first, as shown in step 210, and with reference to Fig. 3 A, provide a waiting coding memory 100.Waiting coding memory 100 has the bit line 110 of many arrangements parallel to each other, and vertical with bit line 110 and be arranged at the top character line 120.Be the memory bank to be encoded 130 of lining up array with character line 120 staggered places between any two bit lines 110, have in the present embodiment nine memory banks 130 to be encoded.
Then, as shown in step 220, calculate to want in coded program the quantity of first state and second state.In the present embodiment, first state is for example 0, and the second state is for example 1.Certainly, also first state of definable is 1, and the second state is 0, the invention is not restricted to this.In the present embodiment, suppose that the quantity of first state in the wish coded program is more, and the record of first state 0 need to carry out sequencing (program) with implanted ions memory bank 130 to be encoded.To explain as an example of boron implant (boron) example in the present embodiment.
Then, as shown in step 230, when the quantity of first state 0 during greater than the quantity of second state 1, namely to carry out the bank number of implanted ions when more, a shielding is provided.Please refer to Fig. 3 B, shielding 20 has three perforates 21,22,23, a respectively corresponding memory bank 130 to be encoded, and the quantity of perforate is identical with quantity and the position of the second state 1 of wanting coded program.That is to say, in the memory bank to be encoded with the corresponding second state 1 of wanting coded program originally of implanted ions, but not in the memory bank to be encoded of corresponding first state 0 wanting coded program originally.
Then, as shown in step 240, form one and implant the impedance material layer on waiting coding memory 100.
Then, as shown in step 250, in implanting the impedance material layer, implant impedance layer 300 to form a patterning with the shielding define pattern.Please refer to Fig. 3 C, patterning is implanted impedance layer 300 and is had notch 310,320,330, the memory bank to be encoded 130 of notch 310,320,330 exposed portions serve.That is to say, the memory bank that will carry out implanted ions is originally covered, carry out implanted ions and the memory bank that will not carry out implanted ions is originally exposed.
Then, as shown in step 260, and with reference to Fig. 3 D.Be embedded with multiple bit lines 110 on the ground 150 of waiting coding memory 100, separate with insulation course 140 between character line 120 and ground 150.So-called memory bank is 110 of two bit lines, is positioned at the passage on ground 150, and ion passes character line 120 and squeezes in ground 150 and define.The memory bank to be encoded 130 that implanted ions exposes, take the memory bank to be encoded 130 that defines implanting ions not as the first memory bank 130a, and the memory bank to be encoded 130 of definition implanting ions is the second memory bank 130b.And relatively when conducting the first memory bank 130a and the second memory bank 130b, by the first memory bank 130a and the first current value of the second memory bank 130b and the size of the second current value and a reference current value, have respectively a second state 1 and one first state 0 to define the first memory bank 130a and the second memory bank 130b respectively.In the present embodiment, the first current value is greater than reference current value, and the second current value is less than reference current value.
Then, as shown in step 270, because desired state of position state and wish coded program of defined memory bank is just the opposite, therefore oppositely define waiting coding memory 100.That is to say, when defining the first current value greater than reference current value, the first memory bank 130a has first state; The second current value is during less than reference current value, and the second memory bank 130b has the second state.Make the first memory bank 130a and the second memory bank 130b have respectively first state 0 and second state 1.Desired state of the position state that this moment, waiting coding memory 100 recorded and wish coded program is namely identical.
Yet in step 230, if the quantity of wanting first state 0 in coded program during less than the quantity of second state 1, the negligible amounts due to first state 0 of need implanted ions definition provides a secondary shielding.Secondary shielding has the second perforate, and the quantity of the second perforate is identical with the quantity of first state 0.Then, in implanting the impedance material layer, implant impedance layer to form one second patterning with the secondary shielding define pattern.The second patterning is implanted impedance layer and is had the second notch, the memory bank to be encoded of the second notch exposed portions serve.Then, the memory bank to be encoded 130 that implanted ions exposes take the memory bank to be encoded that defines implanting ions as the 3rd memory bank, and defines not that the memory bank to be encoded of implanting ions is the 4th memory bank.And relatively when conducting the 3rd memory bank and the 4th memory bank, by the 3rd memory bank and the 3rd current value of the 4th memory bank and the size of the 4th current value and reference current value, have respectively first state 0 and second state 1 to define the 3rd memory bank and the 4th memory bank respectively.Because desired state of the position state of defined memory bank and wish coded program is identical, therefore need oppositely not define.
Usually know the knowledgeable yet the technical field under the present invention has, technology of the present invention is not limited to this as can be known.In step 260 relatively in the step of the first current value and the second current value, can be also the first current value during less than reference current value, the first memory bank 130a has second state 1; The second current value is during greater than reference current value, and the second memory bank 130b has first state 0.Therefore in step 270 oppositely defined the step of waiting coding memory 100, when defining the first current value less than reference current value, the first memory bank 130a had first state 0; The second current value is during greater than reference current value, and the second memory bank 130b has second state 1.Hence one can see that, and first state and second state are 0 or 1, and the magnitude relationship of the first current value and the second current value and reference current value, relevant with the ion of implanting, and is not particularly limited in the present invention.
In addition, though the present embodiment explains as an example of shielded read-only memory example, the scope of utilizing of the present invention is not limited to this.The present invention also can be used in the formation that contact hole (contact hole) is fastened plug, has equally the effect that promotes yield rate.Utilize mode of the present invention to carry out implanted ions to the protected type storer, because it is less to expose the memory bank proportion of implanting, can effectively reduce because foreign matter blocks the probability that causes graft failure and produce the data definition mistake.
The described reverse definition of the step 270 of leading portion such as Fig. 2 can be reached by circuit design.Please refer to Fig. 4, it shows the read functions calcspar of nonvolatile memory of the present invention.Nonvolatile memory 400 comprises non-volatile memories volume array 410 and induction amplifier 420, output after the signal that non-volatile memories volume array 410 is read amplifies via induction amplifier 420.Nonvolatile memory 400 can be shielded read-only memory (mask read-only memory, Mask ROM), a secondary program (one-time program, OTP) storer, repeatedly program (multi-time program, MTP) storer and the flash memory (flash memory) that can carry out repeatedly program-erase.As shown in Figure 4, if want the coded program data originally not through oppositely definition, can follow path P 2, export output port 440 to after selecting via multiplexer (MUX) 430 with position definition status originally; If wanted originally the once oppositely definition originally of coded program data, can follow path P 1, after again oppositely defining through phase inverter 425, export output port 440 to after selecting via multiplexer (MUX) 430.
As for the selection of path P 1, P2, be the control signal V by multiplexer 430
aDecide.Please refer to Fig. 5 A and Fig. 5 B, it shows respectively the generation circuit diagram of the control signal of the first of the present invention and the second multiplexer.As shown in Fig. 5 A, circuit series winding P-type mos (the metal oxide semiconductor in left side, MOS) PM0 and N-type metal-oxide semiconductor (MOS) NM0, circuit series winding P-type mos PM1 and the N-type metal-oxide semiconductor (MOS) NM1 on right side.This kind structure is to decide V by sequencing N-type metal-oxide semiconductor (MOS) NM0 or NM1
aOutput voltage.For example when sequencing NM0, although NM0 and NM1 connect high-pressure side V at grid respectively
cc, but NM0 has higher threshold voltage because of sequencing can't with earth terminal GND conducting.Relative, NM1 can with earth terminal GND conducting, so V
aCurrent potential identical with earth terminal GND.And be coupled to the circuit on right side due to the grid of PM0, so grid potential is identical with earth terminal GND, makes the PM0 conducting and makes current potential and the high-pressure side V of left side circuit
ccIdentical.And the grid of PM1 couples with the left side circuit, so the grid potential of PM1 and high-pressure side V
ccIdentical, the grid that makes PM1 with pathway closure to suppress electric current.Thus, can avoid the right side circuit to continue generation current and cause loss.Relative, V
aOutput high-pressure side V
ccCurrent potential the time, sequencing NM1.
As shown in Fig. 5 B, its assembly is identical from Fig. 5 A but mode of connection is different, and this kind structure is to decide V by sequencing P-type mos PM0 or PM1
aOutput voltage.For example when sequencing PM0, although PM0 and PM1 connect earth terminal GND at grid respectively, PM0 because sequencing has higher threshold voltage can't with earth terminal GND conducting.Relative, PM1 can with high-pressure side V
ccConducting, so V
aCurrent potential and high-pressure side V
ccIdentical.And be coupled to the circuit on right side due to the grid of NM0, so grid potential and high-pressure side V
ccIdentical, make the NM0 conducting and make the left side circuit current potential identical with earth terminal GND.And the circuit in the grid of NM1 and left side couples, so the grid potential of NM1 is identical with earth terminal GND, the grid that makes NM1 with pathway closure to suppress electric current.Thus, can avoid the right side circuit to continue generation current and cause loss.Relative, V
aDuring the current potential of output earth terminal GND, sequencing PM1.
Therefore by the circuit structure that adopts Fig. 5 A or Fig. 5 B, can control V by the different MOS assembly of sequencing
aExport different current potentials, provide nonvolatile memory 400 to select different path output data.
Propose to be used for writing of OTP, MTP and flash memory and read method please refer to Fig. 6 as for the present invention, it shows writing of nonvolatile memory of the present invention and reading circuit functional schematic.And please be simultaneously with reference to Fig. 7, it shows the process flow diagram that writes of nonvolatile memory of the present invention.At first, as shown in step 701, provide a waiting coding memory 600.Waiting coding memory 600 comprises non-volatile memories volume array 602 and induction amplifier 604, and non-volatile memories volume array 602 has respectively one first state and a second state after sequencing with before sequencing, refers to respectively in this embodiment 0 with 1.
Then, as shown in step 702, calculate a quantity of wanting in the coded program data first state 0 and second state 1.This function can be write as and be integrated in the circuit structure of waiting coding memory 600 by program language.
Then, as shown in step 703, whether the quantity that judges first state 0 is greater than the quantity of second state 1.During greater than the quantity of this second state 1, as shown in step 704, oppositely the coded program data are wanted in definition when the quantity of first state 0.Then, as shown in step 705, will want the coded program data and write in waiting coding memory 600.Relative, if in step 703, the quantity of first state 0 as shown in step 706, keeps original position state to define and writes in waiting coding memory 600 during less than the quantity of second state 1.
Usually know the knowledgeable but the technical field under the present invention has, technology of the present invention is not limited to this as can be known.Wish coded program data more can be divided into the 1st to n and organize, for example in the present embodiment, waiting coding memory 600 more comprises n data input channel, distinguishing wish coded program data according to the data input channel that passes through is the 1st to n group, only draws for simplicity the 1st group of input data channel 610 and n group input data channel 620 in Fig. 6.Each organizes data channel as shown in step 702, calculates respectively by the 1st to n group of the 1st to n data channel and wants in the coded program data, the quantity of the quantity of first state 0 and second state 1.Each data channel of waiting coding memory 600 more comprises and comprises respectively an input multiplexer (MUX), for example the 1st input multiplexer 613 of Fig. 6 is to n input multiplexer 623, in order to as shown in step 703, according to the quantity of first state 0 and second state 1, whether need oppositely definition with the wish coded program data that determine to write.The 1st input multiplexer 613 to n input multiplexer 623 respectively by controlling voltage V
in1 to V
inN controls, V
in1 to V
inN can adopt the circuit structure as 5A figure or Fig. 5 B to produce, and will adopt path P with determination data channel 610
in1_1 or P
in1_2, and data channel 620 will adopt path P
inN_1 or P
inN_2.
When each the 1st to n group is wanted in coded program data, the quantity of first state 0 is during greater than the quantity of second state 1, as shown in step 704, use as the 1st input inverter 614 of Fig. 6 to n input inverter 624, oppositely definition wish coded program data.Then each group is wanted the coded program data as shown in step 705, after accumulating certain data writing via the 1st buffer register 612 to the n buffer register respectively, in the wish coded program data write-once waiting coding memory 600 with accumulation.Relative, when each the 1st to n group is wanted in coded program data, the quantity of first state 0 as shown in step 706, keeps original position state to define and writes in waiting coding memory 600 during less than 1 quantity of second state.
By the writing mode that the present embodiment proposes, can make electric program change into the time decreased that the second state needs, improve the production efficiency of storer.In addition, more oppositely define in the present embodiment waiting coding memory 600 write want the coded program data after, the position state of remaining memory bank in non-volatile memories volume array 602, this function can be by arranging other one group of input multiplexer, oppositely defines in order to the position state of the memory bank that whole non-volatile memories volume array 602 is remaining.Because untapped memory bank must be programmed into 0 through electric, if can significantly save the required time of sequencing through reverse definition.When especially remaining memory bank ratio is very high, more can make the production time of storer significantly reduce, improving production efficiency.
Below introduce the method for reading non-volatile storage 600.Please refer to Fig. 8, it shows the process flow diagram that reads of nonvolatile memory of the present invention, and asks the while with reference to the assembly label of Fig. 6.As shown in step 801, the wish coded program data in the reading non-volatile bank array are via exporting after induction amplifier 604 amplifying signals.
Then, as shown in step 802, check the whether oppositely definition of these wish coded program data.
Then, as shown in step 803, be oppositely definition if want the coded program data, oppositely once output afterwards of definition again.If want the coded program data without reverse definition, as shown in step 804, keep original position state definition output.
Inputted if divide into originally n group data channel with the present embodiment, and relatively also needed to export with n group data channel, only drew for simplicity the 1st group of output data channel 630 and n group output data channel 640 in Fig. 6.Therefore, as shown in step 802, check each the 1st to n group wish coded program data were write fashionable whether once oppositely the definition originally, and this function can also be integrated into by the program writing reading circuit of nonvolatile memory 600.If it is oppositely definition that arbitrary the 1st to n group is wanted the coded program data, as shown in step 803, reverse definition once each group is wanted to export output port 650 to after the coded program data.For example in the 1st group of data delivery channel 630 and n group data delivery channel 640, follow path P
out1_2 and P
outN_2 is undertaken oppositely by the 1st output phase inverter 634 and n output phase inverter 644.If there is no reverse definition process mistake before arbitrary the 1st to n group is wanted the coded program data, keep each group to want the original position state definition of coded program data and export output port 650 to.For example in the 1st group of data delivery channel 630 and n group data output 640, follow path P
out1_1 and P
outN_1.As for the selection in path, be to be decided by each group output multi-channel multiplexer in data channel, the 1st output multi-channel multiplexer 632 and the n output multi-channel multiplexer 642 in data channel 630 and 640 for example.The control voltage V of the 1st output multi-channel multiplexer 632 and n output multi-channel multiplexer 642
out1 and V
outN can adopt the circuit as 5A figure or Fig. 5 B to produce equally.In addition, if also once oppositely definition of remaining memory bank originally, again oppositely define waiting coding memory 600 write want the coded program data after, export after the position state of non-volatile memories volume array 602 residue memory banks.This function can oppositely be exported after definition in order to the position state of the memory bank that whole non-volatile memories volume array 602 is remaining again by other one group of output multi-channel multiplexer is set, and is the data kenel of original definition.
The manufacture method of the disclosed nonvolatile memory of the above embodiment of the present invention, when the bank number to be encoded that needs implanted ions is more, the memory bank to be encoded that originally need not implant is carried out implanted ions, make memory bank to be encoded implant the position state opposite with wanting coded program.Then again that the definition of waiting coding memory is reverse, namely obtain and the storer of wanting coded program identical bits state.Because the bank number to be encoded of exposing is less, can reduces and stop or implant the probability that the impedance layer misalignment causes graft failure because of foreign matter.Therefore the present invention does not need to increase extra step or significantly changes technique, can reduce because foreign matter blocks or implant the probability that the impedance layer misalignment causes the implanted ions failure, promotes the yield rate that nonvolatile memory is produced.And the wiring method of nonvolatile memory proposed by the invention and read method can be saved write time of nonvolatile memory greatly, increase the production efficiency of storer.
In sum, although the present invention discloses as above with a preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (3)
1. the method for operating of a nonvolatile memory, is characterized in that, comprising:
(a) provide a waiting coding memory, the memory bank of this waiting coding memory has a second state have one first state and sequencing after sequencing before, wherein this waiting coding memory comprises n data input channel, and distinguishing one according to described n data input channel, to want the coded program data be the 1st to n to organize;
(b) calculating respectively the 1st to n is organized in wish coded program data respectively, the quantity of the quantity of this first state and this second state;
(c) want the coded program data for the 1st to n group respectively, during greater than the quantity of this second state, oppositely define this wish coded program data when the quantity of this first state; And
(d) these group wish coded program data that will be somebody's turn to do after oppositely defining write in this waiting coding memory;
Wherein, these group wish coded program data of described reverse definition comprise:
By a shielding being provided, forming an implantation impedance material layer on this waiting coding memory;
Implant impedance layer in implanting the impedance material layer to form a patterning with the shielding define pattern; And
The memory bank to be encoded that implanted ions exposes.
2. method of operating as claimed in claim 1, is characterized in that, also comprises:
(e) when the quantity of this first state during less than the quantity of this second state, the position state definition that keeps original writes in this waiting coding memory.
3. method of operating as claimed in claim 1, is characterized in that, also comprises:
Read this waiting coding memory;
Check the whether oppositely definition of these wish coded program data; And
Be oppositely definition if should want the coded program data, oppositely once output afterwards of definition again.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910177543 CN101661797B (en) | 2006-09-20 | 2007-03-29 | Manufacturing method of nonvolatile memory, writing method and reading method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200610154290.0 | 2006-09-20 | ||
| CN200610154290 | 2006-09-20 | ||
| CN 200910177543 CN101661797B (en) | 2006-09-20 | 2007-03-29 | Manufacturing method of nonvolatile memory, writing method and reading method thereof |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710088991A Division CN100580813C (en) | 2006-09-20 | 2007-03-29 | Non-volatile memory production method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156324A (en) * | 1995-08-22 | 1997-08-06 | 三菱电机株式会社 | Semiconductor storing device |
| US5745401A (en) * | 1997-02-14 | 1998-04-28 | Lucent Technologies Inc. | High-speed programmable read only memory |
| CN1286494A (en) * | 1999-08-30 | 2001-03-07 | 旺宏电子股份有限公司 | Programming method for mask-type ROM |
| US6363001B1 (en) * | 1999-05-12 | 2002-03-26 | Stmicroelectronics S.R.L. | ROM with a reduced static consumption |
-
2007
- 2007-03-29 CN CN 200910177543 patent/CN101661797B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156324A (en) * | 1995-08-22 | 1997-08-06 | 三菱电机株式会社 | Semiconductor storing device |
| US5745401A (en) * | 1997-02-14 | 1998-04-28 | Lucent Technologies Inc. | High-speed programmable read only memory |
| US6363001B1 (en) * | 1999-05-12 | 2002-03-26 | Stmicroelectronics S.R.L. | ROM with a reduced static consumption |
| CN1286494A (en) * | 1999-08-30 | 2001-03-07 | 旺宏电子股份有限公司 | Programming method for mask-type ROM |
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