CN101681894B - 集成电路封装件和集成电路装置 - Google Patents

集成电路封装件和集成电路装置 Download PDF

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CN101681894B
CN101681894B CN2008800088956A CN200880008895A CN101681894B CN 101681894 B CN101681894 B CN 101681894B CN 2008800088956 A CN2008800088956 A CN 2008800088956A CN 200880008895 A CN200880008895 A CN 200880008895A CN 101681894 B CN101681894 B CN 101681894B
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moulding material
bonding wire
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integrated circuit
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CN101681894A (zh
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R·W·恩格尔
N·夏尔马
W·P·泰勒
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Allegro Microsystems Inc
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    • HELECTRICITY
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    • G01D5/12Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/142Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage using Hall-effect devices
    • G01D5/147Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage using Hall-effect devices influenced by the movement of a third element, the position of Hall device and the source of magnetic field being fixed in respect to each other
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract

本发明涉及使用多步骤成型方法来生产集成电路(410)的方法和装置,以保护接合引线。在一个实施例中,所述方法包括:将裸晶(414)连接到具有引线指状部的引线框架上;将接合引线(417)连接到裸晶(414)和引线指状部之间;在接合引线(417)、裸晶(414)、引线指状部的至少一部分上施加第一成型材料,以形成组件;等待直至第一成型材料至少部分地硬化;以及在所形成的组件上施加第二成型材料。各个实施例包括带有霍尔元件(412)的传感器或磁阻元件以及带有磁体且设置在组件背侧上的杆件式集中器。这些实施例用作齿轮齿传感器。

Description

集成电路封装件和集成电路装置
背景技术
在现有技术中公知地,集成电路(IC)包括引线框以支承着裸晶(die,或裸芯片)且为IC封装件提供外部连接结构。例如,裸晶和引线框指状部之间的连接结构可由接合引线来制成。对于塑料封装件而言,引线框/裸晶组件由塑料材料来包覆成型。 
在一种传统的封装件中,传感器包括具有背侧部的、所谓K型组件,其中磁体连接到所述背侧部上。连接有磁体的所述组件被模制或包裹到传感器壳体中。在一个公知的方法中,裸晶被连接到引线框上,通量集中器(flux concentrator)和/或磁体被连接,且所述组件被包覆成型。 
在成型过程中,相对纤细的接合引线可能会由于塑料的受压流动而断裂。此外,接合引线的易断性也限制了成型过程的效率。 
发明内容
本发明提供了用于集成电路的方法和装置,其具有被施加的第一成型材料以保护位于裸晶和引线指之间的接合引线连接结构,以及具有被施加在第一成型材料上的第二成型材料。通过利用第一成型材料来保护接合引线,使得可以使用相对高的压力来施加第二成型材料。利用这种结构,由于接合引线受到的损坏较少而提高了产量。尽管本发明主要参考传感器集成电路来显示和描述,但是可以理解本发明也可应用于一般的集成电路,其用于保护纤细的连接件免受裸晶的损害。 
根据本发明的一个方面,本发明涉及一种方法,其包括:将裸晶连接到具有引线指状部的引线框架上;将接合引线连接到裸晶和引线指状部之间;在接合引线、裸晶、引线指状部的至少一部分上施加第一成型材料,以形成组件;等待直至第一成型材料至少部分地硬化;以及在所形成的组件上施加第二成型材料。 
上述方法还进一步包括以下的一个或多个特征:仅在引线框的裸晶侧施加成型材料;施加第一成型材料以封装着接合引线;施加第一成型材料 以在引线框上封装着裸晶;至少部分地基于与磁体的膨胀系数的相似性,来选择第一成型材料所用的材料;第一成型材料和第二成型材料是不同的;至少部分地基于填充料的尺寸,来选择用于第一成型材料和/或第二成型材料所用的材料;在某一压力下施加第二成型材料,其中施加第二成型材料所用的压力显著地高于施加第一成型材料所用的压力;所述裸晶包括一个或多个霍尔元件;将集中器连接到组件上;所述接合引线包括金线。 
本发明的另一方面涉及一种集成电路装置,其包括:裸晶,其连接到具有引线指状部的引线框架上;接合引线,其连接到裸晶和引线指状部之间;第一成型材料,其覆盖着接合引线、裸晶、引线指状部的至少一部分,以形成组件;以及第二成型材料,其对所述组件进行包覆成型。 
上述装置还进一步包括以下的一个或多个特征:第一成型材料仅位于引线框的裸晶侧;第一成型材料封装着接合引线;第一成型材料封装着引线框上的裸晶;第一成型材料的膨胀系数与磁体的膨胀系数相兼容;第一成型材料和第二成型材料是不同的;所述裸晶包括一个或多个霍尔元件;所述接合引线包括金线。 
附图说明
通过以下的详细说明以及附图,将更加完全地理解本发明所包含的示例性实施例,其中: 
图1是示例性集成电路的示意图,其包括根据本发明示例性实施例的多步骤成型过程。 
图1A是图1的集成电路的示意立体图。 
图2A是示例性集成电路的透视俯视图,其包括根据本发明示例性实施例的多步骤成型过程。 
图2B是图2A的集成电路的透视侧部线条图。 
图3是示例性集成电路的局部透视立体图,其包括根据本发明示例性实施例的多步骤成型过程。 
图4是流程图,显示了示例性步骤顺序,以实现根据本发明示例性实施例的集成电路所用的多步骤成型过程。 
图5是具有接合引线的集成电路传感器的示意立体图,所述集成电路传感器由第一成型材料所防护,以形成由第二成型材料所包覆成型的组件。 
具体实施方式
图1显示了作为传感器的示例性集成电路(IC)100,其由根据本发明示例性的多步骤成型过程而制造。在示例性实施例中,传感器100是齿轮齿传感器,以探测在齿轮12上的齿10的移动。总体而言,第一成型步骤用来防护接合引线。在第一成型工艺完成之后,实行第二成型步骤以完成最终的封装结构。 
在示例性实施例中,传感器100包括霍尔IC 102,其具有设置在引线框108上的第一和第二霍尔元件104、106。集中器(concentrator)110(如图所示为杆件式集中器)设置在组件的后侧上,同时磁体112紧固到所述集中器上。以下将详细介绍,在一个示例性实施例中,在对具有集中器110和磁体112的组件进行包覆成型之前,所述组件在第一步骤中进行成型,以防护着从IC 102到引线框108范围内的接合引线(wirebond)。 
图1A显示了用于图1的霍尔集成电路用的示例性IC封装件100,其结构为4引脚(120a-120d)SIP(单列直插式封装)。IC 100是两个接合引线、差动峰值探测的齿轮齿传感器(GTS)。 
图2A和2B示出了示例性集成电路200的剖视图,所述集成电路200包括根据本发明示例性实施例的多步骤成型过程所制造的第一成型材料202和第二成型材料204。IC 200,如图所示为传感器IC,包括设置在引线框208上的裸晶206。一系列的接合引线210使得裸晶206和引线框208的引线指状部之间进行电连接。裸晶/接合引线组件由第一成型材料202所包覆成型。IC 200进一步包括由第二材料204包覆成型的集中器214和磁体216。 
在所示的实施例中,接合引线210从裸晶206仅延伸到引线框208的一侧。在其他实施例中,接合引线210可延伸到裸晶206的两侧和/或两端。 
第一模制材料202以能够保护接合引线210的完整性的方式进行施加。在一个实施例中,第一模制材料202在引线框208的裸晶侧仅封装着裸晶206和接合引线210。在封装件的背后侧不进行成型过程,直至在完成之前进行附加的工艺步骤。 
可以理解,接合引线210的形成材料和/或尺寸可能会使得接合引线易于损坏。尽管某些材料的电导性是理想的、容易连接和/或容易制造(即展 延性),但是这样的材料可能会容易变形。金是一种普遍用于接合引线的示例性材料。在传感器的应用场合,金线的直径通常在0.9密耳(mil)到1.3密耳的范围内。这样的尺寸适合于进行电连接,但是在极端压力下所施加的成型材料可能会容易移动、弯曲、断裂,或者使得接合引线连接的性能降低。 
本领域的一般技术人员能够使用公知的各种适当环氧成型化合物,来封装着预成型组件,以及第二成型材料204的包覆成型。一种由Hysol公司所生产的化合物MG52F可用于第一和第二成型材料202、204。这种材料的工艺性能类似于磁体材料。封装组件和磁体216的膨胀系数之间应当类似,以使得当各个部件遭受极端温度的操作循环(例如汽车中部件所遇到的各种情况)时不会发生断裂。 
用于第一和第二成型材料202、204的可选化合物是Sumitomo BakeliteCo.Ltd所生产的SUMIKON EME-6600R。在选择合适化合物中的一个因素是使得填充料(filler)的分布是朝向范围的较高侧。例如,尺寸为5-10μm的填充料将会产生相当大的毛刺(flash)和溢出(bleed),而尺寸为30μm或更大尺寸的填充料将几乎消除这个现象。在现有技术中公知的,半导体成型件具有使空气排走的出口,同时容纳着成型化合物。随着富含树脂的材料渗漏,在这些区域中将可以看到细微小的树脂溢出。可由特定的化合物来设计成型件,同时出口被设计成经选择的化合物才被允许经过。 
在选择第一成型材料202时需要考虑的因素是与磁体216的膨胀系数以及毛刺和树脂溢出量之间的类似性,其能够妨碍磁体216和集中器214两者的连接以及第二成型材料204的包覆成型。 
在一个实施例中,第一和第二成型材料202、204使用了相同的材料。在其他的实施例中,第一和第二成型材料不同,以满足特定应用场合的需要。此外,尽管显示和描述了第一和第二成型步骤,但是可以理解还可以使用进一步的成型步骤来施加相同或不同的材料,以保护其他的组件特征,实现特定的几何特征等。 
大体上,在预成型过程(第一成型材料202)和包覆成型过程(第二成型材料204)中的成型配置和固化时间可基于成型材料和成型形状来选择。在一个示例性实施例中,使用0秒的预热时间、5秒的传递时间和120秒的固化时间来进行处理工艺。可使用适当的传递压力和传递时间来封装裸晶 和接合引线,以使得没有明显的最终剩余接合引线偏斜(sway)。可在包覆成型的过程中显著增加传递压力和传递时间,而不会有破坏或移动被粘合的接合引线的风险,其没有预成型就不能实现。由于由磁体尺寸所产生的成型腔的相对较大深度,使得在包覆成型过程中的显著较高传递压力和时间有助于适当使得第二成型材料变得紧凑。 
可以理解,预成型和包覆成型的工艺具有不同的参数。总体而言,预成型(第一成型材料202)使用相对慢的注射速度以及小的初始填充压力,以阻止接合引线被带走。第一成型材料202防护着接合引线和磨具,同时发生用于第二成型材料204的随后包覆成型操作。包覆成型工艺可使用相对高的传递速度和压力,以使得第二成型材料204在磁体的周围避开较深的腔。由于防护着接合引线210和裸晶202的第一成型材料202的存在,使得第二成型材料204不具有较高的压力,从而即使不是不可能、也难以在磁体区域中或其周围消除空隙。通过防止线缆210在随后的处理步骤中受到损坏,增加了产出,以使得IC的生产更有效率。 
一旦完成第一成型材料202的施加,预成型组件被制成使得集中器214和磁体216以本领域一般技术人员公知地方式连接到引线框208的背侧上。在一个示例性实施例中,第一成型材料202仅模制着封装件的前部以保护着裸晶206和引线210,而使得后侧空闲留待进一步处理。在一个示例性实施例中,集中器214和磁体216使用粘结剂连接到后侧上,然后在最终包覆成型之前进行烘热硬化。 
例如,由于接合引线的存在(比如1密耳的金线),第一成型材料202的施加在时间和压力方面受到限制。封装件需要完全地成型而在相对低的压力下不带有空隙,以使得不会移动或者要不然损坏金线。一旦设置第一成型材料202,第二成型材料204可在没有接合引线限制的情况下进行施加,因为接合引线被封装在第一成型材料202中。可在不考虑接合引线的情况下进行各种后处理步骤。 
图3是图2A和2B的最终组件200的立体图,其中第二成型材料204是局部透明的。如图所示,第一成型材料202封装着裸晶/引线框/接合引线的组件。在示例性实施例中,第二成型材料204局部地封装着第一成型材料202。引线280从所述装置处延伸以用于外部连接。 
图4显示了根据本发明示例性实施例、在多步骤成型工艺中用来制造 IC(例如传感器)的示例性步骤顺序。在步骤300,裸晶以本领域一般技术人员公知的方式连接到引线框上。在步骤302,接合引线然后被连接在裸晶和引线指状部的选定位置之间。然后,在步骤304,第一成型材料被用于至少部分地覆盖着接合引线。在一个实施例中,第一成型材料包封着接合引线。 
在步骤306中,第一成型材料固化,直到至少实现临界水平。在可选的步骤308中,通量集中器被紧固到引线框上。在可选的步骤310中,磁体紧固到集中器上。该组件然后在步骤312中由第二成型材料包覆成型,以在最终的封装件中提供IC。可以理解,最终的封装件可以经受额外的处理,以满足一定的所需物理和/或电学规范。 
尽管在此显示和描述的示例性实施例是有关于传感器,特别是具有集中器和/或磁体的传感器,但是可以理解,本发明可应用于IC制造工艺,在其中的组件大体上在引线框和裸晶之间包括接合引线或其他纤细的连接件。此外,可以理解,也能够使用相同或不同的材料来实现多于两个的成型步骤。 
图5例如显示了小型的集成电流传感器410,其具有磁场传感器(在此为霍尔效应传感器412)、载流导体416和磁芯424。导体416包括一些特征来接收霍尔效应传感器412和磁芯424的一部分,以使得这些元件相对于彼此处于固定的位置处。在所示的实施例中,导体416具有第一凹口418a和与第一凹口大致对齐的第二凹口418b。在组装当中,霍尔效应传感器412的至少一部分位于第一凹口418a中。磁芯424大致是C型的,且具有中心区域424a以及从中心区域延伸的一对大致平行的腿部424b、424c。在组装当中,中心区域424a的至少一部分位于导体的第二凹口418b中,以使得每个腿部424b、424c覆盖着霍尔效应传感器412的各个表面的至少一部分。 
如上所述,霍尔效应传感器412设置为集成电路的形式,其包含第二裸晶414,同时接合引线417由第一成型材料固定就位,以形成由第二成型材料所包覆成型的组件。集成的霍尔效应传感器412可设置为不同的封装类型,例如“K”型单列直插式封装件(SIP)。具体的细节描述在US6,781,359,并在此引用。 
尽管主要结合霍尔传感器显示和描述了本发明的示例性实施例,但是可以理解,本发明一般地也可适合于集成电路以及传感器、特别是磁场传 感器,其例如用作霍尔传感器、GMR(巨型磁致电阻,giantmagnetoresistance)、AMR(各向异性的磁致电阻,anisotropicmagnetoresistance)、TMR(穿隧磁致电阻,tunnel magnetoresistance)和MTJ(磁性隧道结,Magnetic tunnel junctions)。 
在描述本发明的示例性实施例之后,本发明的一般技术人员也可以使用包含所述概念的其他实施例。在此所包含的实施例不限于所披露的内容,而仅由所述权利要求书的主旨和范围所限定。在此所引用的所有出版物和文献的全部内容在此引用并包含在其中。 

Claims (7)

1.一种集成电路装置,其包括:
至少一个裸晶,其连接到具有引线指状部的引线框架上;
接合引线,其在至少一个裸晶和引线指状部之间进行连接;
第一成型材料,其在第一压力下注射以防止接合引线发生引线偏斜,用于封装着接合引线并覆盖着至少一个裸晶和引线指状部的至少一部分,其中第一成型材料仅位于引线框架的裸晶侧且包覆成型着连接到至少一个裸晶上的所有接合引线;以及
具有第一侧和第二侧的集中器,其中集中器的第一侧紧固到引线框架的非裸晶侧;
紧固到集中器的第二侧上的磁体;
第二成型材料,其在大于第一压力的第二压力下进行注射,用于对至少一个裸晶、第一成型材料、集中器和磁体进行包覆成型。
2.如权利要求1所述的装置,其中第一成型材料封装着引线框上的至少一个裸晶。
3.如权利要求1所述的装置,其中第一成型材料的膨胀系数与磁体的膨胀系数相兼容。
4.如权利要求1所述的装置,其中第一成型材料和第二成型材料是不同的。
5.如权利要求1所述的装置,其中所述裸晶包括一个或多个磁场传感器。
6.如权利要求5所述的装置,其中所述磁场传感器包括霍尔元件。
7.如权利要求1所述的装置,其中所述接合引线包括金线。 
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US20080237818A1 (en) 2008-10-02
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US8143169B2 (en) 2012-03-27
DE112008000759T5 (de) 2010-02-04
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US7816772B2 (en) 2010-10-19
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