CN101689561B - 高压GaN基异质结晶体管的终止结构和接触结构 - Google Patents

高压GaN基异质结晶体管的终止结构和接触结构 Download PDF

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CN101689561B
CN101689561B CN2008800091342A CN200880009134A CN101689561B CN 101689561 B CN101689561 B CN 101689561B CN 2008800091342 A CN2008800091342 A CN 2008800091342A CN 200880009134 A CN200880009134 A CN 200880009134A CN 101689561 B CN101689561 B CN 101689561B
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迈克尔·墨菲
米兰·波普赫里斯蒂奇
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Abstract

提供了一种半导体器件，该半导体器件包括：衬底；第一有源层，所述第一有源层设置在所述衬底的上方；以及第二有源层，所述第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层和所述第二有源层之间产生二维电子气层。在所述第二有源层上设置的终止层包括InGaN。在所述终止层上设置源极接触、栅极接触和漏极接触。

Description

高压GaN基异质结晶体管的终止结构和接触结构
相关申请的交叉引用
该申请涉及与其同日提交的序列号为No.11/725,760且名为“Cascode Circuit Employing A Depletion-Mode，GaN-Based Fet”的共同待决的美国专利申请，并且通过引用将其内容合并与此。
该申请还涉及与其同日提交的序列号为No.11/725,820且名为“High-Voltage GaN-Based Heterojunction Transistor Structure andMethod of Forming Same”的共同待决的美国专利申请，并且通过引用将其内容合并与此。
技术领域
本发明涉及高压晶体管异质结构，更具体来讲，涉及高压氮化镓(GaN)高电子迁移率晶体管(HEMT)。
背景技术
氮化镓(GaN)提供重要的机会来增强诸如高电子迁移率晶体管(HEMT)的电子器件的性能。HEMT表现得更像传统的场效应晶体管(FET)，并且HEMT器件的制造是基于FET结构的。然而，HEMT需要两个化合物半导体层之间非常精确的晶格匹配异质结。通常，GaNHEMT具有沉积在衬底上的肖特基(Schottky)层和GaN缓冲层，以及沉积在肖特基层上的源极接触、栅极接触和漏极接触。
通过在具有大带隙的AlGaN层和具有较窄带隙的GaN层之间的异质结界面上形成量子阱，GaN基HEMT器件能够将电子迁移率最大化。结果，电子被捕获在量子阱中。通过在未被掺杂的GaN层中的二维电子气来表现所捕获的电子。通过向栅电极施加电压来控制电流量，所述栅电极与半导体肖特基接触，以使得电子沿着源电极和漏电极之间的沟道流动。
随着HEMT的市场持续扩大，仍然期望进行一些改进，以增强诸如击穿电压Vbr和漏电流I的各种操作特性。例如，因为肖特基层通常是金属的并且在HEMT制造过程中和/或HEMT的操作过程中会暴露于空气中，所以仍然需要充分地解决引起的该个问题。由于肖特基层暴露于空气中，因此会在肖特基层的表面上发生诸如氧化的表面反应。这些表面反应会劣化HEMT的性能，并且还会降低钝化处理的效率。钝化处理是指将电介质材料沉积在HEMT表面上，以钝化或填充HEMT表面上的表面陷阱，由此避免由于这些表面陷阱而导致的器件劣化，诸如RF至DC频散。
因此，除了别的因素以外，仍然需要高电压GaN HEMT结构具有能够防止在GaN HEMT操作和制造过程中的表面反应的可再生终止层。
发明内容
根据本发明，提供了一种半导体器件，该半导体器件包括：衬底；第一有源层，所述第一有源层设置在所述衬底的上方；以及第二有源层，所述第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层和所述第二有源层之间产生二维电子气层。在所述第二有源层上设置的终止层包括InGaN。在所述终止层上设置源极接触、栅极接触和漏极接触。
根据本发明的一个方面，所述第一有源层包含III族氮化物半导体材料。所述第一有源层包含GaN。
根据本发明的另一个方面，所述第二有源层包含III族氮化物半导体材料。
根据本发明的另一个方面，所述第二有源层包含AlxGa1-xN，其中0＜X＜1。
根据本发明的另一个方面，所述第二有源层选自由AlGaN、AlInN和AlInGaN组成的组。
根据本发明的另一个方面，在所述衬底和所述第一有源层之间设置成核层。
根据本发明的另一个方面，一种半导体器件包括：衬底；第一有源层，所述第一有源层设置在所述衬底的上方；第二有源层，所述第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层和所述第二有源层之间产生二维电子气层。在所述第二有源层的上方设置终止层。所述终止层选自由掺杂Fe的GaN、掺杂Si的GaN、FeN和SiN组成的组。在所述终止层上设置源极接触、栅极接触和漏极接触。
根据本发明的另一个方面，一种半导体器件包括：衬底；第一有源层，所述第一有源层设置在所述衬底的上方；以及第二有源层，所述第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层和所述第二有源层之间产生二维电子气层。所述第二有源层包括形成在其内的第一凹进部和第二凹进部。在所述第一凹进部和所述第二凹进部中分别设置源和漏极接触。在所述第二有源层的上方设置栅电极。
附图说明
图1示出了高电子迁移率晶体管(HEMT)中结合的氮化镓(GaN)异质结结构的一个实施例。
图2和图3示出了高电子迁移率晶体管(HEMT)中结合的氮化镓(GaN)异质结结构的可供选择的实施例。
具体实施方式
值得注意的是，对于“一个实施例”或“实施例”的任何引用意味着结合实施例描述的具体特征、结构或特性被包括在本发明至少一个实施例中。在说明书中的各个地方中产生的短语“在一个实施例中”不是必需指的都是相同的实施例。另外，可以以多种方式组合各种实施例，从而形成在本文中没有明确示出的额外的实施例。
如图1中所示，本发明涉及高电子迁移率晶体管(HEMT)10中结合的高压氮化镓(GaN)异质结结构。HEMT 10包括衬底12、成核(过渡)层18、GaN缓冲层22、氮化铝镓(AlxGa1-xN；0＜x＜1)肖特基层24和覆盖层或终止层16。另外，HEMT 10包括源极接触27、栅极接触28和漏极接触30。
通常使用外延生长工艺来制造GaN异质结结构10。例如，可以使用反应溅射工艺，在该工艺中，在毗邻衬底设置的金属靶和衬底都处于包括氮和一个或多个掺杂物的气氛中时，从金属靶溢出诸如镓、铝和/或铟的半导体金属组分。可供选择的，可以采用金属有机化学气相沉积(MOCVD)，其中，在将衬底保持在升高的温度，通常在700℃至1100℃左右下的同时，将衬底暴露于包含金属的有机化合物的气氛，以及诸如氨的反应含氮气体和含掺杂物气体中。气体化合物分解并且在衬底302的表面上形成晶体材料膜形式的掺杂的半导体。然后将衬底和生长的膜冷却。作为另外可供选择的，可以使用诸如分子束外延(MBE)或原子层外延的其它外延生长方法。可以采用的另外技术包括，但不限于流量调制有机金属气相外延(FM-OMVPE)、有机金属气相外延(OMVPE)、氢化物外延(HVPE)和物理气相沉积(PVD)。
为了开始生长结构，在衬底12上沉积成核层18。衬底12可以由各种材料形成，所述各种材料包括但不限于蓝宝石或碳化硅(SiC)。成核层18可以是，例如，诸如AlxGa1-xN的富铝层，其中，X在0至1的范围内。成核层18操作用于校正GaN缓冲层22和衬底12之间的晶格不匹配。通常，当一层中的原子的间隔与相邻层中原子之间的间距不匹配时，产生晶格不匹配。由于晶格不匹配，导致相邻层中的原子之间的结合弱，并且相邻层会断裂、分离或者具有大量的晶体缺陷。因此，通过在衬底12的晶体结构和GaN缓冲层22的晶体结构之间产生界面，成核层18操作用于校正GaN缓冲层22和衬底12之间的晶格不匹配。
在沉积了成核层18之后，在成核层18上沉积GaN缓冲层22，并且在GaN缓冲层22上沉积AlxGa1-xN肖特基层24。二维导电沟道26是薄的高迁移率沟道，其将载流子限制在GaN缓冲层22和AlxGa1-xN肖特基层24之间的界面区域。在AlxGa1-xN肖特基层24上沉积覆盖层或终止层16，所述覆盖层或终止层16用于在HEMT 10的制造和操作过程中保护AlxGa1-xN肖特基层24以免其发生诸如氧化的表面反应。因为肖特基层24包含铝，所以如果AlxGa1-xN肖特基层24暴露于空气中并且没有以其它方式受保护，则会发生氧化。
在衬底12上生长了外延层18、22和24以及终止层16之后，通过分别在终止层16上沉积源极接触27、栅极接触28和漏极接触30来完成HEMT 10。接触件27、28和30中的每个是金属接触件。优选地，栅极接触28是诸如，但不限于镍、金的金属材料，并且源极接触27和漏极接触30都是诸如但不限于钛、金或铝的金属材料。
在本发明的一个实施例中，终止层16是形成在AlxGa1-xN肖特基层24上的InGaN层。InGaN层16用于两个目的，第一个目的是用于提供不包含Al的上层，以减少氧化。此外，因为诸如InGaAlN的含铝化合物通常需要较高的生长温度来提供足够的均匀度和光滑度，所以通过使用InGaN材料来替代包含铝的材料，可以简化生长工艺。另外，InGaN层24略微降低了表面的势垒，这样可以减少表面电荷的增多并且降低了结构表面上的漏电流。
在本发明的另一个实施例中，终止层16是包含Al金属的快闪层(flash layer)。利用材料的极短猝发来形成该快闪层。这样将在结构表面上方形成非常薄(例如，材料的1-2个单分子层)但是平的覆盖。该快闪层通常是原位执行的。为了确保形成的是金属Al而不是AlN，不存在当形成AlN时将会存在的反应含氮气体(例如，氨)。可以在高温或低温下形成Al快闪层。在其形成之后，随后可以对Al进行退火，以形成薄的氧化物层。由于Al快闪层非常薄，因此它可以被完全氧化，由此在材料上产生初始的“自然”氧化物，该氧化物随后保护肖特基层24，使其不经受处理过程中通常看到的任何类型的劣化。这可以用作另外的势垒材料，用于降低漏电流并且增大击穿电压，这两者对于HEMT性能都是重要的。快闪层可以包含其它金属，例如镓或者甚至铟，以替代铝。还可以将Ga或In快闪层氧化来在结构上形成均匀的“自然”氧化物。
在本发明的其它实施例中，覆盖层或终止层16可以由其它材料形成，诸如高度掺杂Fe的GaN、掺杂Si的GaN、FeN或SiN。可以是外延、非外延或者甚至无定形的这些层可以用作初始钝化层或者用作额外的势垒材料，用于降低漏电流并且增大击穿电压。例如，向GaN添加Fe导致了可以降低漏电流的材料，这是因为该材料更绝缘并且降低了电子迁移率。
在本发明的其它实施例中，可以在AlxGa1-xN肖特基层24上形成薄AlN层。该层提供了额外的肖特基势垒层，以有助于更有效地调节电荷，由此降低了漏电流并且增大了器件的击穿电压。AlN层还可以用作结构的初始钝化层，这是由于AlN可以容易地被湿法蚀刻，以沉积欧姆接触件。可供选择的，可以氧化AlN层以形成钝化层。
在一些实施例中，终止层16的厚度大致为1至5纳米。因此，电子可以容易地隧穿终止层16。结果，终止层16没有增加栅极接触28和AlxGa1-xN肖特基层24之间的肖特基势垒高度，其中，肖特基势垒高度限定了栅极接触28和AlxGa1-xN肖特基层24的界面上的由电子遭遇的电势能量势垒。另外，终止层16没有影响源极接触27和漏极接触30的形成。
图2示出了本发明的又一个实施例，在该实施例中，欧姆接触件27和28位于AlxGa1-xN肖特基层24中形成的凹进部中。通过根据传统技术蚀刻AlxGa1-xN肖特基层24来形成凹进部。凹进部可以部分或完全地延伸穿过AlxGa1-xN肖特基层24。例如，在一些情况下，凹进部可以延伸到约5nm至15nm深的深度，由此使得AlxGa1-xN肖特基层24能够保持足够的厚度来产生沟道层26。通过以此方式使接触件凹进，降低了表面的接触电阻和光滑度，从而增大了被沉积用于形成欧姆接触件的金属的渗透性。表面粗糙的增加导致金属更好地迁移到半导体中。对于需要低导通电阻的器件来说，该布置在实现最低可能的导通电阻方面会效果显著。虽然没有示出，但是本发明的该实施例还可以采用诸如上述的覆盖层或终止层。在这种情况下，设置有接触件27和28的凹进部也将延伸穿过终止层。
图3示出了本发明的另一个实施例，在该实施例中，势垒层24由代替AlxGa1-xN的AlInGaN形成。例如，如在GAAS99中由M.AsifKhan等人所著的“Strain Energy Band Engineering in AlGaInN/GaNHeterostructure Field Effect Transistors”中所讨论的，采用了AlxInyGa(1-x-y)N结，其势垒厚度小于50nm且合金组分在x等于0.1至0.2而y等于0.00至0.02的范围内变化。另外，Khan等人陈述的是，基于晶格常数的线性插值，为5的Al/In比率应该几乎与GaN晶格匹配。通过使用AlInGaN，可以与带隙无关地控制张力，由此使得材料的带隙能够关于临界厚度更自由地变化。对于功率器件，在没有过度对材料施加应力和缩短器件寿命的情况下，在沟道中得到最多的电荷是至关重要的，其中，当随着时间过去材料驰豫时会产生所述器件寿命的缩短。
虽然本文具体示出和描述了各种实施例，但是应该理解的是，在不脱离本发明的精神和意图范围的情况下，本发明的修改形式和变形形式可以被以上教导覆盖并且在所附权利要求书的范围内。例如，虽然已经将耗散模式FET描述为GaN基器件，但是本发明更通常地包括由任何III族氮化物化合物半导体形成的耗散模式FET，在该半导体中，III族元素可以是镓(Ga)、铝(Al)、硼(B)或铟(In)。

Claims (7)

1.一种半导体器件，包括：
衬底；
设置在所述衬底的上方的第一有源层；
设置在所述第一有源层上的第二有源层，所述第二有源层具有比所述第一有源层高的带隙以使得在所述第一有源层和所述第二有源层之间产生二维电子气层；
设置在所述第二有源层上的终止层，所述终止层选自由氧化铝、氧化镓、氧化铟和FeN组成的组；以及
设置在所述终止层上的源极接触、栅极接触和漏极接触。
2.根据权利要求1所述的半导体器件，其中，所述第一有源层包含III族氮化物半导体材料。
3.根据权利要求2所述的半导体器件，其中，所述第一有源层包含GaN。
4.根据权利要求1所述的半导体器件，其中，所述第二有源层包含III族氮化物半导体材料。
5.根据权利要求4所述的半导体器件，其中，所述第二有源层包含AlxGa1-xN，其中0＜X＜1。
6.根据权利要求4所述的半导体器件，其中，所述第二有源层选自由AlGaN、AlInN和AlInGaN组成的组。
7.根据权利要求1所述的半导体器件，还包括设置在所述衬底和所述第一有源层之间的成核层。
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US20080230785A1 (en) 2008-09-25
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EP2140493A4 (en) 2011-06-22
CN103094336A (zh) 2013-05-08
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