CN101728363A - 晶片封装结构及其制作方法 - Google Patents

晶片封装结构及其制作方法 Download PDF

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CN101728363A
CN101728363A CN200910168157A CN200910168157A CN101728363A CN 101728363 A CN101728363 A CN 101728363A CN 200910168157 A CN200910168157 A CN 200910168157A CN 200910168157 A CN200910168157 A CN 200910168157A CN 101728363 A CN101728363 A CN 101728363A
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chip package
package structure
packing colloid
cut
structure according
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CN101728363B (zh
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高东均
李正
安载善
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Advanced Semiconductor Engineering Inc
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Abstract

本发明涉及一种晶片封装结构及其制作方法，所述晶片封装结构，包括一半导体基板、至少一晶片、一封装胶体以及一遮蔽层。晶片配置于半导体基板上且电性连接至半导体基板。封装胶体配置于半导体基板上，且至少包覆晶片与部分半导体基板。遮蔽层配置于封装胶体上，其中遮蔽层包括多个配置于半导体基板上且环绕晶片的导电连接结构。导电连接结构以环状方式围绕晶片配置，且晶片与导电连接结构相互分离。遮蔽层通过导电连接结构电性连接至半导体基板。本发明提供的晶片封装结构，具有提升电磁干扰屏蔽性能，本发明提供的晶片封装结构的制作方法，具有较佳的设计灵活性。

Description

晶片封装结构及其制作方法
技术领域
本发明涉及一种半导体装置，尤其涉及一种晶片封装结构及其制作方法。
背景技术
电磁干扰(electro-magnetic interference)对于大多数的电子产品或系统而言是一严肃且富有挑战性的问题。由于电磁干扰常中断、阻碍、降低或限制电子装置或整体电路系统的性能表现，因此需要有效的电磁干扰屏蔽，以确保电子装置或系统的效率与安全操作。
电磁干扰屏蔽的性能对于小尺寸、高密度的封装体或应用于高频率的敏感电子仪器非常重要。一般而言，大都是通过增加金属板与/或导电性的垫圈来提升电磁干扰屏蔽的性能，但此方式会提高制造成本。
发明内容
本发明提供一种晶片封装结构的制作方法，可提供较佳的设计灵活性。
本发明提供一种晶片封装结构，具有提升电磁干扰屏蔽的性能。
本发明提供的晶片封装结构，其包括一基板、至少一晶片配置于基板上、一封装胶体以及一具有多个导电连接结构的遮蔽层。配置于基板上的导电连接结构排列于封装胶体内且环绕晶片配置。遮蔽层配置于封装胶体上，以覆盖封装胶体的上表面。遮蔽层通过导电连接结构电性连接至半导体基板。
在本发明的一实施例中，上述的导电连接结构可为间柱(stud)或镀通孔结构(plated via structure)，暴露出封装胶体的侧壁或不暴露出封装胶体的侧壁。
在本发明的一实施例中，上述的晶片通过多个凸块与晶片封装结构的积层基板电性连接。
在本发明的一实施例中，上述的封装胶体的侧壁为倾斜面。
本发明提供的晶片封装结构的制作方法。首先，提供一具有多个基板单元的阵列基板，至少一晶片配置于一阵列基板的一基板单元上，且晶片电性连接至基板单元。接着，形成一封装胶体于阵列基板上，以覆盖晶片与部分基板单元。接着，进行一标记制程以移除部分封装胶体至暴露出每一基板单元的一上表面，而形成多个通孔或多个沟渠。之后，形成一遮蔽层于封装胶体上以覆盖封装胶体，同时形成多个导电连接结构于通孔内，以覆盖每一基板单元被暴露出的上表面。进行一单体化制程，以形成多个晶片封装结构。
在本发明的一实施例中，上述的导电连接结构可排列于阵列基板的切割线上与每一基板单元的多条边界线上，因此单体化制程时会切穿导电连接结构与阵列基板。当然，导电连接结构也可排列环绕每一基板单元的边界线且与边界线保持一间隔距离，因此单体化制程时不会切穿导电连接结构。
在本发明的一实施例中，上述的遮蔽层与导电连接结构的形成方式是由一金属材料且利用包括喷涂法(spraying process)、溅镀法(sputteringprocess)或电镀法(plating process)所形成。
在本发明的一实施例中，可依据完全填满或部分的填充通孔，在形成遮蔽层的同时形成多个间柱或多个镀通孔结构。
在本发明的一实施例中，上述的标记制程包括一雷射挖空制程(laserdigging process)或一雷射钻孔制程(laser drilling process)。
基于上述，遮蔽层与间柱配置于基板上的作用可视为晶片封装结构的电磁干扰屏蔽。在本发明之中，通过具有弹性且多种设计型态的遮蔽层与间柱，可改善制程的空间。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并结合附图作详细说明如下。
附图说明
图1A至图1F’为本发明的一实施例的一种晶片封装结构的制作方法的示意图。
图2为本发明的一实施例的一种晶片封装结构的剖面示意图。
图3为本发明的另一实施例的一种晶片封装结构的剖面示意图。
图4为本发明的又一实施例的一种晶片封装结构的剖面示意图。
图5为本发明的再一实施例的一种晶片封装结构的剖面示意图。
图6A至图6B’为本发明的一较佳实施例的一种晶片封装结构的制作方法的部分步骤的示意图。
图7为本发明的一实施例的一种晶片封装结构的立体示意图。
图8为本发明的另一实施例的一种晶片封装结构的立体示意图。
主要元件符号说明：
20b、40b：侧表面；              100、600：阵列基板；
102、602：基板单元；            102a、602a：上表面；
104：接点；                     106：凸块；
108：接地孔；                   120、620：晶片；
130、630：封装胶体；            130a、630a：上表面；
130b、630b：侧壁；              135：通孔；
135a：侧壁；                    142：间柱；
142a：半间柱；                  144：镀通孔结构；
144a：半镀通孔结构；            635：沟渠；
635a：侧壁；                    642：环状填充结构；
644：中空环状结构；             644a：半中空环状结构；
θ：倾斜角；                    d：间隔距离；
140、140’、640、640’：遮蔽层；
10、20、30、40、50、70、80：晶片封装结构。
具体实施方式
本发明所述的晶片封装结构的制作方法可用来制作多种封装结构，其中以制作堆迭式封装体、多层封装体或具有高频率装置的封装体(包括具有射频装置的封装体)最为适合。此外，本发明的晶片封装结构的制作方法与利用积层基板的制作方法或阵列基板的制作方法的封装制程相互符合。
图1A至图1F’为本发明的一实施例的一种晶片封装结构的制作方法的示意图。在此必须说明的是，为了方便说明起见，图1D’与图1D”所示为立体示意图，图1A至图1D、图1E至图1F与图1E’至图1F’所示为剖面示意图。
请先参考图1A，提供一阵列基板100。阵列基板100具有多个基板单元102(是由后面所示出的为虚线的切割线所定义)，其中每一基板单元102上包括多个接点104。这些接点104的作用与覆晶接合技术中的凸块焊垫的作用相同。阵列基板100可为一积层基板，例如可以是一印刷电路板(PrintedCircuit Board；简称为：PCB)。
接着，请参考图1B，至少一晶片120配置于每一基板单元102的上表面102a上。虽然本实施例是提供晶片120配置于每一基板单元102的上表面102a上，但在其他实施例中，也可以是提供多个表面黏着型元件贴附于每一基板单元102的上表面102a上，这种方式也属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。晶片120通过多个凸块106电性连接至基板单元102的这些接点104，其中这些凸块106介于晶片120与这些接点104之间。虽然本实施例是以覆晶接合技术作为说明，但于其他实施例中，也包括利用打线接合技术来电性连接晶片120与这些接点104，仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。较佳地，晶片120配置于基板单元102的中心部。
接着，请参考图1C，通过一封胶制程而形成一封装胶体130于阵列基板100上，以包覆晶片120、这些接点104、这些凸块106与至少一部分的基板单元102。封胶制程例如可以为一阵列封胶制程(over-molding process)。封装胶体130的材料例如可以是环氧树脂(epoxy resins)或硅氧树脂(silicon resins)。
接着，请参考图1D，进行一标记制程以移除部分封装胶体130至暴露出基板单元102的上表面102a，而形成多个通孔135。这些通孔135环绕晶片120排列。较佳地，这些通孔135排列于晶片120与每一基板单元102的边界或周围之间。图1D’所示为图1D的结构的立体示意图。请同时参考图1D与图1D’，这些个别独立的通孔135排列于基板单元102的边界线(虚线)上。在本实施例中，后续的切割制程会沿着这些切割线(图示为虚线)而切穿这些通孔135。标记制程例如可以是一雷射挖空制程或一雷射钻孔制程。此外，通过上述的雷射制程所形成的这些通孔135具有高准确度的直径与可控制的渐缩部(taper)。较佳地，这些通孔135的渐缩部具有一倾斜角θ(介于通孔135的侧壁135a与基板单元102的上表面102a之间)，且此倾斜角θ的范围介于60度至90度之间。以这些通孔135环绕排列于每一基板单元102的边界为例，标记制程可通过钻多个彼此相互分离的孔而移除部分的封装胶体130，其中这些孔在封装胶体130内呈环状排列，且位于每一基板单元102的边界线上。
在其他实施例中，这些通孔135也可以排列靠近且位于基板单元102的这些边界线(虚线)内，但不位于基板单元102的这些边界线上，请参考图1D”。这些通孔135可环绕晶片120配置且靠近基板单元102的这些边界线。举例说明，这些通孔135可排列成环形框状图案(ring-shaped pattern)且与基板单元102的边界线相距一小间隔距离d，且间隔距离d可依据产品的需求而自由调整。此外，后续的切割制程虽然会沿着这些切割线但不会切穿这些通孔135。一般而言，这些通孔135的尺寸或形状可依照屏蔽的需要、封装体电性的特性，或甚至是依据制程的参数而自由调整。
接者，请参考图1E，形成一遮蔽层140于封装胶体130上，以覆盖封装胶体130的上表面130a与基板单元102的上表面102a(指基板单元102被这些通孔135所暴露出的上表面102a)，以及填满这些通孔135。遮蔽层140的形成方式是利用喷涂法、电镀法或溅镀法，使一金属材料(未示出)覆盖封装胶体130及填满这些通孔135。遮蔽层140的材料例如可以是铝、铜、铬、金、银、镍、焊料或上述材料的化合物。间柱142可在形成遮蔽层140的过程经由填满这些通孔135而形成。
最后，请参考图1F，进行一单体化制程，以形成多个独立的晶片封装结构10。单体化制程例如可以是一刀片切割制程。请同时参考图1E与图1F，单体化制程切穿这些间柱142与阵列基板100，以形成多个个别独立且分别具有多个半间柱(semi-studs)142a的晶片封装结构10。
当然，在其他实施例中，请参考图1E’，遮蔽层140’也可以形成在封装胶体130上，以覆盖封装胶体130的上表面130a且共形地(conformally)覆盖这些通孔135的侧壁135a，并暴露出基板单元102的上表面102a，而形成多个镀通孔结构(plated via structure)144。在此实施例中，遮蔽层140’的形成方式是利用喷涂法、电镀法或溅镀法，使一金属材料(未示出)覆盖封装胶体130而不填满这些通孔135。依据通孔135的形状与尺寸，镀通孔结构144的形状可为一杯状或一倒置帽子形状(inverted cap)。接着，请参考图1F’，进行一单体化制程以切穿阵列基板100与这些镀通孔结构144，而形成多个个别独立且分别具有多个半镀通孔结构(semi-plated viasstructure)144a的晶片封装结构10。单体化制程例如可以是一刀片切割制程。
图2为本发明的一实施例的一种晶片封装结构的剖面示意图。请参考图2，在本实施例中，晶片封装结构20包括一基板单元102、多个接点104、多个凸块106、至少一晶片120、一封装胶体130与一遮蔽层140。基板单元102可为一积层基板，例如可以是一两层或一四层积层的印刷电路板基板。晶片120可为一半导体晶片，例如可以是一射频(Radio Frequency；简称为：RF)晶片。遮蔽层140的材质可为铜、铬、金、银、镍、铝或上述材料的合金，甚至是一焊料。晶片120通过接点(凸块焊垫)104与凸块106电性连接至基板单元102。封装胶体130包覆部分基板单元102、凸块106与晶片120。遮蔽层140包括多个半间柱142a。在此所述的半间柱142a是指图1F所示出的切割后的间柱，但在上下文中可将其视为间柱。这些间柱142的形状或结构与这些通孔135的位置排列有关，如这些间柱142是由填满这些通孔135所形成，请参考图1E。请再参考图2，遮蔽层140配置于封装胶体130上，以覆盖封装胶体130的上表面130a，其中半间柱142a覆盖基板102被暴露出的上表面102a。单体化制程会切穿这些间柱142与封装胶体130(切穿这些切割线)，请参考图1F，部分封装胶体130与这些半间柱142a暴露于晶片封装结构20的侧表面20b。遮蔽层140通过这些半间柱142a与至少一基板102的接地孔108而电性连接至基板102，而遮蔽层140通过这些半间柱142a与接地孔108而接地。因此，可利用基板表面的金属线路或走线作为一接地平面，使本实施例的遮蔽层140可通过基板的接地平面而接地于封装结构内。
图3为本发明的另一实施例的一种晶片封装结构的剖面示意图。请参考图3，遮蔽层140配置于封装胶体130上且覆盖封装胶体130的上表面130a。遮蔽层140也包括多个间柱142，其中这些间柱142配置于基板单元102上且位于封装胶体130内，并覆盖基板单元102被暴露出的上表面102a。基本上，晶片封装结构30是依据图1D”(而不是图1D)的制作方法所形成，且切割制程虽是沿着切割线的方向来进行，但并没有切穿这些间柱142。事实上，这些间柱142可视为多个填充的通孔结构，且图3的这些间柱142是环绕晶片120排列且位于晶片120与基板单元102的这些边界线之间。因此，暴露出封装胶体130的这些侧壁130b，但这些间柱142未暴露于晶片封装结构30的侧表面外。
图4为本发明的又一实施例的一种晶片封装结构的剖面示意图。请参考图4，在本实施例中，晶片封装结构40是依据图1D、图1E’与图1F’的制作方法所形成，且遮蔽层140’包括多个半镀通孔结构144a。在此所述的半镀通孔结构144a是指图1F’所示出的切割后的镀通孔结构，但在上下文中可将其视为镀通孔结构。这些半镀通孔结构144a的形状或结构与这些通孔135的位置排列有关，如这些半镀通孔结构144a形成作为这些通孔135的共形涂层(conformal coatings)，请参考图1E’。请再参考图4，遮蔽层140’覆盖封装胶体130的上表面130a，且半镀通孔结构144a覆盖基板单元102被暴露出的上表面102a。单体化制程会切穿这些这些镀通孔结构144与封装胶体130(切穿这些切割线)，请参考图1F’，部分封装胶体130与这些半镀通孔结构144a暴露于晶片封装结构40的侧表面40b外。遮蔽层140’通过这些半镀通孔结构144a与至少一基板单元102的接地孔108而电性连接至基板单元102，而遮蔽层140’通过这些半镀通孔结构144a与接地孔108而接地。
图5为本发明的再一实施例的一种晶片封装结构的剖面示意图。请参考图5，在本实施例中，晶片封装结构50是依据图1D”与图1E’的制作方法所形成，且遮蔽层140’包括多个镀通孔结构144。当切割制程没切穿排列邻近于切割线的这些镀通孔结构144时，暴露出封装胶体130的侧壁130b，但镀通孔结构144未暴露于晶片封装结构50的侧表面外。
简而言之，间柱(半间柱或未切割的间柱)或镀通孔结构(切割的镀通孔结构或未切割的镀通孔结构)可视为上遮蔽层的金属连接结构。遮蔽层是通过间柱(半间柱或未切割的间柱)或镀通孔结构(切割的镀通孔结构或未切割的镀通孔结构)而物理性与/或电性连接至下方的基板。
图1A至图1F’的晶片封装结构的制作方法在符合本发明的情况下，可以更进一步地被修改与描述于以下的具体实施例中。
接着图1A至图1C的步骤后，请参考图6A，进行一标记制程以移除部分封装胶体630至暴露出阵列基板600的基板单元602的上表面602a，而形成多个沟渠(trench)635。这些沟渠635环绕晶片620排列。较佳地，每一沟渠635为一环状沟渠且排列于晶片620与每一基板单元602的边界或周围之间。图6A’为图6A的结构的立体示意图。请参考图6A与图6A’，这些个别独立的沟渠635排列于基板单元602的边界线(虚线)上。在某方面而言，通过标记制程所形成的这些沟渠635可视为一格子(grid)或格子状(latticed)的图案。在本实施例中，后续的切割制程会沿着这些切割线(图示为虚线)而切穿这些沟渠635。标记制程例如可以是一雷射挖空制程或一雷射钻孔制程。此外，通过上述的雷射制程所形成的这些沟渠635具有高准确度的直径与可控制的渐缩部(taper)。较佳地，这些沟渠635的渐缩部具有一倾斜角θ(介于侧壁635a与基板单元602的上表面602a之间)，且此倾斜角θ的范围介于60度至90度之间。以这些沟渠635环绕排列于每一基板单元602的边界为例，标记制程可通过钻多个环状沟渠而移除部份的封装胶体630，其中这些环状沟渠位于封装胶体630内，且位于每一基板单元602的边界线上。
在其他实施例中，这些沟渠635也可以排列靠近于基板单元602的这些边界线(虚线)内，但不位于基板单元602的这些边界线上，请参考图6A”。这些沟渠635配置邻近基板单元602的这些边界线。此外，后续的切割制程虽然会沿着这些切割线但不会切穿这些沟渠635。一般而言，这些沟渠635的尺寸或形状可依照屏蔽的需要、封装体电性的特性，或甚至是依据制程的参数而自由调整。
类似图1E的步骤，一遮蔽层640形成于封装胶体630上，以覆盖封装胶体630的上表面630a且填满这些沟渠635，并覆盖基板单元602被暴露出的上表面602a(被这些沟渠635所暴露出的基板单元602的上表面602a)，而形成环形填充结构642，请参考图6B。在其他实施例中，类似图1E’的步骤，遮蔽层640’也可以形成于封装胶体630上，以覆盖封装胶体630的上表面630a以及共形地覆盖这些沟渠635的侧壁635a与基板单元602被暴露出的上表面602a，而形成多个中空环状结构644，请参考图6B’。
最后，接续着图1F或图1F’的步骤，进行单体化制程，以形成多个独立的晶片封装结构。
图7为本发明的一实施例的一种晶片封装结构的立体示意图。请参考图7，在本实施例中，晶片封装结构70是依据图1A至图1C、图6A与图6B’的制作方法所形成，且遮蔽层640’包括多个切割的半中空环状结构644a。请参考图6B’与图7，遮蔽层640’覆盖封装胶体630的上表面630a，同时，切割的(或半)中空环状结构644覆盖封装胶体630的侧壁635a。当进行切割制程切穿中空环状结构644(切穿切割线)时，只有切割的半中空环状结构644a被暴露于晶片封装结构70的侧表面外。遮蔽层640’通过切割的中空环状结构644与至少一基板单元602的接地孔108而电性连接至基板单元602，而遮蔽层640’通过这些半中空环状结构644a与接地孔108而接地。
图8为本发明的另一实施例的一种晶片封装结构的立体示意图。请参考图8，在本实施例中，晶片封装结构80是依据图1A至图1C、图6A”与图6B的制作方法所形成。遮蔽层640覆盖封装胶体630的上表面630a且包括多个环状填充结构642。当切割制程没切穿排列邻近于切割线的这些环状填充结构642时，暴露出封装胶体630的侧壁630b，但环状填充结构642未暴露于晶片封装结构80的侧表面外。
简言之，实心的环状结构(切割的环状结构或未切割的环状结构)或中空环状结构(切割的中空环状结构或未切割的中空环状结构)可视为上遮蔽层的金属连接结构。遮蔽层是通过实心的环状结构(切割的环状结构或未切割的环状结构)或中空环状结构(切割的中空环状结构或未切割的中空环状结构)而物理性与/或电性连接至下方的基板。
在本实施例的晶片封装结构中，遮蔽层与导电连接结构配置于基板上的作用可视为一电磁干扰屏蔽，用以保护晶片封装结构免于周围辐射源的电磁干扰辐射。
在本发明中，由于通孔的形状与位置可通过标记制程而精准地控制，因此晶片封装结构的电磁干扰屏蔽设计可依照产品的需要而自由调整。此外，当遮蔽层包括排列于封装胶体内的导电连接结构时，可提高电磁干扰屏蔽的性能。
综上所述，由于遮蔽层与导电连接结构可有效地遮蔽外界电磁干扰辐射，因此可提高本发明的晶片封装结构的电磁干扰屏蔽的性能。此外，本发明的晶片封装结构的制作方法，是于封装结构内设立一接地路径，而不是利用一额外的金属板来作为接地平面。因此，这样的设计适合具有高频装置的封装，特别是一射频装置。
最后应说明的是：以上实施例仅用以说明本发明的技术方案而非对其进行限制，尽管参照较佳实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对本发明的技术方案进行修改或者等同替换，而这些修改或者等同替换亦不能使修改后的技术方案脱离本发明技术方案的精神和范围。

Claims (23)

1.一种晶片封装结构，其特征在于，包括：
一半导体基板；
至少一晶片，配置于所述半导体基板上且电性连接至所述半导体基板；
一封装胶体，配置于所述半导体基板上，且至少包覆所述晶片与部分所述半导体基板；以及
一遮蔽层，配置于所述封装胶体上，其中所述遮蔽层包括多个配置于所述半导体基板上且环绕所述晶片的导电连接结构，多个所述导电连接结构以环状方式围绕所述晶片配置，且所述晶片与多个所述导电连接结构相互分离，所述遮蔽层通过多个所述导电连接结构电性连接至所述半导体基板。
2.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个彼此相互分离的金属间柱，且暴露于所述封装胶体的多个侧壁外。
3.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个彼此相互分离的金属间柱，位于所述封装胶体内且未暴露于所述封装胶体的多个侧壁外。
4.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个彼此相互分离的镀通孔结构，且暴露于所述封装胶体的多个侧壁外。
5.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个彼此相互分离的镀通孔结构，位于所述封装胶体内且未暴露于所述封装胶体的多个侧壁外。
6.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个实心的环状结构且未暴露于所述封装胶体的多个侧壁外。
7.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构为多个中空环状结构且未暴露于所述封装胶体的多个侧壁外。
8.根据权利要求1所述的晶片封装结构，其特征在于，其中多个所述导电连接结构完全地覆盖所述封装胶体的多个侧壁。
9.根据权利要求8所述的晶片封装结构，其特征在于，其中所述封装胶体的多个所述侧壁为倾斜面。
10.根据权利要求1所述的晶片封装结构，其特征在于，其中所述遮蔽层通过多个所述导电连接结构与所述半导体基板的至少一接地孔而电性连接至所述半导体基板。
11.一种晶片封装结构的制作方法，其特征在于，包括：
提供一阵列基板，所述阵列基板具有多个基板单元，其中每一所述基板单元是由多条切割线所定义；
配置至少一晶片于每一所述基板单元上，其中所述晶片电性连接至所述基板单元；
形成一封装胶体于所述阵列基板上，以包覆所述晶片；
进行一标记制程以移除部分所述封装胶体至暴露出每一所述基板单元的一上表面，以形成多个通孔或多个沟渠于所述封装胶体内；
形成一遮蔽层于所述封装胶体上以覆盖所述封装胶体，同时形成多个导电连接结构，以覆盖所述多个通孔或所述多个沟渠且覆盖每一所述基板单元被暴露出的所述上表面；以及
进行一单体化制程，以形成多个晶片封装结构。
12.根据权利要求11所述的晶片封装结构的制作方法，其特征在于，其中多个所述导电连接结构为填满所述多个通孔所形成的多个间柱。
13.根据权利要求12所述的晶片封装结构的制作方法，其特征在于，其中所述多个间柱排列于所述阵列基板的所述多条切割线上与每一所述基板单元的多条边界线上，且所述单体化制程切穿所述多个间柱与所述阵列基板。
14.根据权利要求12所述的晶片封装结构的制作方法，其特征在于，其中所述多个间柱配置于每一所述基板单元的多条边界线与所述晶片之间，且所述单体化制程切穿所述阵列基板但未切穿所述多个间柱。
15.根据权利要求11所述的晶片封装结构的制作方法，其特征在于，其中所述多个导电连接结构为部分地填充所述多个通孔所形成的多个镀通孔结构。
16.根据权利要求15所述的晶片封装结构的制作方法，其特征在于，其中所述多个镀通孔结构排列于所述阵列基板的所述多条切割线上与每一所述基板单元的多条边界线上，且所述单体化制程切穿所述多个镀通孔结构与所述阵列基板。
17.根据权利要求15所述的晶片封装结构的制作方法，其特征在于，其中所述多个镀通孔结构配置于所述晶片与每一所述基板单元的多条边界线之间，且所述单体化制程切穿所述阵列基板但未切穿所述多个镀通孔结构。
18.根据权利要求11所述的晶片封装结构的制作方法，其特征在于，其中所述多个导电连接结构为填满所述多个沟渠所形成的多个环状结构。
19.根据权利要求18所述的晶片封装结构的制作方法，其特征在于，其中所述多个环状结构排列于所述阵列基板的所述多条切割线上与每一所述基板单元的多条边界线上，且所述单体化制程切穿所述多个环状结构与所述阵列基板。
20.根据权利要求18所述的晶片封装结构的制作方法，其特征在于，其中所述多个环状结构配置于所述晶片与每一所述基板单元的多条边界线之间，且所述单体化制程切穿所述阵列基板但未切穿所述多个环状结构。
21.根据权利要求11所述的晶片封装结构的制作方法，其特征在于，其中所述多个导电连接结构为部分地填充所述多个沟渠所形成的多个中空环状结构。
22.根据权利要求21所述的晶片封装结构的制作方法，其特征在于，其中所述多个中空环状结构排列于所述阵列基板的所述多条切割线上与每一所述基板单元的多条边界线上，且所述单体化制程切穿所述多个中空环状结构与所述阵列基板。
23.根据权利要求21所述的晶片封装结构的制作方法，其特征在于，其中所述多个中空环状结构配置于所述晶片与每一所述基板单元的多条边界线之间，且所述单体化制程切穿所述阵列基板但未切穿所述多个中空环状结构。
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