CN101807909B - Buffer applying to driving circuit and driving method applying to load device - Google Patents
Buffer applying to driving circuit and driving method applying to load device Download PDFInfo
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- CN101807909B CN101807909B CN2009100043716A CN200910004371A CN101807909B CN 101807909 B CN101807909 B CN 101807909B CN 2009100043716 A CN2009100043716 A CN 2009100043716A CN 200910004371 A CN200910004371 A CN 200910004371A CN 101807909 B CN101807909 B CN 101807909B
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- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 230000001276 controlling effect Effects 0.000 claims abstract description 20
- 230000001105 regulatory effect Effects 0.000 claims abstract description 13
- 230000005669 field effect Effects 0.000 claims description 67
- 239000004065 semiconductor Substances 0.000 claims description 67
- 230000004913 activation Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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Abstract
The invention relates to a buffer applying to a driving circuit and a driving method applying to a load device. The buffer applying to the driving circuit comprises a first transistor, a second transistor and a conversion rate control circuit, wherein the first transistor is used for supplying current to an output end, and the second transistor is used for drawing current from the output end; and the conversion rate control circuit is used for controlling the conversion rate of at least one of the first transistor and the second transistor according to input signals, and a regulating and controlling circuit is used for preventing the first transistor and the second transistor from conducting simultaneously.
Description
Technical field
The present invention relates to a kind of drive circuit buffer and method thereof, refer to an a kind of drive circuit buffer and method thereof that is used to provide the conversion rate control circuit of suitable driving force that comprises especially.
Background technology
Generally speaking, drive circuit comprises buffer as its afterbody, is used to provide suitable driving force and drives the load that is coupled in this buffer.Yet; Load value can change along with various structure, material and input signal, and the output signal of this buffer can change along with different loads, therefore; If the output signal of this buffer must meet standards; As the standard of the industry processor interface (MIPI) of taking action (for instance, its switching rate (slew rate) can not surpass a predetermined value), just then the output signal of this buffer can not have no restrictedly along with load variations.
Summary of the invention
Therefore, one of the object of the invention is to provide a kind of drive circuit buffer, and it can provide a suitable output signal under the situation that does not receive the load variations influence.
One embodiment of the invention provide a kind of buffer that is used for drive circuit.This buffer comprises the first transistor, transistor seconds and conversion rate control circuit.This first transistor is in order to provide current to output.This transistor seconds is then in order to draw electric current from this output.This conversion rate control circuit is in order to controlling the switching rate of at least one control signal in a plurality of control signals according to this input signal, with the conducting of controlling this first transistor and this transistor seconds or by operation.This circuit for regulating and controlling is in order to prevent the conducting simultaneously of this first transistor and this transistor seconds.
Another embodiment of the present invention provides a kind of driving method that is used for load device.This driving method comprises: the first transistor (a) is provided, in order to provide current to output; (b) transistor seconds is provided, in order to draw electric current from this output; (c) according to this input signal control this first transistor and this transistor seconds at least one of them switching rate input to this load device to produce the output signal;
And (d) prevent the conducting simultaneously of this first transistor and this transistor seconds.
According to the above, therefore the switching rate of this output signal can be provided an output signal with appropriate conversion speed by control well.
Description of drawings
Fig. 1 is the circuit diagram of the buffer of drive circuit in one embodiment of the invention;
Fig. 2 is the circuit diagram of the detailed structure embodiment of the buffer in the drive circuit shown in Fig. 1;
Fig. 3 is the sketch map of signal relation among the embodiment shown in Figure 2;
Fig. 4 is the circuit diagram of another detailed structure embodiment of buffer in the drive circuit shown in Fig. 1.
Embodiment
In the middle of specification and follow-up claims, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This specification and follow-up claims are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be an open term mentioned " comprising " in the middle of specification and follow-up claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device through other devices or the intersegmental ground connection of connection hand if describe first device in the literary composition.
Fig. 1 is the circuit diagram of the buffer 100 of the drive circuit in one embodiment of the invention.As shown in Figure 1, buffer 100 comprises the first transistor 101, transistor seconds 103, conversion rate control circuit 105 and circuit for regulating and controlling 107.The first transistor 101 is in order to provide electric current I 1 to output 109, and transistor seconds 103 is then in order to draw electric current I 2 from output 109.In this example, load device (not being shown among the figure) is coupled to output 109, and thus, output 109 provides load current to this load device.Conversion rate control circuit 105 is controlled the wherein switching rate of at least one control signal of a plurality of control signal CS1 and CS2 according to input signal In, with the conducting of control the first transistor 101 and transistor seconds 103 or by operation.Note that input signal In can obtain from circuit for regulating and controlling 107 or other sources, it depends on the structure of circuit for regulating and controlling 107.
In this embodiment; If transistor 101 and 103 conductings simultaneously; A big electric current will flow to earthing potential from predetermined potential Vcc, and thus, the first transistor 101 and transistor seconds 103 may be therefore impaired; Therefore, circuit for regulating and controlling 107 is just in order to prevent the first transistor 101 and transistor seconds 103 conductings simultaneously.In this embodiment; The first transistor 101 is P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) (Metal Oxide Semiconductor Field Effect Transistor; MOSFET), its source-coupled is to predetermined potential, and transistor seconds 103 is a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor); The drain electrode of its drain coupled to the first transistor 101, its source-coupled is to earthing potential.
Fig. 2 is the circuit diagram of the detailed structure embodiment of buffer in the drive circuit shown in Fig. 1.Note that structure shown in Figure 2 only as the usefulness of example explanation, is not to be used for limiting to category of the present invention.In this embodiment; Conversion rate control circuit 105 is a delay circuit; It comprises a plurality of resistance 201,203 and a plurality of electric capacity 205,207, makes can be postponed to control the wherein switching rate of at least one control signal of a plurality of control signal InP and InN (that is the control signal CS1 shown in Fig. 1 and CS2) in view of the above from the input signal In of circuit for regulating and controlling 107.In addition, the circuit for regulating and controlling in the present embodiment 107 comprises a plurality of inverter 209,211, P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 and N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215.Inverter 209 is in order to producing anti-phase primary signal IOS with primary signal OS anti-phase, inverter 211 then in order to anti-phase primary signal IOS anti-phase to produce input signal In.The drain electrode of P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 is coupled to the grid of P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 101, and in addition, the source electrode of P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 is coupled to specific potential, and its grid then receives anti-phase primary signal IOS.The drain electrode of N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215 is coupled to the grid of N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 103, and in addition, the source electrode of N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215 is coupled to earthing potential, and its grid then receives anti-phase primary signal IOS.
Fig. 3 is the sketch map of signal relation among the embodiment shown in Figure 2.Please be simultaneously with reference to Fig. 2 and Fig. 3 so that can be well understood to technical characterictic of the present invention more.As shown in Figure 3; Primary signal OS is produced anti-phase primary signal IOS by inverter 209 anti-phases; So anti-phase primary signal IOS has an anti-phase in the phase place of primary signal OS; And anti-phase primary signal IOS is then produced input signal In by anti-phase once more, and therefore, input signal In just has the phase place identical with primary signal OS.Next, conversion rate control circuit 105 delay input signal In come to produce respectively control signal InP and InN to transistor 101 and 103.As shown in Figure 3, control signal InP and InN have a plurality of delay section X1, X2 and Y1, Y2 respectively. Transistor 101 and 103 is controlled by control signal InP and InN, and therefore, output signal OUT just produces according to the operation of transistor 101 and 103.
As shown in Figure 3, the switching rate of section Z1, Z2 is the switching rate of respective segments X1, Y1 respectively; Likewise, the switching rate of section Z3, Z4 is also distinguished the switching rate of respective segments X2, Y2.Therefore, through the switching rate of control control signal InP and InN, the just controlled switching rate that makes output signal OUT.Yet note that conversion rate control circuit 105 is not limited to realize that with delay circuit (for example RC circuit) other circuit that can reach identical function also belong to category of the present invention.For control signal InP and InN; The solid line of period K1～K4 and dotted line show the voltage curve that has P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 and N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215 and do not have P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 and N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215 respectively; As shown in Figure 3; Rising and the fall off rate that clearly can find out solid line are all faster than dotted line; Therefore, P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) can help transistor 101,103 conduction and cut-off more apace really.
In addition specifically; P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 is all controlled by anti-phase primary signal IOS with N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215; And anti-phase primary signal IOS is not postponed by conversion rate control circuit 105; Therefore, P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 213 can more early be switched on/end with N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 215 than transistor 101,103.So the voltage of end points X and Y can be promoted to Vcc apace or reduce to earthing potential, transistor 101,103 can be closed apace, can prevent just that therefore transistor 101,103 is by conducting simultaneously.
Fig. 4 is the circuit diagram of another detailed structure embodiment of the buffer in the drive circuit shown in Fig. 1.Do comparison with embodiment shown in Figure 2, conversion rate control circuit 401 comprises N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 403 and P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 405, is used for replacing resistance and electric capacity.Those skilled in the art can recognize easily that according to the pairing size of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) can reach the function of RC delay circuit originally equally, so this RC delay circuit just can be replaced.In one embodiment, N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 403 and P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) are to have the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) of long channel length to replace this RC delay circuit.
That is to say that N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 403 and P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 405 can be controlled the switching rate of end points X and Y through adjusting its size.For instance, N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 403 can be used for controlling the signal rate of climb of end points X, so can produce the rising edge of output signal OUT.In addition, P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 405 can be used for controlling the signal decrease speed of end points Y, so can produce the drop edge of output signal OUT.In addition; Buffer 400 shown in Figure 4 also comprises enable circuit 407, in order to activation (enable) or deenergize (disable) conversion rate control circuit 401 and control circuit (it includes P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 409, N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) 411 and inverter 413,415).In this example, enable circuit 407 comprise enable signal generator 417, inverter 419, a plurality of switching device 421,423 or non-(NOR) door 425 and with non-(NAND) door 427.
In addition; In order to provide high capacity enough driving forces; The MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) type of Fig. 1 and transistor 101,103 shown in Figure 2 or transistor 402,404 shown in Figure 4 can be carried out suitable selecting for use, so that these transistors can provide big electric current.In one embodiment, Fig. 1 and transistor 101,103 transistor 402,404 perhaps shown in Figure 4 shown in Figure 2 are the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) of long channel width.As is known to the person skilled in the art; The electric current of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) be directly proportional with its channel width-over-length ratio (W/L) (shown in a current equation formula: Id=1/2u Cox (W/L) (Vgs-Vt)/2); Therefore; The channel width-over-length ratio of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is big more, and bigger electric current and switching rate just can be provided.
In sum, therefore the switching rate of output signal can just can be provided an output signal with appropriate conversion speed by control well.In addition, even when the output signal is used for a high capacity, because used the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) of long channel width or long channel length, the output signal also is not easy to be affected.
The above is merely the preferred embodiments of the present invention, and all equalizations of making according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (2)
1. buffer that is applied to drive circuit comprises:
The first transistor is in order to provide current to output;
Transistor seconds is coupled to this first transistor, in order to draw electric current from this output;
The conversion rate control circuit; Be coupled to this first transistor, this transistor seconds and input signal; In order to controlling the switching rate of at least one control signal in a plurality of control signals according to this input signal, with the conducting of controlling this first transistor and this transistor seconds or by operation;
Circuit for regulating and controlling is coupled to this first transistor and this transistor seconds, in order to prevent the conducting simultaneously of this first transistor and this transistor seconds; And
Enable circuit, in order to activation or deenergize this conversion rate control circuit and this circuit for regulating and controlling,
Wherein this first transistor is a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to predetermined potential; This transistor seconds is a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its drain electrode is coupled to the drain electrode of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential,
Wherein this circuit for regulating and controlling comprises:
First inverter is in order to produce the anti-phase primary signal with the primary signal anti-phase;
Second inverter is in order to produce this input signal with this anti-phase primary signal anti-phase;
The 2nd P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to specific potential, and its grid is in order to receive this anti-phase primary signal; And
The 2nd N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential, and its grid is in order to receiving this anti-phase primary signal,
Wherein this enable circuit comprises:
The enable signal generator is in order to produce enable signal;
The 3rd inverter is coupled to this enable signal generator, in order to produce the anti-phase enable signal;
At least one switching device is coupled to this conversion rate control circuit and this enable signal generator, in order to operate according to this enable signal;
NOR gate, in order to receive this anti-phase primary signal and this anti-phase enable signal, this NOR gate has the grid that output is coupled to the 2nd P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor); And
NAND gate, in order to receive this anti-phase primary signal and this enable signal, this NAND gate has the grid that output is coupled to the 2nd N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor),
And wherein this conversion rate control circuit comprises:
The 3rd N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential; And
The 3rd P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to a predetermined potential.
2. driving method that is applied to load device comprises:
(a) the first transistor is provided, in order to provide current to output;
(b) transistor seconds is provided, in order to draw electric current from this output;
(c) control in this first transistor and this transistor seconds switching rate of one of them at least according to input signal, input to this load device to produce the output signal; And
(d) prevent the conducting simultaneously of this first transistor and this transistor seconds,
Wherein this first transistor is a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to predetermined potential; This transistor seconds is a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its drain electrode is coupled to the drain electrode of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential,
Wherein step (d) is used circuit for regulating and controlling, and it comprises:
First inverter is in order to produce the anti-phase primary signal with the primary signal anti-phase;
Second inverter is in order to produce this input signal with this anti-phase primary signal anti-phase;
The 2nd P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to specific potential, and its grid is in order to receive this anti-phase primary signal; And
The 2nd N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential, and its grid is in order to receiving this anti-phase primary signal,
And wherein step (c) is used the conversion rate control circuit, and it comprises:
The 3rd N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to earthing potential; And
The 3rd P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), its drain electrode is coupled to the grid of a N type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and its source electrode is coupled to predetermined potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100043716A CN101807909B (en) | 2009-02-12 | 2009-02-12 | Buffer applying to driving circuit and driving method applying to load device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100043716A CN101807909B (en) | 2009-02-12 | 2009-02-12 | Buffer applying to driving circuit and driving method applying to load device |
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| Publication Number | Publication Date |
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| CN101807909A CN101807909A (en) | 2010-08-18 |
| CN101807909B true CN101807909B (en) | 2012-07-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009100043716A Expired - Fee Related CN101807909B (en) | 2009-02-12 | 2009-02-12 | Buffer applying to driving circuit and driving method applying to load device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117081577A (en) * | 2023-10-13 | 2023-11-17 | 禹创半导体(深圳)有限公司 | Power DDI architecture applied to 3D printing technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633600A (en) * | 1994-09-29 | 1997-05-27 | Nec Corporation | Output buffer circuit having a minimized output voltage propagation |
| US6169421B1 (en) * | 1999-05-03 | 2001-01-02 | Applied Micro Circuits Corporation | Complementary metal-oxide semiconductor buffer |
| CN1496002A (en) * | 2002-07-15 | 2004-05-12 | 株式会社瑞萨科技 | Semiconductor device with complementary metal oxide semiconductor drive circuit |
| CN101101736A (en) * | 2006-07-06 | 2008-01-09 | 奇景光电股份有限公司 | Output circuit in a driving circuit and driving method of a display device |
-
2009
- 2009-02-12 CN CN2009100043716A patent/CN101807909B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633600A (en) * | 1994-09-29 | 1997-05-27 | Nec Corporation | Output buffer circuit having a minimized output voltage propagation |
| US6169421B1 (en) * | 1999-05-03 | 2001-01-02 | Applied Micro Circuits Corporation | Complementary metal-oxide semiconductor buffer |
| CN1496002A (en) * | 2002-07-15 | 2004-05-12 | 株式会社瑞萨科技 | Semiconductor device with complementary metal oxide semiconductor drive circuit |
| CN101101736A (en) * | 2006-07-06 | 2008-01-09 | 奇景光电股份有限公司 | Output circuit in a driving circuit and driving method of a display device |
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