CN101859734B - 导线架及其制造方法与封装结构的制造方法 - Google Patents
导线架及其制造方法与封装结构的制造方法 Download PDFInfo
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- CN101859734B CN101859734B CN201010107079XA CN201010107079A CN101859734B CN 101859734 B CN101859734 B CN 101859734B CN 201010107079X A CN201010107079X A CN 201010107079XA CN 201010107079 A CN201010107079 A CN 201010107079A CN 101859734 B CN101859734 B CN 101859734B
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
本发明公开了一种导线架及其制造方法与封装结构的制造方法,该制造方法包括在进行背侧蚀刻工艺以定义出多个接触端子之前先进行预切割工艺。预切割工艺可确保个别的接触端子之间彼此独立并可提升封装体的可靠度。
Description
技术领域
本发明涉及一种导线架及其制作方法与封装结构及其制造方法,且特别是涉及一种先进四方扁平无引脚(advanced quad flat non-leaded,a-QFN)封装结构的制造方法,以及先进四方扁平无引脚封装结构的导线架及其制作方法。
背景技术
根据导线架(leadframe)的引脚(lead)的形状,四方扁平封装(quad flatpackage,QFP)可以分为I型(QFI)、J型(QFJ)与无引脚型(QFN)封装。其中,四方扁平无引脚封装具有减少引脚电感、脚位面积(footprint)小、厚度小且信号传输速度快等优点。因此,四方扁平无引脚封装为一种普遍的封装结构且适于用来作为高频(例如射频频宽(radio frequency bandwidth))传输的芯片封装。
就四方扁平无引脚封装结构而言,是利用平面型的导线架基板来制作芯片垫与其周围的接触端子(contact terminal),即引脚垫(lead pad)。一般来说,是通过表面粘着技术(surface mounting technology,SMT)将四方扁平无引脚封装结构焊接至印刷电路板。因此,四方扁平无引脚封装结构的芯片垫或是接触端子/接垫必须符合封装工艺的能力以增加接点的可靠度。
发明内容
本发明提供一种先进四方扁平无引脚封装的制作方法,其可确保引脚接触端彼此绝缘且可增加产品的可靠度。
本发明提出一种先进四方扁平无引脚封装结构的制作方法如下所述。首先,提供金属载板,金属载板具有上表面与下表面,且金属载板的上表面配置有第一金属层,金属载板的下表面配置有第二金属层,并以第一金属层为掩模进行第一蚀刻工艺图案化金属载板的上表面,以形成至少一容置凹槽与多个第一开口,以及通过预切割工艺图案化金属载板的下表面,以形成多个预切割开口。接着,提供芯片至金属载板的容置凹槽中。然后,形成多个连接于芯片与第一金属层之间的导线。之后,在金属载板上形成封装胶体,以包覆芯片、导线与第一金属层,并填满容置凹槽与第一开口。接着,以位于金属载板的下表面的第二金属层为掩模,对金属载板的下表面进行第二蚀刻工艺,以通过蚀刻预切割开口以及更蚀穿金属载板直到填在第一开口中的封装胶体暴露出来的方式形成多个第二开口,从而形成多个引脚与芯片垫。
在本发明的实施例中,可在形成封装胶体之后,进行预切割工艺。
根据前述实施例,预切割工艺可为激光切割工艺、刀切工艺或电弧切割工艺。由于预切割工艺可确保第二蚀刻工艺可完全蚀穿剩下的基板以绝缘并定义出接触端子(引脚)及芯片垫。因此,利用预切割工艺可加宽第二蚀刻工艺的工艺窗并可减少残留金属的问题,进而提升产品的可靠度。
本发明提出一种导线架的制作方法如下所述。首先,提供金属载板,金属载板具有上表面与下表面。接着,在金属载板的上表面与下表面上分别形成第一金属层与第二金属层,且第二金属层具有多个开口。然后,以第一金属层为蚀刻掩模,对金属载板的上表面进行蚀刻工艺,以形成至少一容置凹槽与多个内引脚,多个位于内引脚之间的第一开口定义出内引脚。之后,通过开口对金属载板的下表面进行预切割工艺,以形成多个预切割开口。
本发明提出一种导线架,包括金属载板,其具有上表面与下表面,且金属载板的上表面配置有第一金属层,金属载板的下表面配置有第二金属层,第二金属层具有多个开口,其中金属载板的上表面包括至少一容置凹槽与多个第一开口,且金属载板的下表面包括多个预切割开口。
根据本发明的多个实施例,预切开口的底部是平坦的或是U形。预切开口的深度约为基板厚度的0.2倍~0.4倍。预切开口的宽度约为开口的宽度的50%~100%。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1A~图1I绘示本发明实施例的先进四方扁平无引脚封装的工艺剖面图。
图1E’与图1E”分别绘示图1E的先进四方扁平无引脚封装结构的示例性的部分的放大剖面图与放大立体图。
图2绘示本发明实施例的先进四方扁平无引脚封装结构的剖面图。
附图标记说明
10、20:先进四方扁平无引脚封装结构
100、200:承载器
110:基板
110a:上表面
110b:下表面
114a:第一图案化光致抗蚀剂层
114b:第二图案化光致抗蚀剂层
115a:第一金属部
115b:第二金属部
116a:第一金属层
116b:第二金属层
117a:第三金属部
117b:第四金属部
120、220:芯片垫
120a:容置凹槽
122:中心部
124、224:周边部、接地环
130、230:内引脚
136、236:外引脚
138、238:引脚或接触端子
140:粘着层
150、250:芯片
160、260:导线
180、280:封装胶体
D:厚度
d:深度
S1:第一开口
S2:第二开口
Sc:预切割开口
w、W:宽度
具体实施方式
图1A~图1I绘示本发明实施例的先进四方扁平无引脚封装结构的工艺剖面图。
如图1A所示,提供基板110,其具有上表面110a与下表面110b。举例来说,基板110可为金属承载片。基板110的材料例如为铜、铜合金或是其他适合的金属材料。之后,再次参照图1A,在基板110的上表面110a上形成第一图案化光致抗蚀剂层114a,并在基板110的下表面110b上形成第二图案化光致抗蚀剂层114b。
之后,请参照图1B,以第一/第二图案化光致抗蚀剂层114a/114b为掩模,在基板110的上表面110a的被第一图案化光致抗蚀剂层114a所暴露出的部分上形成第一金属层116a,并在基板110的下表面110b的被第二图案化光致抗蚀剂层114b所暴露出的部分上形成第二金属层116b。在本实施例中,例如是以电镀的方式形成第一金属层116a与第二金属层116b。根据第一图案化光致抗蚀剂层114a与第二图案化光致抗蚀剂层114b的图案设计,第一与第二金属层116a/116b可具有多组不相连的图案或是连续层。第一金属层116a例如为镍/金层。
如图1B所示,第一金属层116a包括多个第一金属部115a与至少一第二金属部115b。第一金属部115a之后将会形成内引脚130(如图1D所示),第二金属部115b之后将会形成芯片垫120的接地环124(如图1H所示)。相同地,第二金属层116b包括多个第三金属部117a与至少一第四金属部117b。第三金属部117a对应于之后将形成的内引脚130,且第四金属部117b对应于之后将形成的芯片垫120。
之后,请参照图1C,移除第一光致抗蚀剂层114a。然后,以第一金属层116a为蚀刻掩模对基板110的上表面110a进行第一蚀刻工艺,以移除部分的基板110并形成至少一容置凹槽120a与多个第一开口S1。第一蚀刻工艺例如为湿式蚀刻工艺(wet etching process)。由于第一蚀刻工艺为各向同性蚀刻工艺(isotropic etching process),因此,底切(undercut)容易发生在第一金属层116a下。第一开口S1定义出多个独立的内引脚130。在形成第一金属层116a、第二金属层116b与图案化基板110之后,已初步形成承载器100。容置凹槽120a具有中心部122与环绕中心部122的周边部124。内引脚130环绕并分离于周边部124。内引脚130的排列方式可以是成行、成列或是阵列排列。周边部124之后可作为接地环(ground ring)。
因此,如图1D所示,进行水刀工艺(water-jet process)以切除或移除第一金属层116a的位于底切部分的正上方的部分。
图1E’与图1E”分别绘示图1E的先进四方扁平无引脚封装的示例性的部分的放大剖面图与放大立体图。然后,请参照图1E与图1E’,对基板100的下表面110b进行预切割工艺(pre-cutting process),以于基板110中形成多个预切割开口(pre-cut opening)Sc。预切割开口Sc位于第二金属层116b的第三金属部117a与第四金属部117b之间,并对应于第一开口S1。宽度w例如是小于或约略等于(约50%至100%的)距离W,距离W为第二金属层116b的金属部之间的间距。举例来说,预切割开口Sc的深度d约30~50微米,预切割开口Sc的深度d约为基板110的厚度D的0.2倍~0.4倍。详细而言,如图1E”所绘示的基板110的底视图,预切割开口Sc可为浅环状沟槽,浅环状沟槽围绕或包围第二金属层116b的第三金属部117a与第四金属部117b。为清楚介绍,放大图中的相对尺寸较为夸大,但并非用以限定本发明。预切割开口的深度或形状可根据之后工艺的工艺参数而做调整。预切割工艺例如为激光切割工艺(laser cutting process)、刀切工艺(bladecutting process)或电弧切割工艺(electric arc cutting process)。随着使用不同的预切割工艺,预切割开口Sc的底部的形状亦随的不同。举例来说,对于以刀切工艺形成的预切割开口Sc而言,预切割开口Sc的底部可以是平坦的(如图1E’所示)。然而,对于以激光切割工艺或电弧切割工艺所形成的预切割开口Sc而言,预切割开口Sc的底部可以是U形(如图1E’所示)。
之后,请参照图1F,将至少一芯片150粘着至各容置凹槽120a的中心部122,其中粘着层140配置于芯片150与中心部122之间。然后,多条导线160连接于芯片150与接地环124以及内引脚130之间。换言之,芯片150通过导线160连接至接地环124与内引脚130。
接着,请参照图1G,形成封装胶体180以包覆芯片150、导线160、内引脚130、接地环124以及填满容置凹槽120a以及第一开口S1。另外,在其他实施例中,可在形成封装胶体之后进行预切割工艺,而非紧接在第一蚀刻工艺之后进行。
然后,请参照图1H,以第二金属层116b为蚀刻掩模,对承载器100的下表面110b进行第二蚀刻工艺以移除部分的基板110,并蚀穿基板110而暴露出填于第一开口S1中的封装胶体180且同时形成多个第二开口S2。由于以第二金属层116b为蚀刻掩模,第二开口S2的宽度相同于第二金属层116b的金属部之间的宽度(或间距)W。第二蚀刻工艺例如为湿式蚀刻工艺。因为预切割开口Sc位于第三金属部117a与第四金属部117b之间,第二蚀刻工艺是从基板110的预切割开口Sc进行蚀刻且进一步地蚀刻基板110直到基板110被蚀穿为止。在此,第二蚀刻工艺将预切割开口Sc扩大为第二开口S2。第二开口S2定义出多个外引脚136且使内引脚130彼此电性绝缘。换言之,在第二蚀刻工艺之后,形成多个引脚或接触端子138,各引脚或接触端子138包括内引脚130与对应的外引脚136。此外,第二蚀刻工艺更定义出承载器100的至少一芯片垫120。引脚138围绕芯片垫120,且芯片垫120通过第二开口S2电性绝缘于引脚138。一般而言,引脚138通过前述蚀刻工艺而彼此电性绝缘。举例来说,预切割开口Sc的深度与第二开口S2的深度的比约介于3∶8至1∶2之间。
假如基板在第二蚀刻工艺中并未被完全蚀穿或是可能残留的铜或是金属碎屑皆有可能导致接触短路或是其他的电性问题。然而,预切割工艺有助于减少残留的问题。由于预切割工艺在第二蚀刻工艺之前切入基板110预定深度,故可减少第二蚀刻工艺的蚀刻深度。换言之,预切割开口Sc可使第二蚀刻工艺的蚀穿基板110的蚀刻深度减少。这样,可确保第二蚀刻工艺可完全移除基板110的位于引脚138之间的部分,如此一来,引脚138可物理上的以及电性上的彼此独立。
之后,请参照图1I,进行切单工艺(singulation process),以得到多个独立的先进四方扁平无引脚封装结构10。
详细而言,在本实施例中,预切割开口Sc可确保基板110在第二蚀刻工艺中被蚀穿且在第二蚀刻工艺之后引脚可彼此电性绝缘。因此,可加大工艺窗并可显著提升产品的可靠度。对于本实施例的先进四方扁平无引脚封装结构10而言,可减少于接触端子(或引脚)138之间的铜残留问题并提升封装产品的可靠度。
图2绘示本发明实施例的先进四方扁平无引脚封装结构的剖面图。请参照图2,在本实施例中,先进四方扁平无引脚封装结构20包括承载器200、芯片250、多条导线260与封装胶体280。
本实施例的承载器200例如为导线架。详细而言,承载器200包括芯片垫220与多个引脚(接触端子)238。引脚238包括多个内引脚230与多个外引脚236。图2绘示了多行/多列的接触端子238。详细而言,引脚238围绕着芯片垫220,且引脚238的材料可包括镍、金或钯(palladium)。封装胶体定义出内引脚与外引脚,也就是说,被封装胶体包覆的引脚是内引脚,而被封装胶体暴露出的引脚是外引脚。
再者,承载器200的芯片垫220还包括至少一接地环224。接地环224通过导线260电性连接至芯片250。由于接地环224连接芯片垫220,故接地环224与芯片垫220可作为接地平面。值得注意的是,相对于图2中的接地环224与芯片垫220,引脚238的位置、排列与数量仅用来举例而并非用以限定本发明。
此外,本实施例的先进四方扁平无引脚封装结构20的封装胶体280包覆芯片250、导线260、内引脚230并填满内引脚230之间的间隙,而暴露出外引脚236与芯片垫220的底面。封装胶体280的材料例如为环氧树脂或是其他适合的高分子材料。
对于前述实施例的先进四方扁平无引脚封装结构而言,是通过预切割工艺与蚀刻工艺制作外引脚,且之后的蚀刻工艺定义出外引脚,并使外引脚彼此独立。本实施例的先进四方扁平无引脚封装结构的产品可靠度较佳。
虽然本发明已以实施例披露如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视所附的权利要求所界定为准。
Claims (11)
1.一种四方扁平无引脚封装结构的制作方法,包括:
提供金属载板,该金属载板具有上表面与下表面,且该金属载板的该上表面配置有第一金属层,该金属载板的该下表面配置有第二金属层,并以该第一金属层为掩模进行第一蚀刻工艺图案化该金属载板的该上表面,以形成至少一容置凹槽与多个第一开口,以及通过预切割工艺图案化该金属载板的该下表面,以形成多个预切割开口;
提供芯片至该金属载板的该容置凹槽中;
形成多条连接于该芯片与该第一金属层之间的导线;
于该金属载板上形成封装胶体,以包覆该芯片、该多条导线与该第一金属层,并填满该容置凹槽与该多个第一开口;以及
以位于该金属载板的该下表面的该第二金属层为掩模,对该金属载板的该下表面进行第二蚀刻工艺,以通过蚀刻该多个预切割开口以及更蚀穿该金属载板直到填在该多个第一开口中的该封装胶体暴露出来的方式形成多个第二开口,从而形成多个引脚与芯片垫。
2.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该第二蚀刻工艺为各向同性蚀刻工艺,且该第一蚀刻工艺为各向同性蚀刻工艺。
3.如权利要求2所述的四方扁平无引脚封装结构的制作方法,还包括:
在第一蚀刻工艺之后,对该金属载板的该上表面进行水刀工艺。
4.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该预切割工艺为激光切割工艺、刀切工艺或电弧切割工艺。
5.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该预切割开口的底部是平坦的或是U形的。
6.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该预切割开口的深度为该金属载板的厚度的0.2倍至0.4倍。
7.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该预切割开口的宽度为该多个第二开口的宽度的50%至100%。
8.如权利要求1所述的四方扁平无引脚封装结构的制作方法,其中该第一金属层与该第二金属层的形成方法包括电镀。
9.如权利要求1所述的四方扁平无引脚封装结构的制作方法,还包括:
在提供该芯片之前,在该容置凹槽中形成粘着层。
10.一种导线架的制作方法,包括:
提供金属载板,该金属载板具有上表面与下表面;
在该金属载板的该上表面与该下表面上分别形成第一金属层与第二金属层,且该第二金属层具有多个开口;
以该第一金属层为蚀刻掩模,对该金属载板的该上表面进行蚀刻工艺,以形成至少一容置凹槽与多个内引脚,多个位于该多个内引脚之间的第一开口定义出该多个内引脚,其中该蚀刻工艺为各向同性蚀刻工艺;
在该蚀刻工艺之后,对该金属载板的该上表面进行水刀工艺;以及
通过该多个开口对该金属载板的该下表面进行预切割工艺,以形成多个预切割开口。
11.一种导线架的制作方法,包括:
提供金属载板,该金属载板具有上表面与下表面;
在该金属载板的该上表面与该下表面上分别形成第一金属层与第二金属层,且该第二金属层具有多个开口;
以该第一金属层为蚀刻掩模,对该金属载板的该上表面进行蚀刻工艺,以形成至少一容置凹槽与多个内引脚,多个位于该多个内引脚之间的第一开口定义出该多个内引脚;以及
通过该多个开口对该金属载板的该下表面进行预切割工艺,以形成多个预切割开口,其中该预切割工艺为激光切割工艺、刀切工艺或电弧切割工艺。
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Families Citing this family (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8492883B2 (en) | 2008-03-14 | 2013-07-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a cavity structure |
US20110042794A1 (en) * | 2008-05-19 | 2011-02-24 | Tung-Hsien Hsieh | Qfn semiconductor package and circuit board structure adapted for the same |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8357998B2 (en) * | 2009-02-09 | 2013-01-22 | Advanced Semiconductor Engineering, Inc. | Wirebonded semiconductor package |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US8502357B2 (en) * | 2009-10-01 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with shaped lead and method of manufacture thereof |
US8241965B2 (en) * | 2009-10-01 | 2012-08-14 | Stats Chippac Ltd. | Integrated circuit packaging system with pad connection and method of manufacture thereof |
US8749074B2 (en) * | 2009-11-30 | 2014-06-10 | Micron Technology, Inc. | Package including an interposer having at least one topological feature |
US20110140253A1 (en) * | 2009-12-14 | 2011-06-16 | National Semiconductor Corporation | Dap ground bond enhancement |
TWI479580B (zh) * | 2010-03-12 | 2015-04-01 | 矽品精密工業股份有限公司 | 四方平面無導腳半導體封裝件及其製法 |
TWM393039U (en) * | 2010-04-29 | 2010-11-21 | Kun Yuan Technology Co Ltd | Wire holder capable of reinforcing sealing connection and packaging structure thereof |
CN102270619B (zh) * | 2010-06-04 | 2014-03-19 | 马维尔国际贸易有限公司 | 用于电子封装组件的焊盘配置 |
US20110316163A1 (en) * | 2010-06-24 | 2011-12-29 | Byung Tai Do | Integrated circuit packaging system with molded interconnects and method of manufacture thereof |
US8669654B2 (en) * | 2010-08-03 | 2014-03-11 | Stats Chippac Ltd. | Integrated circuit packaging system with die paddle and method of manufacture thereof |
US8476772B2 (en) | 2010-09-09 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die |
US8304277B2 (en) * | 2010-09-09 | 2012-11-06 | Stats Chippac, Ltd. | Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking |
TWI420630B (zh) * | 2010-09-14 | 2013-12-21 | Advanced Semiconductor Eng | 半導體封裝結構與半導體封裝製程 |
TWI464852B (zh) * | 2010-11-03 | 2014-12-11 | Mediatek Inc | 四方扁平無引腳封裝及適用於四方扁平無引腳封裝之線路板 |
US20120119342A1 (en) * | 2010-11-11 | 2012-05-17 | Mediatek Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US20120140427A1 (en) * | 2010-12-01 | 2012-06-07 | Mediatek Inc. | Printed circuit board (pcb) assembly with advanced quad flat no-lead (a-qfn) package |
US8338924B2 (en) * | 2010-12-09 | 2012-12-25 | Qpl Limited | Substrate for integrated circuit package with selective exposure of bonding compound and method of making thereof |
TWI455213B (zh) * | 2010-12-15 | 2014-10-01 | Chipmos Technologies Inc | 無外引腳封裝結構及其製作方法 |
US8426254B2 (en) * | 2010-12-30 | 2013-04-23 | Stmicroelectronics, Inc. | Leadless semiconductor package with routable leads, and method of manufacture |
US20120168920A1 (en) | 2010-12-30 | 2012-07-05 | Stmicroelectronics, Inc. | Leadless semiconductor package and method of manufacture |
KR101774004B1 (ko) | 2011-03-17 | 2017-09-01 | 해성디에스 주식회사 | 반도체 패키지 제조방법 |
US8604596B2 (en) * | 2011-03-24 | 2013-12-10 | Stats Chippac Ltd. | Integrated circuit packaging system with locking interconnects and method of manufacture thereof |
US8367475B2 (en) | 2011-03-25 | 2013-02-05 | Broadcom Corporation | Chip scale package assembly in reconstitution panel process format |
TW201241970A (en) * | 2011-04-08 | 2012-10-16 | Advanced Semiconductor Eng | Semiconductor package with recesses in the edged leadas |
CN102184908A (zh) * | 2011-04-26 | 2011-09-14 | 日月光半导体制造股份有限公司 | 进阶式四方扁平无引脚封装结构及其制作方法 |
TWI460796B (zh) * | 2011-07-25 | 2014-11-11 | Advanced Semiconductor Eng | 具有保護層的半導體封裝及其製作方法 |
US8749035B2 (en) * | 2011-08-11 | 2014-06-10 | Eoplex Limited | Lead carrier with multi-material print formed package components |
US8513787B2 (en) * | 2011-08-16 | 2013-08-20 | Advanced Analogic Technologies, Incorporated | Multi-die semiconductor package with one or more embedded die pads |
US10522452B2 (en) | 2011-10-18 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates |
CN102403282B (zh) * | 2011-11-22 | 2013-08-28 | 江苏长电科技股份有限公司 | 有基岛四面无引脚封装结构及其制造方法 |
CN102376656B (zh) * | 2011-11-28 | 2013-11-27 | 江苏长电科技股份有限公司 | 无基岛四面无引脚封装结构及其制造方法 |
TWI462255B (zh) * | 2012-02-29 | 2014-11-21 | 矽品精密工業股份有限公司 | 封裝結構、基板結構及其製法 |
CN102629599B (zh) * | 2012-04-06 | 2014-09-03 | 天水华天科技股份有限公司 | 四边扁平无引脚封装件及其生产方法 |
US8937376B2 (en) * | 2012-04-16 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with heat dissipation structures and related methods |
CN102738015A (zh) * | 2012-06-05 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于腐蚀、喷砂的aaqfn产品的二次塑封制作工艺 |
TWI459517B (zh) * | 2012-06-14 | 2014-11-01 | 矽品精密工業股份有限公司 | 封裝基板暨半導體封裝件及其製法 |
CN102738010A (zh) * | 2012-06-15 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于喷砂的aaqfn框架产品扁平封装件制作工艺 |
US8927345B2 (en) * | 2012-07-09 | 2015-01-06 | Freescale Semiconductor, Inc. | Device package with rigid interconnect structure connecting die and substrate and method thereof |
US9324584B2 (en) * | 2012-12-14 | 2016-04-26 | Stats Chippac Ltd. | Integrated circuit packaging system with transferable trace lead frame |
JP6138496B2 (ja) * | 2013-01-18 | 2017-05-31 | Shマテリアル株式会社 | 半導体素子搭載用基板及び半導体装置 |
US10345343B2 (en) | 2013-03-15 | 2019-07-09 | Allegro Microsystems, Llc | Current sensor isolation |
US9190606B2 (en) * | 2013-03-15 | 2015-11-17 | Allegro Micosystems, LLC | Packaging for an electronic device |
TWI502657B (zh) * | 2013-04-18 | 2015-10-01 | 矽品精密工業股份有限公司 | 半導體封裝件之製法 |
TWI480995B (zh) * | 2013-06-21 | 2015-04-11 | 矽品精密工業股份有限公司 | 四方扁平無接腳封裝件及其製法 |
US9368423B2 (en) * | 2013-06-28 | 2016-06-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package |
US8937379B1 (en) | 2013-07-03 | 2015-01-20 | Stats Chippac Ltd. | Integrated circuit packaging system with trenched leadframe and method of manufacture thereof |
CN103413766B (zh) * | 2013-08-06 | 2016-08-10 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法 |
CN103400771B (zh) * | 2013-08-06 | 2016-06-29 | 江阴芯智联电子科技有限公司 | 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法 |
CN103456645B (zh) * | 2013-08-06 | 2016-06-01 | 江阴芯智联电子科技有限公司 | 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法 |
KR101538543B1 (ko) * | 2013-08-13 | 2015-07-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
GB201318911D0 (en) * | 2013-10-25 | 2013-12-11 | Litecool Ltd | LED Package |
US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
CN105023988B (zh) * | 2014-04-25 | 2018-03-13 | 日月光半导体制造股份有限公司 | 发光半导体封装及相关方法 |
CN103985677B (zh) * | 2014-06-11 | 2016-09-07 | 扬州江新电子有限公司 | 超薄塑封半导体元器件框架、元器件及其制备方法 |
US9219025B1 (en) * | 2014-08-15 | 2015-12-22 | Infineon Technologies Ag | Molded flip-clip semiconductor package |
KR101563909B1 (ko) | 2014-08-19 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 패키지 온 패키지 제조 방법 |
JP6453625B2 (ja) * | 2014-11-27 | 2019-01-16 | 新光電気工業株式会社 | 配線基板及びその製造方法と電子部品装置 |
US9570381B2 (en) | 2015-04-02 | 2017-02-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and related manufacturing methods |
CN205282448U (zh) * | 2015-05-28 | 2016-06-01 | 意法半导体股份有限公司 | 表面安装类型半导体器件 |
US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
JP6539928B2 (ja) * | 2015-12-14 | 2019-07-10 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及びその製造方法 |
JP2017162876A (ja) * | 2016-03-07 | 2017-09-14 | 株式会社ジェイデバイス | 半導体パッケージの製造方法 |
CN108780785A (zh) | 2016-03-30 | 2018-11-09 | 英特尔公司 | 混合微电子基底 |
US10141197B2 (en) * | 2016-03-30 | 2018-11-27 | Stmicroelectronics S.R.L. | Thermosonically bonded connection for flip chip packages |
CN105789072B (zh) * | 2016-05-04 | 2018-06-08 | 天水华天科技股份有限公司 | 一种面阵列无引脚csp封装件及其制造方法 |
CN106129021B (zh) * | 2016-07-17 | 2018-07-13 | 东莞文殊电子科技有限公司 | 一种叠层集成电路封装结构及其制造方法 |
JP2018046057A (ja) * | 2016-09-12 | 2018-03-22 | 株式会社東芝 | 半導体パッケージ |
JP6761738B2 (ja) * | 2016-11-15 | 2020-09-30 | 新光電気工業株式会社 | リードフレーム及びその製造方法、電子部品装置の製造方法 |
CN106409785A (zh) * | 2016-11-30 | 2017-02-15 | 天水华天科技股份有限公司 | 一种薄型阵列塑料封装件及其生产方法 |
TWI604585B (zh) * | 2016-12-23 | 2017-11-01 | 恆勁科技股份有限公司 | 基板結構的製造方法 |
US9972558B1 (en) * | 2017-04-04 | 2018-05-15 | Stmicroelectronics, Inc. | Leadframe package with side solder ball contact and method of manufacturing |
US10529672B2 (en) * | 2017-08-31 | 2020-01-07 | Stmicroelectronics, Inc. | Package with interlocking leads and manufacturing the same |
US10361148B1 (en) * | 2018-03-30 | 2019-07-23 | Semiconductor Components Industries, Llc | Leadframe with efficient heat dissipation for semiconductor device package assembly |
US20210212214A1 (en) * | 2018-05-23 | 2021-07-08 | Sumitomo Bakelite Co., Ltd. | Method of manufacturing circuit board |
CN109037083A (zh) * | 2018-07-27 | 2018-12-18 | 星科金朋半导体(江阴)有限公司 | 一种qfn指纹识别芯片的封装方法 |
CN109037084A (zh) * | 2018-07-27 | 2018-12-18 | 星科金朋半导体(江阴)有限公司 | 一种qfn指纹识别芯片的封装方法 |
CN109256367B (zh) * | 2018-10-24 | 2024-03-22 | 嘉盛半导体(苏州)有限公司 | 预塑封引线框架、半导体封装结构及其单元、封装方法 |
US11398417B2 (en) | 2018-10-30 | 2022-07-26 | Stmicroelectronics, Inc. | Semiconductor package having die pad with cooling fins |
JP7304145B2 (ja) * | 2018-11-07 | 2023-07-06 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
CN110323141B (zh) * | 2019-04-15 | 2021-10-12 | 矽力杰半导体技术(杭州)有限公司 | 引线框架结构,芯片封装结构及其制造方法 |
US10756054B1 (en) * | 2019-07-24 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
CN112309873B (zh) * | 2019-07-26 | 2023-11-10 | 江苏长电科技股份有限公司 | 电磁屏蔽封装结构及其封装方法 |
US11916090B2 (en) * | 2020-07-01 | 2024-02-27 | Stmicroelectronics, Inc. | Tapeless leadframe package with exposed integrated circuit die |
US11569179B2 (en) * | 2020-11-19 | 2023-01-31 | Advanced Semiconductor Engineering, Inc. | Package structure including an outer lead portion and an inner lead portion and method for manufacturing package structure |
US11768230B1 (en) | 2022-03-30 | 2023-09-26 | Allegro Microsystems, Llc | Current sensor integrated circuit with a dual gauge lead frame |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4249299A (en) * | 1979-03-05 | 1981-02-10 | Hughes Aircraft Company | Edge-around leads for backside connections to silicon circuit die |
CN1294483A (zh) * | 1999-10-29 | 2001-05-09 | 华通电脑股份有限公司 | 含金属框的封装用塑胶基板及其制造方法 |
CN101540310A (zh) * | 2008-03-14 | 2009-09-23 | 日月光半导体制造股份有限公司 | 半导体封装及其制作方法 |
Family Cites Families (160)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4948032A (en) | 1988-11-21 | 1990-08-14 | Atmel Corporation | Fluxing agent |
US5200025A (en) | 1990-09-20 | 1993-04-06 | Dainippon Screen Manufacturing Co. Ltd. | Method of forming small through-holes in thin metal plate |
US5389739A (en) | 1992-12-15 | 1995-02-14 | Hewlett-Packard Company | Electronic device packaging assembly |
US5497032A (en) | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
US5554569A (en) * | 1994-06-06 | 1996-09-10 | Motorola, Inc. | Method and apparatus for improving interfacial adhesion between a polymer and a metal |
JPH08115989A (ja) | 1994-08-24 | 1996-05-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
US5646831A (en) | 1995-12-28 | 1997-07-08 | Vlsi Technology, Inc. | Electrically enhanced power quad flat pack arrangement |
US7166495B2 (en) | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
US6001671A (en) | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US5847458A (en) | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
KR0185512B1 (ko) | 1996-08-19 | 1999-03-20 | 김광호 | 칼럼리드구조를갖는패키지및그의제조방법 |
US6097098A (en) | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
US6201292B1 (en) | 1997-04-02 | 2001-03-13 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member used therefor |
JP2928190B2 (ja) | 1997-04-09 | 1999-08-03 | 九州日本電気株式会社 | テーピングリードフレーム |
JP3097653B2 (ja) | 1998-04-17 | 2000-10-10 | 日本電気株式会社 | 半導体装置用パッケージおよびその製造方法 |
US6949816B2 (en) | 2003-04-21 | 2005-09-27 | Motorola, Inc. | Semiconductor component having first surface area for electrically coupling to a semiconductor chip and second surface area for electrically coupling to a substrate, and method of manufacturing same |
US6132593A (en) * | 1998-06-08 | 2000-10-17 | Tan; Yong-Jun | Method and apparatus for measuring localized corrosion and other heterogeneous electrochemical processes |
US6635957B2 (en) | 1998-06-10 | 2003-10-21 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
US6585905B1 (en) | 1998-06-10 | 2003-07-01 | Asat Ltd. | Leadless plastic chip carrier with partial etch die attach pad |
US6989294B1 (en) | 1998-06-10 | 2006-01-24 | Asat, Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6933594B2 (en) | 1998-06-10 | 2005-08-23 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US7226811B1 (en) | 1998-06-10 | 2007-06-05 | Asat Ltd. | Process for fabricating a leadless plastic chip carrier |
US7271032B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US7049177B1 (en) | 2004-01-28 | 2006-05-23 | Asat Ltd. | Leadless plastic chip carrier with standoff contacts and die attach pad |
US7247526B1 (en) | 1998-06-10 | 2007-07-24 | Asat Ltd. | Process for fabricating an integrated circuit package |
US6498099B1 (en) | 1998-06-10 | 2002-12-24 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6143981A (en) * | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
JP3764587B2 (ja) * | 1998-06-30 | 2006-04-12 | 富士通株式会社 | 半導体装置の製造方法 |
US6667541B1 (en) | 1998-10-21 | 2003-12-23 | Matsushita Electric Industrial Co., Ltd. | Terminal land frame and method for manufacturing the same |
US6303985B1 (en) | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
AU6000699A (en) | 1998-12-02 | 2000-06-19 | Hitachi Limited | Semiconductor device, method of manufacture thereof, and electronic device |
DE19905055A1 (de) | 1999-02-08 | 2000-08-17 | Siemens Ag | Halbleiterbauelement mit einem Chipträger mit Öffnungen zur Kontaktierung |
SG75154A1 (en) | 1999-02-23 | 2000-09-19 | Inst Of Microelectronics | Plastic ball grid array package |
JP3780122B2 (ja) | 1999-07-07 | 2006-05-31 | 株式会社三井ハイテック | 半導体装置の製造方法 |
US20020100165A1 (en) | 2000-02-14 | 2002-08-01 | Amkor Technology, Inc. | Method of forming an integrated circuit device package using a temporary substrate |
JP3062192B1 (ja) | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
US6451627B1 (en) | 1999-09-07 | 2002-09-17 | Motorola, Inc. | Semiconductor device and process for manufacturing and packaging a semiconductor device |
TW423133B (en) | 1999-09-14 | 2001-02-21 | Advanced Semiconductor Eng | Manufacturing method of semiconductor chip package |
US6525406B1 (en) | 1999-10-15 | 2003-02-25 | Amkor Technology, Inc. | Semiconductor device having increased moisture path and increased solder joint strength |
US6333252B1 (en) | 2000-01-05 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6342730B1 (en) | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6261864B1 (en) | 2000-01-28 | 2001-07-17 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
EP1122778A3 (en) | 2000-01-31 | 2004-04-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
JP3706533B2 (ja) | 2000-09-20 | 2005-10-12 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
US7173336B2 (en) | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
US7091606B2 (en) | 2000-01-31 | 2006-08-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device and semiconductor module |
US6306685B1 (en) | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
US6238952B1 (en) | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
EP1143509A3 (en) | 2000-03-08 | 2004-04-07 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
US6242284B1 (en) | 2000-05-05 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Method for packaging a semiconductor chip |
JP3883784B2 (ja) | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP2001338947A (ja) | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
US6683368B1 (en) | 2000-06-09 | 2004-01-27 | National Semiconductor Corporation | Lead frame design for chip scale package |
TW506236B (en) | 2000-06-09 | 2002-10-11 | Sanyo Electric Co | Method for manufacturing an illumination device |
TW507482B (en) | 2000-06-09 | 2002-10-21 | Sanyo Electric Co | Light emitting device, its manufacturing process, and lighting device using such a light-emitting device |
JP3650001B2 (ja) | 2000-07-05 | 2005-05-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US6429536B1 (en) | 2000-07-12 | 2002-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
TW473965B (en) | 2000-09-04 | 2002-01-21 | Siliconware Precision Industries Co Ltd | Thin type semiconductor device and the manufacturing method thereof |
TW497371B (en) | 2000-10-05 | 2002-08-01 | Sanyo Electric Co | Semiconductor device and semiconductor module |
JP4417541B2 (ja) | 2000-10-23 | 2010-02-17 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3653460B2 (ja) | 2000-10-26 | 2005-05-25 | 三洋電機株式会社 | 半導体モジュールおよびその製造方法 |
US6689640B1 (en) | 2000-10-26 | 2004-02-10 | National Semiconductor Corporation | Chip scale pin array |
US6906414B2 (en) | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
JP3895570B2 (ja) | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
US6720207B2 (en) | 2001-02-14 | 2004-04-13 | Matsushita Electric Industrial Co., Ltd. | Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device |
US6551859B1 (en) | 2001-02-22 | 2003-04-22 | National Semiconductor Corporation | Chip scale and land grid array semiconductor packages |
US6661083B2 (en) | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US6545347B2 (en) | 2001-03-06 | 2003-04-08 | Asat, Limited | Enhanced leadless chip carrier |
JP3609737B2 (ja) | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
JP4034073B2 (ja) | 2001-05-11 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
TWI264099B (en) * | 2001-07-09 | 2006-10-11 | Sumitomo Metal Mining Co | Lead frame and manufacturing method therefor |
KR20030019082A (ko) | 2001-08-27 | 2003-03-06 | 산요 덴키 가부시키가이샤 | 회로 장치의 제조 방법 |
JP2003124421A (ja) | 2001-10-15 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法 |
US7001798B2 (en) | 2001-11-14 | 2006-02-21 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
TW523887B (en) | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
JP4173346B2 (ja) | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2003204027A (ja) | 2002-01-09 | 2003-07-18 | Matsushita Electric Ind Co Ltd | リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法 |
US7247938B2 (en) | 2002-04-11 | 2007-07-24 | Nxp B.V. | Carrier, method of manufacturing a carrier and an electronic device |
US6777265B2 (en) | 2002-04-29 | 2004-08-17 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6812552B2 (en) | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7799611B2 (en) | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
JP2004063615A (ja) | 2002-07-26 | 2004-02-26 | Nitto Denko Corp | 半導体装置の製造方法、半導体装置製造用接着シートおよび半導体装置 |
KR20040030283A (ko) | 2002-09-05 | 2004-04-09 | 신꼬오덴기 고교 가부시키가이샤 | 리드 프레임 및 그 제조 방법 |
US6818973B1 (en) | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US6777788B1 (en) | 2002-09-10 | 2004-08-17 | National Semiconductor Corporation | Method and structure for applying thick solder layer onto die attach pad |
US7091602B2 (en) * | 2002-12-13 | 2006-08-15 | Freescale Semiconductor, Inc. | Miniature moldlocks for heatsink or flag for an overmolded plastic package |
AU2003285638A1 (en) | 2002-12-20 | 2004-07-14 | Koninklijke Philips Electronics N.V. | Electronic device and method of manufacturing same |
US20040124505A1 (en) | 2002-12-27 | 2004-07-01 | Mahle Richard L. | Semiconductor device package with leadframe-to-plastic lock |
SG157957A1 (en) * | 2003-01-29 | 2010-01-29 | Interplex Qlp Inc | Package for integrated circuit die |
US6927483B1 (en) | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
TW200425427A (en) | 2003-05-02 | 2004-11-16 | Siliconware Precision Industries Co Ltd | Leadframe-based non-leaded semiconductor package and method of fabricating the same |
US6927479B2 (en) | 2003-06-25 | 2005-08-09 | St Assembly Test Services Ltd | Method of manufacturing a semiconductor package for a die larger than a die pad |
US20040262781A1 (en) | 2003-06-27 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for forming an encapsulated device and structure |
TWI233674B (en) | 2003-07-29 | 2005-06-01 | Advanced Semiconductor Eng | Multi-chip semiconductor package and manufacturing method thereof |
CN101375382B (zh) | 2003-08-14 | 2011-04-20 | 宇芯(毛里求斯)控股有限公司 | 半导体器件封装及其制造方法 |
TWI257693B (en) | 2003-08-25 | 2006-07-01 | Advanced Semiconductor Eng | Leadless package |
US7060535B1 (en) | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
KR100568225B1 (ko) | 2003-11-06 | 2006-04-07 | 삼성전자주식회사 | 리드 프레임 및 이를 적용한 반도체 패키지 제조방법 |
JP2005191240A (ja) | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2005191342A (ja) | 2003-12-26 | 2005-07-14 | Renesas Technology Corp | 半導体装置およびその製造方法 |
TWI254437B (en) | 2003-12-31 | 2006-05-01 | Advanced Semiconductor Eng | Leadless package |
US7122406B1 (en) | 2004-01-02 | 2006-10-17 | Gem Services, Inc. | Semiconductor device package diepad having features formed by electroplating |
JP2005203390A (ja) | 2004-01-13 | 2005-07-28 | Seiko Instruments Inc | 樹脂封止型半導体装置の製造方法 |
US7494557B1 (en) * | 2004-01-30 | 2009-02-24 | Sandia Corporation | Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures |
US7215009B1 (en) | 2004-02-23 | 2007-05-08 | Altera Corporation | Expansion plane for PQFP/TQFP IR—package design |
US7008820B2 (en) | 2004-06-10 | 2006-03-07 | St Assembly Test Services Ltd. | Chip scale package with open substrate |
CN2726111Y (zh) | 2004-06-22 | 2005-09-14 | 胜开科技股份有限公司 | 堆叠集成电路封装组件 |
WO2006008679A2 (en) | 2004-07-13 | 2006-01-26 | Koninklijke Philips Electronics N.V. | Electronic device comprising an integrated circuit |
US7087461B2 (en) | 2004-08-11 | 2006-08-08 | Advanced Semiconductor Engineering, Inc. | Process and lead frame for making leadless semiconductor packages |
JP2006066545A (ja) * | 2004-08-25 | 2006-03-09 | Mitsubishi Electric Corp | 電子部品パッケージ |
TWI256096B (en) | 2004-10-15 | 2006-06-01 | Advanced Semiconductor Eng | Method for fabricating quad flat non-leaded package |
US7598606B2 (en) | 2005-02-22 | 2009-10-06 | Stats Chippac Ltd. | Integrated circuit package system with die and package combination |
US7846775B1 (en) | 2005-05-23 | 2010-12-07 | National Semiconductor Corporation | Universal lead frame for micro-array packages |
US7348663B1 (en) | 2005-07-15 | 2008-03-25 | Asat Ltd. | Integrated circuit package and method for fabricating same |
TWI287275B (en) | 2005-07-19 | 2007-09-21 | Siliconware Precision Industries Co Ltd | Semiconductor package without chip carrier and fabrication method thereof |
JP3947750B2 (ja) | 2005-07-25 | 2007-07-25 | 株式会社三井ハイテック | 半導体装置の製造方法及び半導体装置 |
US8003444B2 (en) | 2005-08-10 | 2011-08-23 | Mitsui High-Tec, Inc. | Semiconductor device and manufacturing method thereof |
US7262491B2 (en) | 2005-09-06 | 2007-08-28 | Advanced Interconnect Technologies Limited | Die pad for semiconductor packages and methods of making and using same |
TWI264091B (en) | 2005-09-15 | 2006-10-11 | Siliconware Precision Industries Co Ltd | Method of manufacturing quad flat non-leaded semiconductor package |
US8536689B2 (en) | 2005-10-03 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit package system with multi-surface die attach pad |
US8163604B2 (en) | 2005-10-13 | 2012-04-24 | Stats Chippac Ltd. | Integrated circuit package system using etched leadframe |
TWI277184B (en) * | 2005-12-02 | 2007-03-21 | Advanced Semiconductor Eng | Flip-chip leadframe type package and fabrication method thereof |
TW200729429A (en) | 2006-01-16 | 2007-08-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
TW200729444A (en) | 2006-01-16 | 2007-08-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
JP2007221045A (ja) | 2006-02-20 | 2007-08-30 | Oki Electric Ind Co Ltd | マルチチップ構造を採用した半導体装置 |
US7301225B2 (en) | 2006-02-28 | 2007-11-27 | Freescale Semiconductor, Inc. | Multi-row lead frame |
TWI286375B (en) | 2006-03-24 | 2007-09-01 | Chipmos Technologies Inc | Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same |
US7683461B2 (en) | 2006-07-21 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit leadless package system |
US20080029855A1 (en) | 2006-08-04 | 2008-02-07 | Yi-Ling Chang | Lead Frame and Fabrication Method thereof |
TW200810044A (en) | 2006-08-04 | 2008-02-16 | Advanced Semiconductor Eng | Non-lead leadframe and package therewith |
JP2008053515A (ja) * | 2006-08-25 | 2008-03-06 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
US9281218B2 (en) | 2006-08-30 | 2016-03-08 | United Test And Assembly Center Ltd. | Method of producing a semiconductor package |
JP4533875B2 (ja) | 2006-09-12 | 2010-09-01 | 株式会社三井ハイテック | 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法 |
US20080079127A1 (en) | 2006-10-03 | 2008-04-03 | Texas Instruments Incorporated | Pin Array No Lead Package and Assembly Method Thereof |
US20080079124A1 (en) | 2006-10-03 | 2008-04-03 | Chris Edward Haga | Interdigitated leadfingers |
US7741704B2 (en) | 2006-10-18 | 2010-06-22 | Texas Instruments Incorporated | Leadframe and mold compound interlock in packaged semiconductor device |
EP2084744A2 (en) | 2006-10-27 | 2009-08-05 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7608484B2 (en) | 2006-10-31 | 2009-10-27 | Texas Instruments Incorporated | Non-pull back pad package with an additional solder standoff |
US7608482B1 (en) | 2006-12-21 | 2009-10-27 | National Semiconductor Corporation | Integrated circuit package with molded insulation |
US20080174981A1 (en) * | 2007-01-24 | 2008-07-24 | Chan Say Teow | Pre-molded lead frame and process for manufacturing the same |
US7605477B2 (en) | 2007-01-25 | 2009-10-20 | Raytheon Company | Stacked integrated circuit assembly |
KR100950378B1 (ko) | 2007-01-31 | 2010-03-29 | 야마하 가부시키가이샤 | 반도체 장치와 패키징 구조체 |
TWI337387B (en) | 2007-04-20 | 2011-02-11 | Chipmos Technologies Inc | Leadframe for leadless package, package structure and manufacturing method using the same |
CN101075599A (zh) * | 2007-04-29 | 2007-11-21 | 江苏长电科技股份有限公司 | 改善半导体塑料封装体内元器件分层的封装方法 |
US7800211B2 (en) | 2007-06-29 | 2010-09-21 | Stats Chippac, Ltd. | Stackable package by using internal stacking modules |
US7675146B2 (en) | 2007-09-07 | 2010-03-09 | Infineon Technologies Ag | Semiconductor device with leadframe including a diffusion barrier |
JP2009064995A (ja) * | 2007-09-07 | 2009-03-26 | Sharp Corp | 半導体パッケージおよび電子機器 |
US7838974B2 (en) | 2007-09-13 | 2010-11-23 | National Semiconductor Corporation | Intergrated circuit packaging with improved die bonding |
US20090127682A1 (en) * | 2007-11-16 | 2009-05-21 | Advanced Semiconductor Engineering, Inc. | Chip package structure and method of fabricating the same |
US20090189261A1 (en) | 2008-01-25 | 2009-07-30 | Lay Yeap Lim | Ultra-Thin Semiconductor Package |
US7834431B2 (en) | 2008-04-08 | 2010-11-16 | Freescale Semiconductor, Inc. | Leadframe for packaged electronic device with enhanced mold locking capability |
TWI368983B (en) | 2008-04-29 | 2012-07-21 | Advanced Semiconductor Eng | Integrated circuit package and manufacturing method thereof |
TWI372458B (en) | 2008-05-12 | 2012-09-11 | Advanced Semiconductor Eng | Stacked type chip package structure |
TW200947654A (en) | 2008-05-12 | 2009-11-16 | Advanced Semiconductor Eng | Stacked type chip package structure and method of fabricating the same |
US7786557B2 (en) | 2008-05-19 | 2010-08-31 | Mediatek Inc. | QFN Semiconductor package |
US20090315159A1 (en) | 2008-06-20 | 2009-12-24 | Donald Charles Abbott | Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20110163430A1 (en) | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
-
2009
- 2009-08-26 US US12/547,787 patent/US8124447B2/en active Active
- 2009-08-31 US US12/550,645 patent/US8106492B2/en active Active
- 2009-08-31 US US12/550,655 patent/US20100258921A1/en not_active Abandoned
- 2009-12-21 TW TW098143935A patent/TWI587414B/zh active
- 2009-12-21 TW TW098143934A patent/TWI419241B/zh active
- 2009-12-22 TW TW098144326A patent/TW201037808A/zh unknown
-
2010
- 2010-01-22 CN CN2010101068588A patent/CN101859713B/zh active Active
- 2010-01-22 CN CN2010101068338A patent/CN101859740B/zh active Active
- 2010-01-22 CN CN201010107079XA patent/CN101859734B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4249299A (en) * | 1979-03-05 | 1981-02-10 | Hughes Aircraft Company | Edge-around leads for backside connections to silicon circuit die |
CN1294483A (zh) * | 1999-10-29 | 2001-05-09 | 华通电脑股份有限公司 | 含金属框的封装用塑胶基板及其制造方法 |
CN101540310A (zh) * | 2008-03-14 | 2009-09-23 | 日月光半导体制造股份有限公司 | 半导体封装及其制作方法 |
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CN101859740A (zh) | 2010-10-13 |
CN101859713A (zh) | 2010-10-13 |
US8124447B2 (en) | 2012-02-28 |
TW201037808A (en) | 2010-10-16 |
TW201037776A (en) | 2010-10-16 |
CN101859734A (zh) | 2010-10-13 |
TWI419241B (zh) | 2013-12-11 |
US20100258921A1 (en) | 2010-10-14 |
US20100258920A1 (en) | 2010-10-14 |
CN101859713B (zh) | 2012-05-02 |
CN101859740B (zh) | 2012-05-02 |
US8106492B2 (en) | 2012-01-31 |
US20100258934A1 (en) | 2010-10-14 |
TWI587414B (zh) | 2017-06-11 |
TW201037775A (en) | 2010-10-16 |
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