CN101872778B - 集成电路3d相变存储器阵列及制造方法 - Google Patents

集成电路3d相变存储器阵列及制造方法 Download PDF

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CN101872778B
CN101872778B CN2010100014947A CN201010001494A CN101872778B CN 101872778 B CN101872778 B CN 101872778B CN 2010100014947 A CN2010100014947 A CN 2010100014947A CN 201010001494 A CN201010001494 A CN 201010001494A CN 101872778 B CN101872778 B CN 101872778B
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龙翔澜
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Abstract

一种3D相变存储器元件是基于电极柱阵列及多个电极平面，所述多个电极平面在界面区与所述电极柱相交，所述界面区包含存储器构件，所述存储器构件包括可程序化相变存储器构件及临界值切换构件。可使用二维解码来选择所述电极柱，且可使用第三维上的解码来选择所述多个电极平面。

Description

集成电路3D相变存储器阵列及制造方法
技术领域
本发明是有关于高密度相变存储器元件，且特别是有关于其中多个存储器单元平面经配置以提供三维(three-dimensional，3D)阵列的存储器元件。
背景技术
可由以适于在集成电路中实施的位准施加电流来致使基于相变的存储器材料(如基于硫族化物(chalcogenide-based)的材料及类似材料)在非晶状态与结晶状态之间变相。与大致为结晶状态相比，大致为非晶状态的特征在于较高的电阻率，其可容易被感测以指示资料。此等特性已在使用可程序化电阻材料来形成非挥发性存储器电路中引起关注，所述非挥发性存储器电路可用随机存取进行读取及写入。
随着集成电路中的元件的关键尺寸缩减至一般存储器单元技术的限值，设计者一直在寻找用于堆叠多个存储器单元平面以达成较大储存容量且达成每位的较低成本的技术。在2008年5月1日公开的Haring-Bolivar等人的美国专利申请公开案第US 2008/0101109号中已提出多层相变元件(参见图11a)。Haring-Bolivar等人的结构由以一者位于另一者上方的堆叠配置的若干2D相变存储器单元阵列组成，其中以一者在另一者直接上方的方式配置的相变存储器构件是由选择晶体管由共同通路(vias)而致动并接触的。
亦已开发多层工艺以用于其它存储器技术。举例而言，在Lai等人的“A Multi-Layer Stackable Thin-Film Transistor(TFT)NAND-Type FlashMemory”(IEEE国际电子元件会议，2006年12月11日至13日)中；以及在Jung等人的“Three Dimens ionally Stacked NAND Flash MemoryTechnology Using Stacking Single Crystal Si Layers on ILD and TANOSStructure for Beyond 30nm Node”(IEEE国际电子元件会议，2006年12月11日至13日)中，将薄膜晶体管技术应用于电荷捕集存储器技术。
而且，在Johnson等人的“512-Mb PROM With a Three-DimensionalArray of Diode/Anti-fuse Memory Cells”(2003年11月的IEEE固态电路期刊第38卷11期(IEEE J.of Solid-State Circuits，vol.38，no.11))中，已将交叉点阵列(cross-point array)技术应用于反熔丝(anti-fuse)存储器。在Johnson等人描述的设计中，提供多个字符线层及位线层，其中在交叉点处具有存储器构件。存储器构件包括连接至字符线的p+多晶硅阳极，以及连接至位线的n-多晶硅阴极，其中阳极与阴极藉由反熔丝材料而分离。
在Haring-Bolivar等人、Lai等人、Jung等人以及Johnson等人描述的工艺中，针对每一存储器层存在若干关键光刻步骤。因此，制造元件所需的关键光刻步骤的数目由所构建之层的数目倍增。关键光刻步骤是昂贵的，且因此需在制造集成电路的过程中使关键光刻步骤减至最少。因此，尽管使用3D阵列达成较高密度的益处，但较高制造成本限制所述技术的使用。
在Tanaka等人的“Bit Cost Scalable Technology with Punch andPlug Process for Ultra High Density Flash Memory”(2007VLSI技术讨论会技术论文汇编(2007Symposium on VLSITechnology Digest ofTechnical Papers)；2007年6月12日至14日，第14至15页)中描述另一结构，其在电荷捕集存储器技术中提供垂直“反及”(NAND)单元。Tanaka等人描述的结构包含具有类似于NAND门而操作的垂直通道的多栅极场效晶体管结构，其使用硅-氧化物-氮化物-氧化物-硅(silicon-oxide-nitride-oxide-silicon，SONOS)电荷捕集技术来在每一栅极/垂直通道界面处产生储存位点。所述存储器结构是基于配置为用于多栅极单元的垂直通道的半导体材料柱，其具有邻近于基板的下部选择栅极、位于顶部的上部选择栅极。使用与所述柱相交的平面电极层来形成多个水平控制栅极。用于控制栅极的平面电极层不需要关键光刻，且因此节省成本。然而，在上述垂直单元的每一者的顶部及底部需要关键光刻步骤。而且，在可以此方式成层的控制栅极的数目上存在限制，所述数目由诸如垂直通道的传导性、所使用的程序化及抹除过程等因素决定。
需要提供一种具有较低制造成本的用于三维集成电路存储器的结构，其包含可靠的、非常小的存储器构件。
发明内容
一种3D存储器元件是基于电极柱阵列及多个电极平面的，所述多个电极平面在界面区与所述电极柱相交，所述界面区包含相变存储器构件。可使用二维解码来选择所述电极柱，且可使用第三维上的解码来选择所述多个电极平面。
描述一实施例，所述实施例包括集成电路基板，其具有存储器单元存取层，所述存储器单元存取层具有存取元件阵列及对应的位于顶面上的触点阵列。多个导电层位于存取元件阵列上方或下方，由绝缘层彼此分离且与所述存取元件阵列分离。电极柱阵列延伸穿过所述多个导电层及绝缘层。电极柱(诸如)由接触触点阵列中的触点而耦接至对应的存取元件。存储器构件位于所述柱与所述导电层之间的界面区中，其中所述存储器构件中的每一者包括与临界值切换元件(诸如固体电解质层或隧穿介电质层)串联的可程序化相变存储器构件。
在替代例中，可使用薄膜晶体管或相关技术在导电层上或之间形成存取元件阵列。
列解码电路及行解码电路耦接至存取元件阵列，且用以响应于地址而选择电极柱。平面解码电路耦接至多个导电层，且用以响应于地址而选择导电层。而且，平面解码电路用以在选定导电层的界面区中使临界值切换元件偏置至导电状态，且在未选定导电层的界面区中使临界值切换元件偏置至非导电状态。
描述电极柱，其包含呈导电材料芯的形式的接触触点阵列中的对应触点的导体，以及位于所述芯与所述多个导电层之间的存储器材料层及临界值切换材料层。存储器构件中的可程序化构件包括界面区的存储器材料层中的主动区。存储器构件中的可程序化构件包括芯与导电层之间的界面区的存储器材料层中的主动区。
存储器单元存取层中的存取元件在本文所述的各种实施例中包括垂直晶体管或水平晶体管，其中位线及字符线耦接至所述晶体管的漏极与门极。
使用毯覆式(blanket)沉积工艺序列来形成所述多个导电层，其中进行图案化以组态所述层的周边以便与平面解码电路接触。可使用渐缩蚀刻(tapered etching)工艺来图案化导电层，使得连续层在锥体(taper)上后退以形成突出部分(ledges)，且沿所述锥体形成接触所述层的突出部分的触点。
在另一实施例中，导电层具有沿周边的翼片，所述翼片经组态以与解码电路接触。集成电路包含上覆于所述多个导电层上的布线层，其包含将所述多个导电层耦接至解码电路的导体。导电插塞接触所述多个导电层上的翼片，且向上延伸至布线层。在一实施例中，翼片以交错方式配置，其减少平面解码电路的占据面积。交错翼片用以使得耦接至两个或两个以上导电层上的交错翼片的导电插塞以列配置，所述列在由所述交错翼片界定的方向上延伸。
描述一种存储器元件的制造方法，其包含：形成存储器单元存取层或另外形成存取元件阵列；形成上覆于所述存储器单元存取层中的存取元件阵列上的多个导电层；形成延伸穿过所述多个导电层的电极柱阵列，其具有在所述多个导电层中的电极柱之间的界面区中的存储器构件。用于形成所述多个导电层的技术包含：在存取层的顶面上沉积层间介电质之后，针对每一导电层，执行形成毯覆式导电材料层的步骤以及在所述毯覆式导电材料层上形成毯覆式绝缘材料层的步骤。用于形成电极柱阵列中的电极柱的技术包含：在提供所述多个导电层之后，界定在触点阵列中的触点中的一个触点上方穿过所述多个导电层的电极通路。接下来，在所述电极通路的侧壁上形成诸如固体电解质材料或隧穿介电质的临界值切换材料层。接着，在临界值切换材料层上形成相变存储器材料层。最后，使用一或多层导电材料(诸如类似钨的金属，或类似氮化钛的金属氮化物)，以电极材料填充存储器材料层上的电极通路。
在本文所述的一工艺中，用于在毯覆式导电材料层上界定周边的技术包含图案化所述周边的多个部分，使得所述部分包含经组态以与解码电路接触的翼片。在形成多个导电层之后形成多个导电插塞，其接触所述多个导电层上的相应翼片，且向上延伸至上覆于所述多个导电层上的布线平面。所述翼片可以交错方式配置，使得耦接至不同导电层上的交错翼片的导电插塞以列配置，所述列在由所述交错翼片界定的方向上延伸。
描述一种新颖的三维相变存储器单元结构。在一个实例中，使用字符线及位线来驱动存取晶体管。存取晶体管连接至电极柱。电极柱包含相变材料层，以及位于所述相变材料层上的临界值切换层。电极柱的侧壁由多个导电材料层接触。每一导电层与电极柱的周边之间的界面区提供一存储器单元。
由启用耦接至用于选定柱的存取晶体管的一个字符线及一个位线来对存储器单元进行程序化。柱与选定导电层之间的偏压将使临界值切换材料偏置于导电状态，且对界面区中的相变材料的主动区进行程序化。由感测选定位线上或导电层中与选定存储器单元耦接的一者上的电流来读出信息。
附图说明
在审阅所附的附图、详细描述及申请专利范围后可见本发明的其它态样及优点，其中：
图1为垂直FET存取元件以及包含用于如本文所述的元件的多个存储器构件的多层级电极柱的剖面。
图2为已移除导电层的多层级电极柱的俯视图。
图3说明包含存储器构件及临界值切换构件的多层级电极柱上的界面区。
图4为诸如图1所示的存取元件及多层级电极柱的示意图。
图5为由多层级电极柱组成的存储器阵列的2×2×n部分的示意图。
图6为包含用于如本文所述的元件的多个存储器构件的多层级电极柱中的水平FET存取元件的剖面。
图7为绘示用于如图6所示而构建的存储器阵列的字符线及位线的布局图。
图8A至图8C说明用于基于渐缩蚀刻而图案化导电层的周边的工艺中的阶段。
图9为导电层及用于将导电层连接至平面解码电路的内连布线的布局图。
图10为包含水平FET存取元件的存储器阵列的一部分的剖面。
图11为存储器阵列的另一部分的剖面，所述部分包含水平FET存取元件以及导电层的周边上的内连插塞及通路。
图12A至图12B为用于制造如本文所述的存储器阵列的方法的流程图。
图13A至图13B说明包含经配置以用于与内连通路及插塞形成接触的交错翼片的导电层的布局。
图14绘示包含交错翼片以及用于与解码电路内连的上覆布线的导电层的俯视图。
图15为说明可用于极大数目的存储器平面的电极柱堆叠的剖面图。
图16为包含具有列解码电路、行解码电路及平面解码电路的3D存储器阵列的集成电路的示意图。
具体实施方式
参看图1至图16而提供本发明的实施例的详细描述。
图1为多层级存储器单元的剖面。所述存储器单元形成于集成电路基板上，所述集成电路基板在此实例中包含半导体主体10，其具有以列形式图案化于表面上的沟渠隔离结构12。在沟渠隔离结构12之间，沉积植入物以形成埋入式扩散位线11。绘示用于单个存储器单元柱的存取元件，其由具有由栅极介电层29围绕的漏极13、通道14以及源极15的垂直FET晶体管组成。绝缘层16上覆于半导体主体10上。字符线17横穿阵列，且围绕垂直FET的通道14。在此实例中，绝缘层18上覆于字符线上。硅化物层19形成于源极15的顶部。在此实例中，在硅化物层19上界定并图案化钨接触焊垫20。在此实例中包含层21及层22的绝缘层上覆于接触焊垫20上。图中所示结构的自接触焊垫20至半导体主体10(例如，块体硅)的部分为包含存储器单元存取层100的集成电路基板的部分。
多个导电层23-1至23-n上覆于接触焊垫20以及绝缘层22上。绝缘层24-1至24-(n-1)使导电层23-1至23-n彼此分离。导电层23-1至23-n可包括耐火金属(诸如W)或其它材料(例如TiN或TaN)。或者，导电层23-1至23-n可包括来自Ti、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O及Ru的族群之一或多个元素。在其它实施例中，导电层23-1至23-n可包括掺杂多晶硅、其它掺杂半导体材料。
绝缘层24-n覆盖顶部导电层23-n。在替代实施例中，可使用薄膜晶体管技术来在所述多个导电层上或导电层之间形成存取元件阵列。
用于多层级存储器的电极柱由包含中央导电芯25的导体组成，所述中央导电芯25例如由钨或其它合适电极材料制成，且由相变存储器材料层26及位于相变存储器材料层26上的临界值(threshold)切换材料层27围绕，其中所述临界值切换材料接触所述多个导电层，或以其它方式与所述多个导电层电流连通。
所述多个导电层23-1至23-n与柱之间的界面区(诸如区30)包含相变存储器构件，其包括与如下文参看图3更详细地阐释的临界值切换构件串联的可程序化构件。
层26包含基于相变的存储器材料，诸如基于硫族化物的材料及其它材料。硫族化物包含形成周期表的第VIA族的部分的四个元素氧(O)、硫(S)、硒(Se)及碲(Te)中的任一者。硫族化物包括硫族元素与更具电正性的元素或自由基的化合物。硫族化物合金包括硫族化物与其它材料(诸如过渡金属)的组合。硫族化物合金通常含有来自元素周期表的第IVA族之一或多个元素，诸如锗(Ge)及锡(Sn)。通常，硫族化物合金包含包括锑(Sb)、镓(Ga)、铟(In)及银(Ag)中之一或多者的组合。技术文献中已描述了许多基于相变的存储器材料，包含以下各项的合金：Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te及Te/Ge/Sb/S。在Ge/Sb/Te合金族中，较广范围的合金组合物可起作用。可将所述组合物表征为TeaGebSb100-(a+b)。一位研究者已将最有用的合金描述为在所沉积材料中具有大大低于70％的Te平均浓度，典型地低于约60％且通常在自低至约23％至多达约58％的范围内变动的Te，最佳为约48％至58％的Te。Ge的浓度为高于约5％，且在材料中自约8％的低值至约30％的平均值的范围内变动，保持于大致为低于50％。最佳的是，Ge的浓度在自约8％至约40％的范围内变动。此组合物中的主要组成元素的其余部分为Sb。此等百分比为原子百分比，其总计为组成元素的原子的100％。(Ovshinsky的5,687,112专利第10至11行)。另一研究者评估的特定合金包含Ge2Sb2Te5、GeSb2Te4及GeSb4Te7(Noboru Yamada，“Potent ial of Ge-Sb-Te Phase-ChangeOptical Disks for High-Data-Rate Recording”，SPIE v.3109，第28至37页(1997))。更一般而言，诸如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)及其混合物或合金的过渡金属可与Ge/Sb/Te组合，以形成具有可程序化电阻特性的相变合金。Ovshinsky的‘112中在第11至13行处给出可使用的存储器材料的特定实例，所述实例以引用的方式并入本文中。
在一些实施例中，用杂质来掺杂硫族化物及其它相变材料，以使用经掺杂的硫族化物来改变存储器构件的导电性、转变温度、熔化温度以及其它特性。用于掺杂硫族化物的代表性杂质包含氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛以及氧化钛。
相变合金能够以第一结构状态及第二结构状态在单元的主动通道区中作局部次序的切换，在第一结构状态下，材料处于大致为非晶固相，且在第二结构状态下，材料处于大致为结晶固相。此等合金至少为双稳态的(bistable)。术语“非晶”用于指代相对较低次序的结构，较单晶体无序，其具有可侦测特征，诸如比结晶相较高的电阻率。术语“结晶”用于指代相对较高次序的结构，较非晶结构有序，其具有可侦测特征，诸如比非晶相更低的电阻率。通常，相变材料可在于完全非晶状态与完全结晶状态之间的范围(spectrum)内具有局部次序的不同的可侦测状态之间的电切换。受非晶相与结晶相之间的改变影响的其它材料特征包含原子次序、自由电子密度及活化能量。材料可切换至不同固相中或两个或两个以上固相的混合物中，从而提供完全非晶状态与完全结晶状态之间的灰阶(gray scale)。材料中的电特性可相应地改变。
相变合金可由电脉冲的施加而自一个相态改变至另一相态。已观察到，较短、较高振幅的脉冲趋于使相变材料改变至大致为非晶状态。较长、较低振幅的脉冲趋于使相变材料改变至大致为结晶状态。较短、较高振幅的脉冲中的能量足够高以允许断开结晶结构的键结，且足够短以防止原子重排序(realigning)为结晶状态。可以决定适当的脉冲剖面，不需要过度(undue)的实验，特别适用于特定相变合金。在本揭露案的以下部分中，将相变材料称为GST，且将理解，可使用其它类型的相变材料。对实施本文所述的PCRAM有用的材料为Ge2Sb2Te5。
用于形成硫族化物材料的例示性方法使用PVD溅镀或磁控管溅镀方法，其中源气体为在1毫托至100毫托的压力下的Ar、N2及/或He等。沉积通常在室温下完成。可使用具有1至5的纵横比的准直仪(collimator)来改良填充效能。为改良填充效能，亦使用几十伏至几百伏的DC偏压。另一方面，可同时使用DC偏压与准直仪的组合。
用于形成硫族化物材料的另一例示性方法使用化学气相沉积(chemical vapor deposition，CVD)，诸如标题为“Chemical VaporDeposition of Chalcogenide Materials”的美国公开案第2006/0172067号中所揭露的CVD，所述美国公开案以引用的方式并入本文中。
选择性地在真空或N2环境中执行沉积后退火处理(post-depositionannealing treatment)，以改良硫族化物材料的结晶状态。退火温度典型地在自100℃至400℃的范围内变动，其中退火时间小于30分钟。
图2绘示包含导电芯25、相变材料层26以及临界值切换材料层27的电极柱的俯视图布局。位线11布设于第一方向上，且字符线17布设于正交的方向上。电极柱由环形临界值切换材料层27围绕。柱中的临界值切换材料层与所述导电材料层中的每一者之间的环形界面界定包含存储器构件的界面区。
图3绘示包含导电层23-2、相变材料层26、导电芯25以及临界值切换材料层27的存储器构件(诸如在界面区30中)的一部分。在原生状态下，相变材料层26可具有大约5至50纳米的厚度。主动区邻近于每一导电层而形成，其响应于在如下文参看图16而描述的芯片上控制电路(on-chipcontrol circuit)的控制下所施加的设定及重设脉冲而改变电阻。读取脉冲可包括在如下文参看图16而描述的芯片上控制电路的控制下所施加的1至2伏的脉冲，其具有取决于组态的脉冲宽度。读取脉冲可比程序化脉冲短得多。
层27中所使用的临界值切换材料的特征在于，在柱上的未选定单元所受到(encounter)的相对较低的电压下具有较低导电性，且在柱上的选定单元所受到的用于读取、设定及重设的操作电压下具有相对较高的导电性。可使用诸如固体电解质(例如硅化锗)的材料或其它合适材料来构建临界值切换层27。对于其它代表性固体电解质材料，请参见Gopalakrishnan的美国专利第7,382,647号。或者，可将诸如具有大约10至50纳米的厚度的二氧化硅层的隧穿介电层用作临界值切换材料，其中低电场允许可忽略的隧穿电流，且在较高电场下允许如读取、设定及重设存储器材料中的主动区所需的较大隧穿电流。
图4为图1的结构的示意性说明。电极柱40耦接至存取晶体管41，使用位线42及字符线43来选择存取晶体管41。多个存储器构件44-1至44-n连接至柱40。所述存储器构件中的每一者包含与临界值切换构件49串联的可程序化构件48。此串联电路示意图表示图3中所示的结构。可程序化构件48由常用于指示可程序化电阻的符号表示。
存储器构件44-1至44-n中的每一者耦接至对应的电极平面45-1至45-n，其中电极平面由本文所述的导电材料层提供。电极平面45-1至45-n耦接至平面解码器46，其响应于地址而将诸如接地47的电压施加至选定电极平面，使得存储器构件中的临界值切换构件导电，且将电压施加至未选定电极平面或使未选定电极平面浮置，使得存储器构件中的临界值切换构件不导电。
图5提供2个字符线×2个位线×n个平面的三维3D存储器阵列的示意性表示。所述阵列包含字符线60及61，其与位线62及63相交。存取元件64、65、66及67位于位线与字符线之间的交叉点处。每一存取元件耦接至对应的电极柱68、69、70、71。每一电极柱包含深度为数目“n”个平面的存储器构件堆叠。因此，柱68耦接至存储器构件72-1至72-n。柱69耦接至存储器构件73-1至73-n。柱70耦接至存储器构件74-1至74-n。柱71耦接至存储器构件75-1至75-n。图5中未说明导电层以避免使图变得拥挤。图5所示的2×2×n阵列可扩展至具有任一数目的平面的数千字符线乘以数千位线的阵列。在代表性实施例中，平面的数目n可为2的幂以促进二进制解码，诸如4、8、16、32、64、128等。
图6为具有水平FET存取元件的多层级存储器单元的剖面。所述存储器单元形成于集成电路基板上，所述基板在此实例中包含半导体主体80。选择性的沟渠隔离结构(未图标)可形成于表面上以隔离元件的区。沉积植入物以形成用于所述存取元件的源极81及漏极82。字符线83形成于栅极介电质上位于源极81与漏极82之间。层间介电质95上覆于半导体主体80中的字符线上。插塞84及插塞86形成于层间介电质95中。插塞84延伸至包含位线BL的经图案化的金属层。插塞86延伸至层间介电质95的表面，且提供上面形成有电极柱的触点(contact)。因此，如图6的实施例中的括号所识别的存储器单元存取层101包含自层间介电质95的表面至半导体主体80的构件。
在此实例中，多个导电层93-1至93-4上覆于绝缘层92上，绝缘层92形成于存储器单元存取层101的顶面上。绝缘层94-1至94-3分离所述多个导电层。绝缘层94-4上覆于导电层93-4上。
多层级电极柱由导电芯组成，所述导电芯包含由相变存储器材料层88围绕的中央导电芯87。临界值切换材料层89形成于相变存储器材料层88与多个导电层93-1至93-4之间，从而在界面区中提供存储器构件(例如，构件90)。
图7绘示使用类似于图6所示的水平FET的存取元件而制成的阵列的布局图。所述阵列包含用于电极柱的接触插塞86以及用于位线的接触插塞84。位线85-1至85-4以对角线方式配置。字符线83-1至83-2在此布局中以垂直方式配置。用于存取元件的主动区96经如图所示图案化，使得其本质上与字符线83-1、83-2正交。沟渠隔离结构(未图标)可选择性地在邻近存取晶体管中的接触插塞86的行与接触插塞84的行之间，与字符线83-1、83-2平行形成。
图8A、图8B以及图8C说明用于界定导电材料层的周边以便与个别层形成接触以用于解码的工艺中的阶段。在图8A中，说明一堆叠，其包含交替的导电层147、148、149及150以及绝缘层165、166、167、168及169。导电层及绝缘层是以交替毯覆式沉积而沉积，其可覆盖集成电路上的整个存储器区域，如图中的虚线所指示。为图案化导电层的周边，形成罩幕160。罩幕160具有渐缩侧边(tapered sides)170。为制作罩幕，可在结构上沈积诸如氮化硅的硬罩幕材料层。接着可图案化一光阻层，且对其进行蚀刻以在光阻上界定渐缩侧边。接着蚀刻所得结构，其中光阻层中的锥体(taper)被转移至硬罩幕160上的对应锥体170。
如图8B所说明，接着以类似方式使用渐缩硬罩幕160。应用诸如反应性离子蚀刻(reactive ion etch，RIE)的蚀刻工艺，使得硬罩幕上的锥体170被转移至导电层堆叠中的对应锥体175。在一些实施例中，可能省略硬罩幕，且在堆叠的锥体蚀刻期间使用渐缩光阻构件。导电层150至147的边缘是参差的(staggered)，以形成围绕其周边的架。由每一层之间的参差产生的架的宽度可由导电层之间的绝缘层的厚度以及锥体175的斜率决定。
用于在硬罩幕上界定锥体170以及在导电层堆叠上界定锥体175的蚀刻工艺可为一连续蚀刻工艺。或者，可使用第一工艺在硬罩幕160上界定锥体170，且使用第二蚀刻工艺在导电层堆叠上界定锥体175。
图8C说明所述工艺中的下一阶段。在形成锥体175之后，沉积绝缘填充物176，且在导电层150至147的堆叠上进行平坦化。接着，使用光刻步骤来界定通路(vias)，所述光刻步骤同时图案化用于所有层的所有通路。应用一蚀刻工艺，其相对于填充层176，对导电层150至147中的导电材料具有高度选择性。以此方式，所述通路中的每一者内的蚀刻工艺在对应的导电层上停止。接着在存储器阵列区域的周边的一侧上用插塞177、178、179、180且在存储器阵列区域的周边的另一侧上用插塞181、182、183、184来填充所述通路。因此，导电层的周边被图案化，且仅使用用以界定硬罩幕160的一个光刻步骤以及用以界定用于接触插塞177至184的通路的位置的一个光刻步骤来形成触点通路。而且，仅应用两个(或可能三个)蚀刻工艺来形成图8C所示的结构。
图9为阵列的一部分的简化布局图，其绘示用于将导电层堆叠连接至平面解码电路的上覆内连件。在图9中，说明顶部介电层150。电极柱(例如，柱151)阵列穿透介电层150。
与图8C中的插塞177至184对应的接触插塞(诸如插塞152)沿导电层的周边配置。位于沿层150的边缘的一列中的接触插塞耦接至上覆于导电层堆叠上的内联机153。
导电层149延伸至内联机153的右方，且位于沿层149的边缘的一列中的接触插塞耦接至内联机154。导电层148延伸至内联机154的右方，且位于沿层148的边缘的一列中的接触插塞耦接至内联机155。导电层147延伸至内联机155的右方，且位于沿层147的边缘的一列中的接触插塞耦接至内联机156。
上覆于阵列上的内连布线153至156的简化视图意欲说明将存储器阵列中的多个导电层耦接至内连布线的方式。所述内连布线接着可在必要时路由至(route)平面解码电路。而且，内连布线可用以在阵列区域上更均匀地分布施加至导电材料层的偏压。
图10及图11共同绘示包含3D相变存储器阵列的集成电路的一部分以及包含多个金属化层及周边电路的存储器单元存取结构的剖面。而且，可在下文参看图12A至图12B陈述的制造方法的描述期间参考图10及图11。
图10绘示形成于基板200上的存储器阵列的一部分。水平FET由基板200中的源极区163、265及漏极区164、266界定。沟渠隔离结构161及162隔离基板中的区。字符线267及268提供用于存取元件的栅极。层间介电质269上覆于字符线267、268及基板上。接触插塞270、271、272及273延伸穿过层间介电质269到达具有介电填充物278的上覆金属化平面，所述介电填充物278包含耦接至触点271及273的位线275及274。接触焊垫277及276延伸穿过介电填充物278到达上覆触点281及280，触点281及280延伸穿过另一层间介电质279。具有介电填充物284的另一金属化平面上覆于介电层279上。接触焊垫282及283耦接至下伏触点280及281，从而提供到达下方存取元件的连接。在此实施例中，存储器单元存取层185包含自接触焊垫282、283穿过存取晶体管的元件，所述存取晶体管包含位于基板200中的源极区及漏极区163、164、265、266。基板200可包括位于此项技术中已知的用于支撑集成电路的绝缘层或其它结构上的块体硅或硅层。
多个电极柱配置于存储器单元存取层185的顶部。在此图中，说明包含导电芯192、相变材料层193及临界值切换材料层194的第一电极柱，以及包含导电芯189、相变材料层190及临界值切换材料层191的第二电极柱。第一电极柱耦接至焊垫282。第二电极柱耦接至焊垫283。绝缘层186-1上覆于存储器单元存取层185上。导电层187-1上覆于绝缘层186-1上。交替的导电层187-2至187-4以及绝缘层186-2至186-4形成于导电层187-1的顶部。介电填充物188上覆于所述结构上，且具有平面顶面。
图11绘示所述元件至周边区中的延续，在周边区中形成支持电路，且形成与所述多个导电层的接触。在图11中，说明包含导电芯189、相变材料层190及临界值切换材料层191的电极柱，且应用与图10中所使用的参考标号相同的参考标号。如图11所示，周边元件包含由源极204、栅极207以及漏极203形成的晶体管。图中说明沟渠隔离结构201。在周边中构建许多种元件，以支持集成电路上的解码逻辑及其它电路。在周边电路中使用多个金属化平面以用于布线内连。因此，接触插塞210自漏极203延伸至上部层中的导线217。插塞218自导线217延伸至另一层中的导线219。
导电层187-1至187-4耦接至对应的接触插塞223、222、221、220。内联机224至227耦接至所述插塞，且提供所述多个导电层与元件周边中的解码电路之间的内连。
图12A及图12B包含可应用于制作图10及图11所示的结构的制造方法的流程图。出于此应用的目的，第一步骤300涉及形成包含位线、字符线、存取元件(包含垂直或水平晶体管)以及触点的存储器单元存取层。在此阶段，集成电路基板上的周边电路亦如图11所示而形成。由于此工艺，元件的存储器区中的存储器单元存取层的顶面具有触点阵列，其包含图10的触点282、283。在此阶段，已应用标准制造技术，包含形成周边电路及存取元件所需的所有必要的图案化及蚀刻步骤。应使用耐火金属(诸如钨)来制作存储器单元存取层中所涉及的触点及内连件，使得大量导电材料层的沉积中所涉及的热预算不会干扰下伏内连件。
接下来，在存储器单元存取层上沉积层间介电质(例如，186-1)(步骤301)。所述层间介电质可为二氧化硅、氮氧化硅、氮化硅或其它层间介电质材料。接下来，执行导电层与介电层的交替毯覆式沉积(步骤302)。此等毯覆式沉积提供充当电极平面的多个导电层(例如，187-1至187-4)。所述导电层的典型厚度可为大约50纳米。所述介电层在导电层之间形成绝缘。在一个实例中，绝缘层的厚度亦可为大约50纳米。其它实例将包含如特定实施方案所要或所需的导体材料以及介电层的较大或较小厚度。在下一阶段中，应用光刻图案来界定并打通用于存储器单元柱的通路，所述通路穿过所述多个导体平面到达存储器单元存取层上的对应触点(步骤303)。可应用反应性离子蚀刻工艺来形成穿过二氧化硅及导体层的较深的高纵横比孔，以提供用于电极柱的通路。
在打通所述通路之后，在电极柱通路的侧壁上沉积临界值切换材料层(步骤304)。可使用原子层沉积或化学气相沉积技术来沉积临界值切换材料。
在形成临界值切换层之后，在电极柱通路的侧壁上的临界值切换材料上沉积相变材料层(步骤305)。接下来，在相变材料层上沈积薄电极材料层，以在后续蚀刻期间保护相变层(步骤306)。
对临界值切换材料、薄膜电极材料及相变材料的所得层进行各向异性(anisotropic)蚀刻以打通电极柱通路的底部，从而暴露下伏触点(步骤307)。在下一步骤中，在电极柱通路内沉积中央电极材料(步骤308)。中央电极材料可与用于步骤306中所形成的薄膜的电极材料相同或不同。在沉积中央电极材料之后，使用化学机械抛光工艺或其它平坦化工艺来回蚀且平坦化所得结构。
接下来，在所述结构上沉积层间介电质(步骤309)。
在形成所述多个导电层之后，使用上文参看图8A至图8C而描述的锥体蚀刻工艺在导电层的周边上界定触点区域(步骤310)。可使用替代技术在所述多个导电层上界定触点区域。替代技术可涉及所述工艺中的其它阶段处的光刻步骤，如根据所应用的技术将理解。在图案化导电层的周边之后，在结构上沉积绝缘填充物并使其平坦化。接着，打通穿过绝缘填充物到达导电层的周边上的触点的通路(步骤311)。
使用钨或其它触点材料来填充所述通路，且应用金属化工艺来在到达元件上的导电层及平面解码电路的触点之间提供内连(步骤312)。最后，应用线BEOL工艺的后端来完成集成电路(步骤313)。
图13A及图13B说明用于所述多个导电层中的导电层的图案，其可应用于在包含交错翼片(tabs)的平面的周边上建立内连触点。因此，图13A绘示平面A，且图13B绘示平面B。翼片250A至253A沿平面A的周边而定位。翼片251B至253B沿平面B的周边而定位。将所述翼片定位成使得当所述平面如图14所示而重迭时，触点(例如，触点255)交错，且界定一平行于所述平面的周边的列。因此，用于平面A的内联机以及用于平面B的内联机可平行路由至所述翼片。此技术显着减少与所述多个导电层形成接触所需的面积。交错可涉及2个以上平面，诸如8个或16个平面或更多，以便显着节省元件上的更多面积。然而，此技术涉及具有导电材料的每一毯覆式沉积的非关键图案步骤。
图15说明一种用于扩展可应用于单个电极柱中的导电层的数目，同时维持相对较小的通路占据面积(footprint)的技术。图15所示的结构包含一堆叠，其包含若干导电层组400-402。第一导电层组400是由使绝缘体层423-1至423-4及导电层424-1至424-4在层422上交替而形成。其它组401及402包括类似结构。所述工艺涉及首先制作第一导电层组400，界定穿过所述第一组的电极柱通路，以及形成电极柱的第一部分。电极柱接触焊垫420的第一部分耦接至存取元件419。接下来，在所述第一组上界定第二导电层组401。穿过第二组401界定电极柱通路，其打通到达电极柱的第一部分的通路。在穿过第二导电层组401的通路内形成电极柱的第二部分。
如图中所示，电极柱的第二部分可与第一部分稍微失对准(misaligned)，因为用于界定通路的光刻工艺中涉及对准容许度。选择性地，可由光刻步骤在层之间形成接触焊垫431，以在需要时在光刻工艺中提供较佳的对准容许度。最后，穿过第三导电层组402界定电极柱通路，其打通到达电极柱的第二部分的通路。在第三导电层组402内形成电极柱的第三部分。附图亦绘示电极柱的第二部分与第三部分之间的选择性接触焊垫432。尽管附图绘示每组四个导电层，但所述技术的实施例可涉及使用较大数目的平面(诸如16个、32个、64个或更多)，其接触电极柱的每一堆叠部分。
图16为根据本发明实施例的集成电路的简化方块图。集成电路475包含位于半导体基板上的如本文所述而构建的3D存储器阵列460。列解码器461耦接至多个字符线462，且沿存储器阵列460中的列而配置。行解码器463耦接至沿存储器阵列460中的行而配置的多个位线464，以用于自阵列460中的存储器单元读取资料并对其进行程序化。平面解码器458在线459上耦接至存储器阵列460中的多个电极平面。地址在总线465上供应至行解码器463、列解码器461以及平面解码器458。区块466中的感测放大器及资料输入结构在此实例中经由资料总线467耦接至行解码器463。资料经由资料输入线471自集成电路475上的输入/输出端口或自集成电路475内部或外部的其它资料源供应至区块466中的资料输入结构。在所说明的实施例中，集成电路上包含其它电路474，诸如通用处理器或特殊应用电路，或提供由薄膜熔丝相变存储器单元阵列支持的芯片上系统(system-on-a-chip)功能性的模块的组合。资料经由资料输出线472自区块466中的感测放大器供应至集成电路475上的输入/输出端口，或供应至集成电路475内部或外部的其它资料目的地。
在此实例中使用偏压配置状态机469构建的控制器控制经由区块468中的电压源产生或提供的偏压配置供电电压(诸如读取及程序化电压)的施加。可使用此项技术中已知的特殊用途逻辑电路来构建所述控制器。在替代实施例中，控制器包括可在同一集成电路上构建的通用处理器，其执行计算机程序以控制元件的操作。在又一些实施例中，特殊用途逻辑电路与通用处理器的组合可用于构建所述控制器。
虽然由参考上文详细描述的较佳实施例及实例而揭露本发明，但应理解，此等实例意欲具有说明性而非限制性意义。预期熟习此项技术者将容易想到修改及组合，所述修改及组合将在本发明的精神以及随附权利要求范围的范畴内。

Claims (17)

1.一种存储器元件，包括：
集成电路基板，包含存取元件阵列；
多个导电层，由绝缘层而彼此分离且与所述存取元件阵列分离；
电极柱阵列，延伸穿过所述多个导电层，所述电极柱阵列中的所述电极柱接触所述存取元件阵列中的对应存取元件，且界定所述电极柱与所述多个导电层中的导电层之间的界面区；以及
所述界面区中的存储器构件，所述存储器构件中的每一者包括可程序化相变存储器构件及临界值切换构件。
2.如权利要求1所述的存储器元件，包含：
耦接至所述存取元件阵列的列解码电路及行解码电路，用以选择所述电极柱阵列中的电极柱；以及
耦接至所述多个导电层的平面解码电路，用以在选定导电层中的所述界面区中使所述临界值切换构件偏置至导电状态，且在未选定导电层中的界面区中使所述临界值切换构件偏置至非导电状态。
3.如权利要求1所述的存储器元件，其中所述电极柱阵列中的电极柱包括与对应存取元件电连通的导体，以及所述导体与所述多个导电层之间的相变存储器材料层，其中所述存储器构件中的每一者中的所述可程序化相变构件包括所述界面区的所述相变存储器材料层中的主动区。
4.如权利要求1所述的存储器元件，其中所述存取元件阵列中的存取元件包括：
晶体管，具有栅极、第一端子及第二端子；以及
所述存取元件阵列包含耦接至所述第一端子的位线、耦接至所述栅极的字符线，且其中所述第二端子耦接至所述电极柱阵列中的对应电极柱。
5.如权利要求1所述的存储器元件，其中所述存取元件阵列中的存取元件包括垂直晶体管；
所述多个导电层具有周边，且所述周边的相应部分经组态以与解码电路接触。
6.如权利要求1所述的存储器元件，其中所述多个导电层具有周边，且所述周边的相应部分包含经组态以与解码电路接触的翼片，且所述存储器元件包含：
上覆于所述多个导电层上的布线层，包含将所述多个导电层耦接至解码电路的导体；以及
导电插塞，接触所述翼片且向上延伸至所述布线层。
7.如权利要求6所述的存储器元件，其中所述翼片以交错方式配置，使得所述多个导电插塞中耦接至所述多个导电层中的不同导电层上的交错翼片的导电插塞以列配置，所述列在由所述交错翼片界定的方向上延伸。
8.如权利要求1所述的存储器元件，其中所述存取元件阵列下伏于所述多个导电层下。
9.如权利要求1所述的存储器元件，其中所述电极柱阵列中的电极柱包括与对应存取元件电连通的中央芯导体，以及位于所述中央芯导体上的相变存储器材料层、位于所述相变存储器材料层上且接触所述多个导电层的临界值切换材料层，其中所述相变存储器构件中的每一者包括位于所述中央芯导体与所述临界值切换材料层之间的所述界面区的所述相变存储器材料层中的主动区。
10.如权利要求1所述的存储器元件，其中所述电极柱包括电极部分的相应堆叠，其中每一部分延伸穿过一组对应的所述多个导电层。
11.一种存储器元件的制造方法，包括：
形成存取元件阵列；
在所述存取元件阵列下方或上方形成多个导电层，所述多个导电层由绝缘层而彼此分离且与所述存取元件阵列分离；
形成延伸穿过所述多个导电层的电极柱阵列，所述电极柱阵列中的所述电极柱接触所述存取元件阵列中的对应存取元件，且界定所述柱与所述多个导电层中的导电层之间的界面区；以及
在所述界面区中形成存储器构件，所述存储器构件中的每一者包括可程序化相变存储器构件以及临界值切换构件。
12.如权利要求11所述的存储器元件的制造方法，其中所述形成多个导电层的步骤包含导体材料的毯覆式沉积。
13.如权利要求12所述的存储器元件的制造方法，其中所述形成多个导电层的步骤包含：
形成多个毯覆式导体材料层；以及
在所述毯覆式导体材料层之间形成毯覆式绝缘材料层。
14.如权利要求11所述的存储器元件的制造方法，其中所述形成电极柱阵列的步骤包含：
界定穿过所述多个导电层的电极通路；
在所述电极通路的侧壁上沉积临界值切换材料层以及存储器材料层；以及
用电极材料填充所述存储器材料层上的所述电极通路。
15.如权利要求11所述的存储器元件的制造方法，其中所述形成电极柱阵列的步骤包含：
在所述多个导电层内界定电极通路；
在所述电极通路的侧壁上沉积临界值切换材料层；
在所述临界值切换材料层上形成相变存储器材料层；以及
用电极材料填充所述相变材料层上的所述电极通路。
16.如权利要求15所述的存储器元件的制造方法，其中所述用电极材料填充所述相变材料层上的所述电极通路的步骤包含：在所述相变材料层上形成电极材料薄膜，进行各向异性蚀刻以在所述电极通路中形成开口，所述开口暴露所述对应存取元件的触点，以及用所述电极材料填充所述通路及所述所得开口。
17.一种存储器元件，包括：
集成电路基板，其包含电极柱阵列以及在界面区与所述电极柱相交的多个电极平面；
位于所述界面区中的相变存储器构件，包括可程序化构件及临界值切换构件；
列解码电路及行解码电路，用以选择所述电极柱阵列中的电极柱；以及
平面解码电路，用以在选定电极平面内的所述界面区中使所述临界值切换构件偏置至导电状态，且在未选定电极平面内的界面区中使所述临界值切换构件偏置至非导电状态。
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