CN101950720B - 极度圆孔屏蔽的栅槽mosfet器件及其生产工艺 - Google Patents

极度圆孔屏蔽的栅槽mosfet器件及其生产工艺 Download PDF

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CN101950720B
CN101950720B CN2010102362511A CN201010236251A CN101950720B CN 101950720 B CN101950720 B CN 101950720B CN 2010102362511 A CN2010102362511 A CN 2010102362511A CN 201010236251 A CN201010236251 A CN 201010236251A CN 101950720 B CN101950720 B CN 101950720B
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常虹
戴嵩山
李铁生
王宇
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Chongqing Wanguo Semiconductor Technology Co ltd
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Abstract

本发明公开了一种改进的槽金属氧化物半导体场效应晶体管(MOSFET)器件，该器件包括一个被源区围绕的槽栅，源区被围绕在位于基片底面上的漏区之上的体区中。MOSFET单元进一步包括一个位于槽栅下面且与槽栅绝缘的屏蔽栅槽(SGT)结构，SGT结构基本是由一个旁向膨胀超出槽栅以及被充填有槽栅材料的介质层覆盖的圆孔组成。圆孔是通过各向同性腐蚀在槽栅底部生成的并通过氧化物绝缘层与槽栅分隔开来。圆孔的旁向膨胀超出槽壁，该旁向膨胀可用作垂直调整的界标，控制槽栅的深度。取决于位于作为槽栅之下一个圆孔的SGT结构之上的槽栅的可控深度，MOSFET器件的栅漏电容Cgd可以减小。

Description

极度圆孔屏蔽的栅槽MOSFET器件及其生产工艺
技术领域
本发明一般地涉及半导体功率器件。更具体地，本发明涉及一种改进的新型生产工艺和器件结构，能提供在硅顶面下深度得到精确控制的屏蔽槽栅，准确地减小栅漏电容。
背景技术
使用屏蔽的栅槽(SGT)结构减小DMOS(双扩散金属氧化物半导体)器件中栅漏电容(Cgd)的常规技术仍然面临着技术局限性和困难，特别是沟槽DMOS器件结构中含有槽栅，栅极与漏极之间较大的电容Cgd限制了器件的转换速度。这个电容主要是由藕联在槽栅底部与漏极之间的电场产生的，为了减小栅漏电容，在槽栅底部引入了一个改进的屏蔽栅槽(SGT)结构，使槽栅与漏极隔绝。SGT结构的设计思想是使槽的底部与源极连接，将槽栅与位于基片底部的漏极屏蔽，如图1所示。采用在槽栅底部引入SGT结构的做法可使栅漏电容Cgd比原来的减小约50％，这样，在槽栅底部引入SGT结构的DMOS器件的转换速度和转换效率也得到极大的提高。
但是，为了能够改善Cgd而实现这样的结构，必须十分注意生产工艺，特别是必须严格控制从栅槽底部时间腐蚀多晶硅。正如图1所示，支撑在具有外延层15基片10上的DMOS器件具有一个槽栅20，槽栅20包括一个注入在槽中、具有栅绝缘层45的多晶硅栅极。在槽栅20下面，还有另一个分隔开的屏蔽栅槽(SGT)结构30，它包括多晶硅，多晶硅注入在被绝缘层40与槽栅20分隔开来的槽底部空间。DMOS器件还进一步包括有作为标准DMOS器件的体区和源区50和60，槽栅底部的深度，如图1中的D所示，取决于构成SGT结构30时从槽底部部分多晶硅的腐蚀速率，仔细地控制蚀刻操作可以控制深度Do但是，由于槽顶部部分多晶硅的腐蚀速率差异，槽底部深度D不能精确地控制。
正如以上所述，即使是能够精确地控制蚀刻过程，相对于硅基片顶面的多晶硅栅极的深度也不能得到足够程度的精确控制，因为除了蚀刻时间的长短之外，槽栅底部多晶硅的蚀刻速度还取决于几个均能造成槽栅深度差异的参数，因此栅极深度差异极难控制。可是，栅极底部的深度差异直接影响器件的性能，包括栅漏电容，栅极深度差异还会进一步影响控制器件通道的难度。除非是采取特殊措施控制槽底部多晶硅的蚀刻速度以控制槽栅的深度，否则减小栅漏电容是无法真正实现的。
所以，在功率半导体器件设计和生产领域依然存在着需要提供一种新的生产方法和器件结构的要求，以便构建一种能解决上述所有问题和局限性的功率器件。
发明内容
本发明的目的是提供一种新的、改进的、使用有屏蔽栅槽(SGT)结构的半导体功率器件，SGT结构打开后为圆孔，其旁向膨胀超出槽壁，作为竖向定线的界标。槽栅的深度可用作为垂直调整的旁向膨胀进行精确的控制，从而能够精确地生产出栅漏电容，克服上面所讨论的技术困难和局限性。
具体地，本发明的目的是提供一种改进的器件结构和生产方法，能够减小栅漏电容，同时还能通过控制槽栅的深度精确地控制包括栅漏电容在内的器件参数。槽栅深度是通过生成一个从槽旁向膨胀的圆孔SGT结构，使槽栅深度能够用蚀刻时间精确地控制，而蚀刻时间采用圆孔旁向膨胀作为垂直调整的控制指标。
在一个优选实施例中，本发明公开了一种槽金属氧化物半导体场效应晶体管(MOSFET)。这种MOSFET包括一个由源区围绕的槽栅，源区被围绕在位于基片底面上的漏区上的体区中。MOSFET单元进一步包括一个位于槽栅下面且与槽栅绝缘的屏蔽栅槽(SGT)结构，生成的SGT结构基本是一个圆孔，其旁向膨胀超出槽栅并被一层充填有槽栅材料的介质层覆盖。圆孔通过各向同性腐蚀生成，位于槽栅底部，通过氧化物绝缘层与槽栅绝缘。圆孔的旁向膨胀超出槽壁，其旁向膨胀用作控制槽栅深度垂直调整的界标。取决于位于槽栅下面作为一个圆孔的SGT结构之上的槽栅的控制深度，MOSFET器件的栅漏电容Cgd被减小。
附图说明
图1显示了背景技术中具有一个常规屏蔽栅槽(SGT)结构的、使用槽栅结构的常规槽MOSFET器件的截面图；
图2显示了在槽栅下使用了根据本发明生产的圆孔SGT结构的槽MOSFET器件的截面图；
图3A一图3L是一组显示根据本发明的工艺生产一个槽MOSFET器件的截面图。
具体实施方式
为更好地理解本发明，以下结合图2和图3，详细说明本发明的较佳实施例，使得本领域的技术人员将会更加清楚地理解本发明的各种技术特征和有效技术效果。
图2是本发明的槽MOSFET器件100的截面图。槽MOSFET器件100支撑在具有外延层110的基片105上，槽MOSFET器件100包括一个屏蔽栅槽(SGT)结构130，SGT结构130打开时是一个位于槽栅150之下的圆孔屏蔽结构，在此充填有多晶硅的圆孔SGT结构130是用来通过绝缘层120将槽栅150与位于基片105之下的漏极屏蔽和绝缘，绝缘层120围绕SGT结构130和SGT结构130与槽栅150之间的氧化物层140。槽栅150包括充填到槽中的多晶硅，槽被覆盖槽壁的栅绝缘层155所围绕。体区160掺杂有第二型传导性，如P型的搀杂物，延伸在槽栅150之间。围绕源区170的P体区160掺杂有第一传导性，如N+的搀杂物，源区170位于围绕槽栅150的外延层顶面附近。半导体基片顶面上也是绝缘层、接触开口和金属层，提供源-体区以及栅极的电接触。由于这些结构业已为本领域技术人员所熟知，为了简洁起见，这些结构特征没有特别地画出，也未特别地进行讨论。
图3A-图3L是一组显示生产MOSFET器件步骤的侧面截面图，具体如图3A-图3D所示。在图3A中，槽掩模208用来在基片205上开多个槽209。在图3B中，氧化物层210生长在槽壁表面上。在图3C中，进行非各向同性氧化物腐蚀(non-isotropic oxide etch)，从槽壁底部清除氧化物层210。然后从事各向异性硅腐蚀，使槽209向下蚀刻到基片，再进行一种独特的硅圆孔腐蚀，例如各向同性硅腐蚀，打开圆孔215将槽底部延伸到图3D所示的侧面方向和垂直方向。槽底部的圆孔旁向延伸，圆孔215要比侧壁氧化物层210保护的顶部槽的宽度宽。在图3E中，进行的第二次槽氧化在底部槽孔215的侧壁上生成氧化物层220，然后多晶硅层230沉淀充填槽209和底部圆孔215。
在图3F中，进行定时的多晶硅腐蚀从槽209顶部清除多晶硅层220。在多晶硅中心进行的多晶硅回蚀(etch back)操作的差异不影响器件的性能或栅漏电容Cgd，栅漏电容是由底部多晶硅层的上边缘和通道深度决定的。在图3G中，氧化物硬掩模208清除后紧接着便是如图3H所示的第三次槽栅氧化物氧化，生成覆盖槽壁和底部圆孔230顶面的栅氧化物层240。在图31中，多晶硅进行第二次沉淀用多晶硅层250充填槽，如图3J所示，通过第二次多晶硅腐蚀回蚀覆盖基片205顶面的多晶硅层，生成顶部槽多晶硅栅250，这种第二次多晶硅回蚀与当前技术的标准工艺完全相同。然后，进行体植入和扩散工艺的准备过程(stand processes)，生成如图3K所示的P体区260。接下来进行标准源搀杂物植入和扩散工艺，生成如图3L所示的源区270。这些工艺与当前标准的槽MOS工艺相同，剩下的工艺，如接触工艺、金属工艺和钝化工艺也与当前技术相同。
在上述工艺中，由于起始材料是扁平园片，槽209的深度可以更加均匀、精确地控制。下面的非各向同性氧化物腐蚀从槽壁底部清除氧化物层210，氧化物层的清除点可为垂直方向提供一个界标，因为在接下来的各向同性硅腐蚀过程中，底部膨胀槽的上边缘会自动地调整到这一点，这个上边缘而不是多晶硅腐蚀面提供一个能控制底部栅屏蔽效应的参照点。与底部源电极的顶部由腐蚀时间控制的常规工艺比较，本申请公开的工艺提供了一种精确度更高的垂直自动调整结构，因为该结构能通过自动调整过程做到从不太容易控制的依赖时间腐蚀的多晶硅回蚀表面到一个比较精确的参照点，从而精确地得到栅控点的深度。
按照以上所述，本发明进一步公开了一种生产槽金属氧化物半导体场效应晶体管(MOSFET)器件的方法。该方法进一步包括在基片上开槽和使用介质层覆盖槽的槽壁以及接下来从槽的底部部分清除部分介质层的步骤。该方法还进一步包括利用各向同性基片腐蚀法在槽的底部部分开一个圆孔，使圆孔从槽壁侧面延伸的步骤。该方法还包括用栅材料充填槽和槽底部的圆孔，以及接下来运用时间腐蚀法(time etch)从槽的顶部部分清除栅材料，使栅材料仅充填圆孔和直到圆孔的旁向膨胀点的步骤。该方法还包括采用圆孔的旁向膨胀点作为垂直调整的界标，控制从槽的顶部部分清除栅材料的腐蚀时间，从而达到控制MOSFET器件的槽栅深度的步骤。该方法还进一步包括生成一层绝缘层用来覆盖圆孔顶面，使圆孔与槽栅分隔开来的步骤，该方法还进一步包括将栅材料充填到位于圆孔之上的槽，接下来通过回蚀工艺从基片顶面清除栅材料生成槽栅的步骤。该方法还进一步包括在槽栅周围生成一个体区和一个源区的步骤。
从本质上说，本发明进一步公开了一种生产半导体器件的方法。该方法包括沿基片垂直方向建立一个调整界标的步骤，从而提供一个可测量的控制参数，用来控制生产过程，获得具有预先设定的垂直调整指标的结构特征的步骤。该方法进一步包括开一个具有可控深度的槽的步骤。在一个特定的实施例中，该方法进一步包括沿基片垂直方向建立一个调整界标，从而提供一个可测量的控制参数，用来控制生产过程，获得具有预先设定的垂直调整指标的结构特征的步骤。这个生产方法还包括开一个具有可控深度的槽的步骤。建立一个垂直调整界标的步骤包括在槽中开一个圆孔，使其侧面膨胀超过槽壁，为垂直调整提供界标。在槽中开一个圆孔的步骤还包括在槽底部开一个圆孔以及用栅材料充填圆孔使其扮演屏蔽栅槽(SGT)结构的功能的步骤。开圆孔的步骤是采用各向同性基片腐蚀在槽底部开一个圆孔的步骤。该方法还进一步包括在充填有栅材料的圆孔顶部生成一层绝缘层，从而构建一个SGT结构，作为与槽分隔开来的结构的步骤。该方法还包括用栅材料充填槽以及从槽顶面回蚀栅材料，从而在槽中生成槽栅，使SGT结构位于槽栅之下的圆孔中的步骤。该方法还进一步包括在围绕槽栅的基片中生产一个体区和一个源区，以便生产MOSFET器件的步骤。生产MOSFET器件的步骤包括为垂直调整建立界标的步骤，建立垂直调整界标的步骤包括在槽中开一个圆孔，使其旁向膨胀超出槽壁，从而为垂直调整提供界标的步骤。
尽管本发明是用当前优选的实施例进行介绍的，但必须认识到这种介绍绝不能理解为仅局限于此。本领域技术人员在阅读上述介绍后将清楚到认识到还存在着多种变化和修改。因此，所附的权利要求被认为包括不背离本发明的精神和范围的各种这样的等效变化和修改。

Claims (6)

1.一种生产半导体器件的方法，其特征在于，包括下述步骤：
在基片中开一个具有可控深度的槽；
在所述槽中开一个圆孔，使其旁向膨胀超出槽壁，采用圆孔的旁向膨胀点作为沿基片垂直方向所建立的一个调整界标；并在充填栅材料至槽和圆孔中之后，利用圆孔的旁向膨胀点作为垂直调整的界标以控制从槽的顶部部分清除栅材料的腐蚀时间，从而提供一个利用腐蚀时间作为可测量的控制参数，用来控制生产过程，即通过腐蚀时间来控制槽栅深度，获得具有预先设定的垂直调整界标的结构特征。
2.根据权利要求1所述的方法，其特征在于，所述的在槽中开圆孔的步骤进一步包括在所述槽开一个圆孔以及用栅材料充填所述圆孔使其具有屏蔽栅槽结构的功能的步骤。
3.根据权利要求2所述的方法，其特征在于，所述开圆孔的步骤是采用各向同性基片腐蚀法在所述槽底部开一个圆孔。
4.根据权利要求3所述的方法，其特征在于，进一步包括：在充填有所述栅材料的所述圆孔顶部生成一层绝缘层，从而构建一个所述屏蔽栅槽结构，作为与所述槽分隔开来的结构。
5.根据权利要求4所述的方法，其特征在于，进一步包括：用所述栅材料充填所述槽以及从所述槽顶面回蚀所述栅材料，从而在所述槽中生成槽栅，使所述屏蔽栅槽结构位于所述槽栅之下的所述圆孔中。
6.根据权利要求5所述的方法，其特征在于，进一步包括：在围绕所述槽栅的所述基片中生成一个体区和一个源区，以生产一个MOSFET器件。
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