CN1020317C - 电气器件的制造方法 - Google Patents

电气器件的制造方法 Download PDF

Info

Publication number
CN1020317C
CN1020317C CN89103436A CN89103436A CN1020317C CN 1020317 C CN1020317 C CN 1020317C CN 89103436 A CN89103436 A CN 89103436A CN 89103436 A CN89103436 A CN 89103436A CN 1020317 C CN1020317 C CN 1020317C
Authority
CN
China
Prior art keywords
electric device
chip
substrate
wire
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN89103436A
Other languages
English (en)
Other versions
CN1039504A (zh
Inventor
山崎舜平
石田典也
坂间光
佐佐木麻里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63124360A external-priority patent/JPH01292846A/ja
Priority claimed from JP63124361A external-priority patent/JPH01292833A/ja
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of CN1039504A publication Critical patent/CN1039504A/zh
Application granted granted Critical
Publication of CN1020317C publication Critical patent/CN1020317C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

本说明书叙述了一种经过改进的电气器件的制造方法。器件的例子是一覆盖在塑模中的IC芯片，在塑模工序之前，用氮化硅涂覆IC芯片，以保护IC芯片不受通过裂纹或裂缝的水份的侵蚀。氮化硅的涂覆层是用等离子体CVD法进行的。特别是，在沉积期间，为了获得优质的氮化硅涂层，将一交流电压加到IC芯片上。

Description

本发明涉及一种电气器件的制造方法。
半导体集成电路是曾经在各种各样场合中广泛使用过的最重要的电气器件。从可靠性观点来看，这些器件的问题之一就是水份或其它杂质侵入埋置在塑模中的IC（集成电路）芯片。这种侵入是通过出现在该塑模中的裂纹或裂缝发生的，使得从塑模的外侧到IC芯片的表面形成通路。到达IC表面的水份使组成IC芯片的半导体产生不希望有的腐蚀现象，并导致芯片的失灵。
因此，本发明的一个目的是要提供一种可靠的电气器件的制造方法，这种电气器件不会受到通过密封器件的封装的裂纹或其它路径侵入的水份或其它杂质的影响。
通过下面连同参看附图的详细叙述就可从更好地理解本发明。在这些附图中，
图1是用来体现本发明的一种等离子体CVD设备的示意图。
图2（A）是一种IC芯片组件装配平面示意图。
图2（B）是沿图（2A）A-A线取得的部分横截面视图。
图2（C）是图2（A）经放大的部分视图。
现在参看图1和2（A）至2（C），图中叙述了根据本发明实施例的一种等离子体处理方法。图1展示一种等离子体CVD设备的横截面示意图。该设备包括一个沉积室1，一个通过一阀门9而连接到沉积室1的装卸室7，一对装在沉积室1中的网状或栅状电极11和11′，一个供气系统5，一个通过一阀门21而连接到沉积室1的真空泵20，以及一个通过一变压 器26在电极11和11′间供电的高频功率源10。变压器26次级线圈的中点25′是接地（25）的。供气系统包括三组流量计18和阀门19。输入到电极11和11′的高频能量引起电极间的阳极区辉光放电。辉光放电区（沉积区）限制在一个有四侧边的框架40的范围内，以避免在该区的外侧出现不希望有的沉积。框架40-它可以是一接地的金属框架或者是一绝缘的框架-由一支柱40支撑。有若干个衬底2由框架40支撑着，并以3到13厘米，例如8厘米的间隔平行置放。一组IC芯片被安装在各个组件2上。通过一偏置器件12将交流电能由一交流电源24加到组件（芯片）上。
如图2（A）和图2（B）所示，芯片组件是由固定夹具44和插放并支撑在相邻夹具之间的引线框架29组成的。IC芯片安装在引线框架29的适当位置（基板）并用Au丝39与安排在框周围的引线相连接。图2（C）展示的一种与一个芯片所需的引线相对应的框架单元结构，但芯片右侧的引线的具体说明在图中是不用赘述的。单元结构重复地沿着框架的上下导轨间的框架出现。每一框架含有5到25个单元，例如18个单元结构。一些夹具是整体组装的，以便支撑10到50个，例如10个框架，如图2（A）所示。
接着要解释根据本发明的保护性涂层方法。在完成芯片和有关引线之间的电气连接后，一些引线框架被安装在组件2上。该组件通过装卸室7以一恒定的间隔被置放在沉积室中。NH3、Si2H6和N2（携带气体）分别由进气口15、16和17以适当的压力通过喷咀3漏入沉积室1。引进的NH3/Si2H6/N2的克分子比为1/3/5。当1千瓦和1到500兆赫，例如13.56兆赫的高频能量进入一对电极11和11′时，就出现阳极区辉光放电。另一方面，100到500瓦和1-500千赫的交流偏置能量由交流电源通过偏置器件12输入到安装在组件上的芯片。结果，在芯片、引线及它们之间的连接线上就沉积了氮化硅涂层。涂层的厚度在经过10分钟的沉积后达到1000±200埃。平均的沉积速率约3埃/秒。
完成沉积后，将组件由沉积室取出，并进行塑模工序。各组件按现 状被放在塑模设备上。一种环氧树脂材料（410A）是从中心位置42（它在图2（A）中作为解释而绘出的）注入到各带有适用模子的芯片周围的适当部分，并形成芯片的外封装。从塑模设备取出组件后，通过切断引线的末端使IC脱离框架。然后，每条伸出塑模结构的引线都向下弯曲，以便形成“蜗形IC”的管脚。引线用酸清洗干净后，再用焊料涂复。
图3详细说明塑模结构中的丝线连接结构。如图所示，保护性的氮化硅薄膜27和27′复盖着装在基座35′、接点38、Au线39和包括管座35的引线37上的IC芯片28的表面。由于这个保护性的涂层，使得可以保护芯片避免水份通过模子和引线间的裂纹33或裂缝33″的侵袭。这种裂纹特别可能出现在丝线（33′）或角落边缘（33″）处。根据实验，红外（IR）吸收光谱在表示Si-N键合的864×10-7cm处显示出峰值。测得的绝缘涂层的经受电压电平是8×106伏/厘米，涂层的电阻率为2×105欧-厘米，涂层的反射率为1.7至1.8。涂层的保护能力是用HF腐蚀来评价的。腐蚀率为3到10埃/秒。这和传统的30埃/秒的氮化硅涂层（约30埃/秒）的腐蚀率数值比较起来显著地小了很多。这种优越的涂层厚度1000埃是足够的了（一般是300到5000埃）。
按本发明制造的IC器件要在10个大气压150℃下经受100小时的PCT（压力蒸煮试验）。结果，在经试验后，未发现次品，而碎片次品从50-100菲特（fit）降至5-10菲特。（1菲特指10-9失效/器件小时）
在用实例具体叙述了几个实施例的同时，要理解的是，本发明不受具体所叙述的例子的限制，在不偏离附在权利要求书中所规定的本发明保护范围的情况下，可以做出修正或改型。下面是一些例子。
类金刚石的碳、氧化硅或其它绝绝材料可以沉积以形成保护性涂层。虽然实施例举的是IC芯片，但本发明也可以用于其它电气器件，例如电阻器和电容器。此外，本发明在使用其它键合方法，例如扣焊芯片键合和焊料隆起键合（solder    bump    bonding）时也是行之有效的。

Claims (7)

1、一种制造电气器件的方法，它包括：
在一衬底上安装电气器件；
在所说电气器件的至少一个表面上形成一保护性涂层；以及
用一种树脂材料封装所说电气器件和所说衬底；
其特征在于所说保护性涂层是由下列步骤形成的：
将安装在所说衬底上的所说电气器件置放在反应室中的一对电极之间；
将一反应气体引进所说反应室；
将一高频交流电压加到所说电极对上，以便使所说反应气体转变成等离子体；
将一交流偏压加到所说衬底上；以及
在所说表面上沉积所说保护性涂层。
2、根据权利要求1的方法，其中所说衬底包括一基板和至少一有关引线。
3、根据权利要求2的方法，还包括在所说涂覆步骤之前于所说器件和所说引线之间制造电气连接的步骤。
4、根据权利要求3的方法，其中在所说器件和所说引线间的所说连接是由丝焊来实现的。
5、根据权利要求1的方法，其中所说高频交流电压的频率为1至500兆赫。
6、根据权利要求1的方法，其中所说交流偏压的频率为1至500千赫。
7、根据权利要求1的方法，其中所说保护性涂层由氮化硅、金刚石状碳和氧化硅制得。
CN89103436A 1988-05-19 1989-05-19 电气器件的制造方法 Expired - Fee Related CN1020317C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP63124360A JPH01292846A (ja) 1988-05-19 1988-05-19 電子装置作製方法
JP63124361A JPH01292833A (ja) 1988-05-19 1988-05-19 電子装置作製方法
JP124360/88 1988-05-19
JP124316/88 1988-05-19
JP124361/88 1988-05-19

Publications (2)

Publication Number Publication Date
CN1039504A CN1039504A (zh) 1990-02-07
CN1020317C true CN1020317C (zh) 1993-04-14

Family

ID=26461041

Family Applications (1)

Application Number Title Priority Date Filing Date
CN89103436A Expired - Fee Related CN1020317C (zh) 1988-05-19 1989-05-19 电气器件的制造方法

Country Status (5)

Country Link
US (1) US5096851A (zh)
EP (1) EP0342681B1 (zh)
KR (1) KR900019177A (zh)
CN (1) CN1020317C (zh)
DE (1) DE68923732T2 (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451550A (en) * 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
US5880403A (en) 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
US6613978B2 (en) * 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
KR100202668B1 (ko) * 1996-07-30 1999-07-01 구본준 크랙 방지를 위한 반도체 패키지와 그 제조방법 및 제조장치
US6368899B1 (en) * 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6432737B1 (en) 2001-01-03 2002-08-13 Amkor Technology, Inc. Method for forming a flip chip pressure sensor die package
US6441503B1 (en) 2001-01-03 2002-08-27 Amkor Technology, Inc. Bond wire pressure sensor die package
US6661080B1 (en) 2001-06-28 2003-12-09 Amkor Technology, Inc. Structure for backside saw cavity protection
US6586824B1 (en) 2001-07-26 2003-07-01 Amkor Technology, Inc. Reduced thickness packaged electronic device
US6399418B1 (en) * 2001-07-26 2002-06-04 Amkor Technology, Inc. Method for forming a reduced thickness packaged electronic device
US7382043B2 (en) * 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US20040119172A1 (en) 2002-12-18 2004-06-24 Downey Susan H. Packaged IC using insulated wire
US7191516B2 (en) * 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices
US9953952B2 (en) * 2008-08-20 2018-04-24 Infineon Technologies Ag Semiconductor device having a sealant layer including carbon directly contact the chip and the carrier
DE102016106137B4 (de) * 2016-04-04 2023-12-28 Infineon Technologies Ag Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056681A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Self-aligning package for integrated circuits
US4091407A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
JPS55163850A (en) * 1979-06-08 1980-12-20 Fujitsu Ltd Semiconductor device
JPS5627941A (en) * 1979-08-17 1981-03-18 Hitachi Ltd Manufacture of semiconductor device
JPS56108247A (en) * 1980-01-31 1981-08-27 Sanyo Electric Co Ltd Semiconductor device
JPS5745259A (en) * 1980-09-01 1982-03-15 Hitachi Ltd Resin sealing type semiconductor device
JPS57210646A (en) * 1981-06-19 1982-12-24 Seiko Epson Corp Resin-sealed semiconductor device
JPS59231840A (ja) * 1983-06-14 1984-12-26 Semiconductor Energy Lab Co Ltd 半導体装置作成方法
JPS59231810A (ja) * 1983-06-14 1984-12-26 Toshiba Corp 電子ビ−ム露光装置
JPS601846A (ja) * 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
JPS60107841A (ja) * 1983-11-16 1985-06-13 Hitachi Ltd 窒化シリコン膜の形成方法
JPS61148824A (ja) * 1984-12-21 1986-07-07 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61258436A (ja) * 1985-05-13 1986-11-15 Nec Corp 半導体装置の製造方法
US4729010A (en) * 1985-08-05 1988-03-01 Hitachi, Ltd. Integrated circuit package with low-thermal expansion lead pieces
KR920003431B1 (ko) * 1988-02-05 1992-05-01 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 플라즈마 처리 방법 및 장치

Also Published As

Publication number Publication date
EP0342681A2 (en) 1989-11-23
KR900019177A (ko) 1990-12-24
CN1039504A (zh) 1990-02-07
EP0342681B1 (en) 1995-08-09
DE68923732T2 (de) 1996-01-18
EP0342681A3 (en) 1990-07-04
DE68923732D1 (de) 1995-09-14
US5096851A (en) 1992-03-17

Similar Documents

Publication Publication Date Title
CN1020317C (zh) 电气器件的制造方法
US5147822A (en) Plasma processing method for improving a package of a semiconductor device
US5013688A (en) Method of manufacturing a semiconductor using plasma processing
US6200412B1 (en) Chemical vapor deposition system including dedicated cleaning gas injection
US5208467A (en) Semiconductor device having a film-covered packaged component
US6191492B1 (en) Electronic device including a densified region
JP3502036B2 (ja) 半導体素子の製造方法および半導体素子
US8268675B2 (en) Passivation layer for semiconductor device packaging
US5192995A (en) Electric device utilizing antioxidation film between base pad for semiconductor chip and organic encapsulating material
US5121187A (en) Electric device having a leadframe covered with an antioxidation film
US6756670B1 (en) Electronic device and its manufacturing method
JP2684387B2 (ja) 電子装置およびその作製方法
JP2802650B2 (ja) 電子装置
JPH09246431A (ja) 半導体装置及びその製造方法
JPS59231840A (ja) 半導体装置作成方法
JPH02106940A (ja) 電子装置及びその作製方法
US6537859B2 (en) Semiconductor device baking method
JPH01292833A (ja) 電子装置作製方法
JPH01292846A (ja) 電子装置作製方法
JPH01292849A (ja) 電子装置作製方法
JP2683694B2 (ja) 電子装置の作製方法
JPH0383351A (ja) 電子装置作製方法
EP0363936B1 (en) Method of manufacturing electric devices
JPH0383353A (ja) 電子装置の作製方法
JPH0260154A (ja) リードフレームおよびそれを用いた電子装置の作製方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C15 Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993)
OR01 Other related matters
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee