CN102238053A

CN102238053A - Controller area network (CAN) bus interference generator

Info

Publication number: CN102238053A
Application number: CN2010101680339A
Authority: CN
Inventors: 吴宝红; 莫莽; 刘矗
Original assignee: SHANGHAI GUTAI TECHNOLOGY Co Ltd
Current assignee: SHANGHAI GUTAI TECHNOLOGY Co Ltd
Priority date: 2010-05-06
Filing date: 2010-05-06
Publication date: 2011-11-09

Abstract

The invention discloses a controller area network (CAN) bus interference generator, which aims to the service conditions of a CAN bus node or a CAN bus system under the conditions of digital interference, logic errors, analogue interference and physical layer failures and the capability of recovery of the CAN bus node or the CAN bus system from various errors or failures. The CAN bus interference generator consists of three parts which are a bit stream resolution part, a digital interference injection circuit and a resistance capacitance matrix respectively. The CAN bus digital interference injection circuit in the CAN bus interference generator realizes the injection of each kind of digital logic interference into a CAN bus by the series connection of a pair of triodes and the parallel connection of the pair of triodes with CAN transceivers CAN_H and CAN_L. The resistance capacitance matrix in the CAN bus interference generator stimulates the physical layer failures such as the short-circuiting of the CAN_H and the CAN_L, the circuit-breaking of one or two certain lines in the CAN bus, the load increasing of the bus, the short-circuiting of a certain line in the CAN bus with battery voltage, and the like by the various of resistance values and capacitance values in the resistance capacitance matrix.

Description

A kind of CAN bus interferance generator

Affiliated technical field:

The present invention relates to a kind of CAN of being used for (Controller Area Network controller local area network) bus test process and produce digital interference and logic error, and the physical layer fault that the CAN bus is applied the various CAN bus protocol regulations of simulation interference simulation, be used for investigating CAN bus node or CAN bus system in digital interference and logic error, and simulation disturbs and the physical layer fault, working condition under the situation and the CAN bus interferance generator of recovery capability under various mistakes and the malfunction.

Background technology:

The CAN bus is because its high-performance and reliability are widely used in aspects such as industrial automation, boats and ships, Medical Devices.Especially at vehicle electric field, the CAN bus often is used as in the dynamical system network directly related with safety, and is therefore, particularly important for the testing authentication work of CAN bus system and CAN bus node.For the reliability of testing, verify designed CAN bus system or CAN bus node and in the logic error of various CAN bus standard defineds and the working condition under the physical layer failure condition, with the ability of recovering down from mistake or failure condition, need a kind of CAN bus interferance generator of design to come that tested CAN bus system or CAN bus node are injected configurable digital interference and simulation interference and go to simulate and realize different mistakes and malfunction.

Summary of the invention:

In order to realize injection to CAN bus system or CAN bus node simulation interference and Digital Logic interference, the designed a kind of CAN bus interferance generator of the present invention mainly constitutes (as Fig. 1) by three parts, promptly be used to resolve bit stream that transmits on the bus and the bit stream that carries out the interference triggered condition judgment and resolve part, be used to apply the digital interference injection circuit that Digital Logic is disturbed, and be used for applying the resistance capacitance matrix that simulation disturbs can regulating circuit resistance capacitance value simulates the different physical layer faults of CAN bus protocol defined.

CAN bus digital interference injection circuit among the present invention as shown in Figure 2, the series connection by a pair of triode also realizes injection that the various Digital Logic of CAN bus are disturbed with CAN transceiver CAN_H and CAN_L in parallel.

Resistance capacitance matrix among the present invention as shown in Figure 3, by the variation of resistance value, capacitance in the resistance capacitance matrix, remove to simulate in CAN_H and CAN_L short circuit, the CAN bus a certain line or certain two line opens circuit, bus load increases, physical layer fault such as a certain line and cell voltage short circuit in the CAN bus.

Description of drawings:

Fig. 1 CAN bus interferance generator structured flowchart.

Fig. 2 CAN bus digital interference injection circuit schematic diagram.

Fig. 3 resistance capacitance matrix circuit schematic diagram.

Fig. 4 resistance capacitance resistance matrix constitutes schematic diagram.

Fig. 5 resistance capacitance matrix electric capacity constitutes schematic diagram

Embodiment:

The designed a kind of CAN bus interferance generator of the present invention is resolved part by being used to resolve bit stream that transmits on the bus and the bit stream that carries out the interference triggered condition judgment, be used to apply the digital interference injection circuit that Digital Logic is disturbed, and be used for applying resistance capacitance matrix three parts that simulation disturbs can regulating circuit resistance capacitance value simulates the different physical layer faults of CAN bus protocol defined and form (as Fig. 1).

The circuit theory diagrams of the digital interference among the present invention as shown in Figure 2, Q1, Q2 are that a pair of triode of NPN and PNP that is respectively is to pipe among the figure, their emitter directly links to each other and links to each other with the 2.5V power supply, the collector electrode of Q1 and Q2 respectively with the CAN_H pin and the parallel connection of CAN_L pin of CAN transceiver, insert CAN_H and CAN_L line in the CAN network after the parallel connection respectively, by combination, the CAN bus is forced to write logic " height " and logic " low " or the CAN bus is presented " high resistant " state the high low value of logic level of the TXD pin of CAN transceiver and Q1, Q2 base stage.

Resistance capacitance matrix circuit schematic diagram among the present invention as shown in Figure 3, among the figure can connect and insert in the tested CAN network in CAN1, CAN2 place, each resistance among the figure all is composed in series as behind a series of switches (relay) of Fig. 4 and respective resistance values resistance in parallel, is formed in parallel after the capacitances in series of the variable capacitance CHL among Fig. 3 by a series of switches (relay) among Fig. 5 and corresponding capacitance value.In Fig. 4, the resistance R of single resistance _i=R _Step-length* 2 ⁱ(wherein i=0～10), thus among Fig. 3 the resistance of each resistance can by among Fig. 4 to the control break of relay, its excursion is 0～(2 ^I+1-1) * R _Step-length, the resistance change step-length is R _Step-lengthIn Fig. 5, the capacitance of single electric capacity is C _i=C _Step-length* 2 ⁱ(wherein i=0～5) are so the capacitance scope of the capacitor C HL among Fig. 3 is 0～(2 ^I+1-1) * C _Step-length, the capacitance variation step-length is C _Step-length

The course of work of a kind of CAN bus interferance generator that the present invention is designed is: CAN bus interferance generator is resolved part by its bit stream and in real time the bit stream that is transmitted on the CAN bus is resolved to logical message, in case institute's information transmitted satisfies the interference triggered condition that the user disposes on the bus, CAN bus interferance generator just is applied to pre-configured interference sequence on the tested bus by digital interference injection circuit or resistance capacitance matrix.

Claims

1. CAN bus interferance generator, it is characterized in that: it is made up of the parsing of CAN bus bit stream, digital interference injection circuit, resistance capacitance matrix three parts.

2. according to claim 1 the digital interference injection circuit is described, it is characterized in that: a pair of NPN and PNP triode are directly connected on the 2.5V power supply the emitter of pipe, and the collector electrode of NPN triode and PNP triode is connected with CAN L pin with the CAN H pin of CAN transceiver respectively.TXD pin by the CAN transceiver and two triodes are realized the CAN bus is forced to write logic " height ", logic " low " and the CAN bus is presented high-impedance state to the combination of pipe base stage logic level height.

3. according to claim 1 the resistance capacitance matrix is described, it is characterized in that: the resistance capacitance matrix externally has two interfaces of CAN1, CAN2, each interface has two lines to pick out, and is respectively CAN1_H, CAN1_L and CAN2_H, CAN2_L, is connected variable resistor R between CAN1_H and power supply or the ground _H, be connected variable resistor R between CAN1_H and the CAN2_H _SH, be connected variable resistor R between CAN1_H and the CAN1_L _HL, be connected variable resistor R between CAN1_L and power supply or the ground _L, be connected variable resistor R between CAN1_L and the CAN2_L _SL, connect variable capacitance C between CAN2_H and the CAN2_L _HLEach variable resistor in the resistance capacitance matrix is composed in series the resistance R of single resistance again by behind a series of switches (relay) and respective resistance values resistance in parallel _i=R _Step-length* 2 ⁱ(wherein i is a nonnegative integer), wherein R _Step-lengthBe any resistance value.Variable capacitance in the resistance capacitance matrix composes in parallel the capacitance C of single electric capacity again by after the connecting of the electric capacity of a series of switches (relay) and corresponding capacitance value _i=C _Step-length* 2 ⁱ(wherein i is a nonnegative integer), wherein C _Step-lengthBe any capacitance.