CN102272916A - 具有熔丝型硅通孔的3d芯片叠层 - Google Patents

具有熔丝型硅通孔的3d芯片叠层 Download PDF

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CN102272916A
CN102272916A CN2009801543021A CN200980154302A CN102272916A CN 102272916 A CN102272916 A CN 102272916A CN 2009801543021 A CN2009801543021 A CN 2009801543021A CN 200980154302 A CN200980154302 A CN 200980154302A CN 102272916 A CN102272916 A CN 102272916A
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chip
silicon
hole
control circuit
tsv
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CN102272916B (zh
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王平川
冯凯棣
L·L-C·许
杨志坚
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International Business Machines Corp
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    • H01L2924/3011—Impedance

Abstract

在硅芯片中的可编程熔丝型硅通孔(TSV)具有在相同芯片中的不可编程TSV。所述可编程熔丝型TSV可利用在TSV结构内的具有侧壁间隔物的区域，该侧壁间隔物限制了邻近芯片表面接触衬垫的TSV的横截导电路径。通过编程电路施加充足电流会造成金属的电迁移，从而在所述接触衬垫中产生孔隙，因而造成开放电路。编程可通过多层芯片叠层中的两个邻近芯片上的互补电路来实施。

Description

具有熔丝型硅通孔的3D芯片叠层
技术领域
本发明涉及一种具有熔丝型硅通孔(TSV，“Through silicon via”)结构的三维(3D)芯片叠层，尤指一种具有用于承载垂直穿过半导体管芯的电子信号的可编程熔丝型TSV结构的三维芯片叠层。
背景技术
在电子器件的封装当中，例如半导体芯片和晶片，或半导体芯片载体，至下一封装层级的垂直互连，不论其为芯片载体或堆叠的芯片，皆可由硅通孔(TSV)达成。公知由多种技术来产生TSV。叠层芯片为多层芯片结构，有时候称为三维芯片叠层，其允许缩小管芯间的信号传输距离，并可大为增加在管芯之间建立的链接的数目。
这种小尺寸封装由使用TSV结构的三维芯片叠层所提供时，其为多种应用所高度需要，例如，移动电话、数字相机、PDA、GPS、膝上型计算机等等。这些应用的持续成长需要不懈的努力来提高效能、扩展功能、降低成本并增加封装密度。
这类结构的困难之一为当该三维叠层被装配时，芯片之间的该等互连由预制的TSV所形成。结果，一旦被装配，便不可能改变这些TSV的状态。然而，为了修理、编程、改变状态以及重定线(rerouting)的目的，需要具有可打开原先短路的TSV线的能力。
发明内容
根据本发明的具体实施例，方法与器件用于提供一种可编程设置，其可允许例如通过程序控制电路打开芯片之间的原先闭合或短路的TSV链接。
本发明的实施例通常涉及用于芯片配置的可编程熔丝型TSV。可运用具有可编程熔丝型TSV的层叠芯片，其亦提供在其中该可编程熔丝型TSV可通过控制电路被编程的其它配置，如存在于邻近芯片中的，例如一起协作以选择性打开该芯片中的TSV。芯片可以同时包括可编程熔丝型TSV，以及永久式，即，不可编程TSV。
在本发明的实施例中，一种电子封装包括至少一个芯片，其具有用于至其它电子结构的芯片互连的至少一个可编程熔丝型TSV过孔结构。
在该电子封装的其它方面中；
该可编程熔丝型TSV结构包括在该至少一个TSV结构的过孔的一部分内形成的过孔开口中的横截面减小的导电材料的区域；
该可编程熔丝型TSV结构系通过控制电路从低阻抗状态被编程成高阻抗状态，所述控制电路控制通过在所述至少一个TSV结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料的电流流动；
所述电流流动由形成在彼此层叠的至少两个芯片中的每一个中的控制电路所控制；
在所述至少两个芯片中的每一个中的功能性电路在编程操作期间通过隔离电路与所述控制电路解耦；
在编程操作期间，在所述至少两个芯片中的一者中的所述控制电路，控制进入在所述至少一个TSV结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料中的所述电流流动水平，并感测所述熔丝型结构何时由所述低阻抗状态成为所述高阻抗状态；以及
在编程操作期间，在所述至少两个芯片中的另一者内的所述控制电路，控制从所述至少一个TSV结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料流出的所述电流流动。
在另一实施例中，提供一种电子封装，其包括多个层叠的芯片，其由TSV所互连，至少一部分TSV可由熔丝型结构编程，所述熔丝型结构响应于由跨邻近芯片的设置的编程控制电路所启始的通过所述熔丝型结构的充足的电流流动，在未编程状态下提供一个阻抗值，而在编程状态下提供另一阻抗值。
在又一实施例中，提供一种用于编程芯片叠层中的用以互连芯片的可TSV的方法，其通过：
提供具有横截面减小的导电材料的区域的至少一个TSV；
将充足水平的电流提供到具有横截面缩小的导电材料的区域的所述至少一个TSV的一端以在所述导电材料中形成孔隙，从而产生高阻抗状态；
控制从具有横截面缩小的导电材料的区域的所述至少一个TSV的另一端流出的所述电流；
感测所述至少一个TSV何时被编程到所述高阻抗状态；以及
当编程完时从该至少一个TSV去除该电流。
用于编程可编程TSV的方法的其它方面包括：
所述将电流提供到所述至少一个TSV的一端的步骤通过所述芯片叠层中的一个芯片提供，以及所述控制从所述至少一个TSV的另一端流出的所述电流的步骤通过所述芯片层叠中的另一芯片来控制；以及
将至少一个芯片和另一芯片中的功能性电路与将电流提供到所述至少一个TSV的一端和控制流出所述至少一个TSV的另一端的所述电流的所述步骤隔离的又一步骤。
在另一实施例中，提供了一种在芯片中制造可编程硅通孔的方法，所述方法包括：在芯片上形成器件与电路，包括用于编程所述芯片中的至少一个硅通孔的控制电路；形成互连所述器件和电路的金属化和电介质，包括在所述电介质的表面处的用于互连用以编程所述至少一个TSV的所述控制电路的金属化；在所述芯片中形成导电TSV，用于将所述芯片垂直互连至其它电子装置；在所述导电TSV中的至少一者的过孔内形成可编程材料，其包括所述导电TSV的横截面减小的导电材料的区域以形成所述可编程TSV；在所述可编程材料与用于编程所述可编程TSV的所述控制电路之间形成导电连接。
用于在该芯片中制造可编程TSV的方法的另一方面包括：
包括横截面减小的导电材料的区域的该可编程材料通过提供绝缘材料的过孔侧壁间隔物而形成；
通过以下步骤形成所述侧壁间隔物：
去除所述至少一个导电通孔的过孔内的导电材料的一部分，以在所述芯片的活性表面处形成凹陷；
在所述凹陷中沉积绝缘材料层；以及
方向性干蚀刻所述绝缘材料以在所述绝缘材料中的其底部区域形成受限制的开口(restricted opening)；
所述附加控制电路被设置成互补于形成在另一芯片的所述器件和电路内的所述另一芯片中的额外控制电路；
形成从所述另一芯片中的所述额外控制电路到在所述另一芯片的冶金层中的表面接触衬垫的电连接；
所述芯片与所述另一芯片彼此层叠，以便所述另一芯片的所述表面接触衬垫被电连接至所述芯片的所述可编程TSV；
用导电材料填充所述受限制的开口，以形成所述横截面缩小的导电材料的区域；以及
所述导电材料延伸超过所述电介质的表面之上的所述开口到所述电介质的所述表面处的所述金属化，以在所述可编程材料与用于编程所述可编程TSV的所述控制电路之间形成所述导电连接的至少一部分。
附图说明
图1显示一对层叠的芯片，其中之一包括可编程熔丝型TSV结构。
图2显示具有包括由前段制程所形成的器件与电路的第一层与包括形成于后段制程的金属化的第二层的芯片。
图3显示形成在图2的芯片中的过孔。
图4显示图3的芯片结构，其具有绝缘材料的共形层，以及用导电材料填充以形成导电TSV的过孔。
图5显示图4的芯片结构，其具有回蚀刻的TSV的一部分，以在该TSV结构中形成凹陷。
图6显示图5的芯片结构，其具有在该凹陷中形成的侧壁间隔物。
图7显示图6的芯片结构，其具有形成在电介质中并对准于TSV的开口。
图8显示图7的芯片结构，其具有形成在电介质开口中的接触衬垫。
图9显示图8的芯片结构，其由从背侧的减薄晶片而产生。
图10显示一对彼此层叠的芯片。
图11显示该熔丝型结构如何操作。
图12A显示芯片叠层结构的概视图，其中一些芯片具有编程熔丝型TSV和不可编程TSV。
图12B显示可编程熔丝型TSV与在一对层叠的芯片上的可用于编程该熔丝型TSV的相关部件的示意图。
图12C显示在一对层叠的芯片上的可用于编程该熔丝型TSV的熔丝编程和控制电路的电路简图。
图12D显示用于控制图12C的编程和控制电路的操作的一系列电压波形。
具体实施方式
请参照图1，其所示为层叠的芯片结构3的具体实施例。虽然显示两个芯片，在该芯片叠层中很明显的可层叠两个以上的芯片。此外，该设置很明显的可位于晶片层级。芯片1与2同时包括导电硅通孔(TSV)，其中芯片1具有不可编程(即，常规的)TSV 5和可编程熔丝型TSV 7。芯片2包括两个不可编程TSV 9与10。显然，虽然该TSV代表“硅”通孔，但该通孔亦可只存在于除了硅之外的材料中。显然，在芯片中可以包括额外的TSV。
通常，这些芯片可在该芯片层级制造，而使用前段(FEOL，“Front endof line″)制程分别在芯片1与2的层11与13中形成标准器件与电路。然后使用后段(BEOL，“Back end of line”)制程分别在芯片1与2的层15与17中形成互连与电介质。在层15与17中所包括的为金属接触19与21，其连接至编程控制电路，其在以下会有更详细的解释。为了方便起见，接触19与21在FEOL层11与13中形成时，仅有效地显示成包括器件的电路的一部分，但此处未示出。此编程控制电路可于FEOL制程期间形成(将在稍后解释)并可为互补，其中该编程控制电路的一部分可以在芯片1中，而该编程控制电路的另一部分可以在芯片2中。除了编程控制电路之外，接触19与21连接至在FEOL制程期间所形成的芯片功能性电路。因此，接触19与21用于将在FEOL层11与13中的两种电路互连至TSV金属接触22与24。
该编程控制电路被设计为通过使熔丝结构23由低阻抗或闭合状态进入到高阻抗或开放状态，来控制可编程熔丝型TSV 7的编程。该编程控制电路典型地与该功能性电路(即，设计用于芯片操作的电路，例如逻辑、存储器等等)分离。在芯片1与2中的接触26与28分别将FEOL层11与13中的功能性电路互连至各不可编程TSV 5与9。
熔丝型结构23可为多种熔丝型结构中的任一种。在可被采用的熔丝型结构中包含那些涉及基于金属化的、一次性可编程、设置在具有侧壁间隔物的过孔内的电熔丝结构来限定该过孔导体的导电横截面面积的结构。这种设置由图1的熔丝型结构23所表示。
因此，如图1所示，绝缘层25与27形成在芯片1与2上，其具有设置成允许形成接触22、24、29与31以连接至各导电TSV 7、10、5与9的凹陷。熔丝型结构23形成在TSV 7中的凹陷中，以互连接触22与TSV7的导电材料8。
请参照图2，显示在硅层51上制造具有层35的芯片结构41。层35包括由多种FEOL制程中任一种所制造的器件与电路结构。形成在层35上的层37包括由多种BEOL制程中任一种所制造的金属互连与介电层。
除了为了芯片效能所形成的该功能性电路之外，编程控制与感测电路以及电源亦可被制造在层35中，用于控制该可编程熔丝型TSV的编程。此控制电路的互连类似地被形成在层37中，其具有连接至此芯片的编程控制电路的接触39与40中的一者或二者上的金属。金属接触39与40亦连接至芯片功能性电路。上保护层43与下保护层45被形成在该芯片结构上。
虽然此处用该芯片层级处的制造来说明，当应了解在该晶片层级可以实施用于制造各种芯片结构的制程。典型地，该晶片在晶片减薄之后可被切割成芯片，例如参照图9。
保护层43与45可为多种保护材料中的任何一种，例如由常规沉积制程所形成的氧化物层或氮化物层或两者兼具。请参照图3，然后使用例如光致抗蚀剂掩模(未示出)以允许TSV 47与49开口在上保护层43、BEOL层37、FEOL层35与硅层51中被蚀刻。
TSV 47与49开口例如可为圆形，直径为1到100μm，深度为20到200μm。在此处例如可使用深反应性离子蚀刻(RIE，“Reactive ion etch”)法来形成TSV 47与49开口。因此，如本领域中所公知，可采用在等离子体中产生的氟基进行的深硅蚀刻。如图3所示，蚀刻终止于作为蚀刻停止层的保护层45处。然而，蚀刻很明显的可终止于硅晶层51中其它选择的点(如稍后解释)，该硅晶体的背侧研磨用于暴露TSV 47与49开口。
在形成TSV 47与49开口之后，在芯片结构41上沉积绝缘材料的共形层，以便涂敷芯片表面、TSV 47与49开口的侧壁表面与底壁表面。该绝缘材料的共形层可以被回蚀刻以从保护层43的表面去除材料，留下该绝缘材料层作为TSV 47与49开口的侧壁与底壁表面上的绝缘衬里53。可选地，该绝缘材料层可利用下一个金属化步骤从保护层43的表面去除，这显示于图4。该绝缘材料的衬里53可为氧化物、氮化物、TEOS、PSG等等中的任何一种。该共形层被沉积，以便该绝缘薄膜沿过孔或沟槽侧壁的厚度为充分均匀。该涂敷使用多种已知的沉积技术来实施，例如化学气相沉积(CVD，“Chemical vapor deposition″)，CVD典型地可提供良好的共形性。
另外如图4所示，在形成绝缘材料的衬里53之后，金属层，例如铝、铜、钨或掺杂有铜的铝，被沉积在芯片结构41上，以便填充蚀刻的TSV 47与49开口。该填充被实施为不在TSV开口中留下孔隙。存在多种已知的沉积技术用来在该芯片结构上形成金属，以便均匀地填充过孔，包括例如CVD与电镀。
在芯片结构41上沉积该金属层以填充TSV 47与49开口之后，可自芯片结构41顶部向下到保护层43去除过多的金属与绝缘材料(保留在其上的)。这可使用化学机械抛光(CMP，“Chemical-mechanical polishing”)制程完成，其停止在保护层43的上表面处，后者作为CMP蚀刻停止层。因此，金属层与绝缘材料层两者可自芯片结构41的上表面去除，留下暴露于该表面处的金属填充的TSV 47与49形成导体55。
如图5所示，然后，抗蚀剂层或接触掩模57形成在芯片结构41的顶表面上。该掩模可为光致抗蚀剂掩模，其被构图而在TSV 47之上形成开口59。该开口可延伸超过填充的TSV 47的宽度(如图所示)，或可与该TSV的横截面开口共同延伸。
然后，RIE制程可用于回蚀刻金属填充的TSV 47中的导体55，以在TSV 47中形成凹陷60，如图5所示。该蚀刻制程由计时控制，以形成深度为1到10μm的凹陷60。虽然未示出，该蚀刻制程可去除一些由沉积绝缘材料的共形层53所形成的侧壁电介质，除了来自BEOL层37的所有绝缘材料之外。请注意该蚀刻制程亦可原位地(in-situ)以数个步骤进行，而不需要破坏真空。因为有数个不同材料层，包括金属、共形层、电介质等要去除，每个材料层接着可在单独的步骤中被蚀刻。在蚀刻之后，去除抗蚀剂层57。
图6与图7显示可用于形成例如图1所示的TSV熔丝型结构的制程。但是，为此目的可使用多种熔丝型结构的任何一种。为了形成这种结构，如图6所示，绝缘材料的毯层(blanket layer)被沉积在芯片结构41上，以覆盖保护层43的表面，并共形地沉积在凹陷60的内。此材料可例如为Si3N4或SiO2。方向性干蚀刻，例如物理溅射，则可用于自保护层43的表面及凹陷60的底部去除该绝缘层，在该凹陷的壁上留下锥形的侧壁间隔物61。例如当该过孔开口为圆形时，该间隔物将为圆形。
由此形成的该间隔物或多个间隔物用于限制或减小该过孔开口的横截面面积。此窄化的开口62，亦称为颈部区域，依此用于限制或减小可填充过孔47的金属的横截面。于编程期间，电流拥挤效应将在该颈部区域中发生，并造成金属材料随着电子风移动，造成孔隙或开口。根据电子流动方向，该孔隙会发生在靠近该颈部的不同区域中，如图11所示。该目标为要在编程后打开该连接。
图7与图8显示为在由侧壁间隔物61限制的该开口中形成导电材料，及在该芯片的表面处形成导电接触衬垫的步骤。在图7中，介电层63被沉积在保护层43上。然后，在该介电层上沉积抗蚀剂层65，然后，被构图以在过孔47与49之上形成开口67与69。然后开口67与69通过蚀刻，例如通过RIE，于介电层63与保护层43中被呈现出来。该RIE制程在蚀刻通过所有的保护层43之后停止，以暴露接触39与40。该蚀刻制程被选择性地完成，所以诸如金属接触39与40和过孔金属55的金属不会被蚀刻。
虽然在图式中未示出，当保护层43、衬里53与间隔物61为相同材料时，蚀刻可以将衬里53与侧壁间隔物61减小至BEOL层37的表面平面。但是，这不会影响该熔丝型结构的操作。但是当材料不同时，选择性蚀刻将会将这些材料留在其适当的位置。
如图8所示，在去除抗蚀剂层65之后，电接触衬垫71与73被形成在介电层63的开口67与69中。这可通过在芯片结构41上沉积金属的共形层来完成，其足以填充开口67与69，然后通过化学机械抛光，去除在介电绝缘层63的表面上的金属以在凹陷的开口67与69中形成接触衬垫71与73。可选地，构图的金属毯层，例如使用抗蚀剂层65来构图该金属，可被沉积在开口67与69中，以形成接触衬垫71与73。如图8所示，该沉积为用于制造电连接至金属接触39与40。除了金属被沉积在凹陷67与69中之外，同时金属被沉积在凹陷60的由侧壁间隔物61所限制的窄化的开口或区域62中。
因此，如图8所示，用金属填充在绝缘层63中的凹陷开口67与69以在该凹陷中形成接触71与73，并延伸到金属接触39与40之上。此外，所沉积的金属往下延伸到由侧壁间隔物61所限制的窄化的开口或区域62，以构成与TSV 47中的导电材料55的电接触。如上所述，所使用的金属优选地是对应于在TSV 47与49及电路接触39与40中所使用的相同种类的金属。因此，该TSV与接触可填充例如铝、铜、钨或掺杂有铝的铜中的任何一种，然后在此处所选择要形成接触71与73的金属基本上将为相同的材料。
如图9所示，然后即可实施自硅51的背侧的晶片减薄来减薄芯片结构41。在先前的图式中所示的TSV延伸到保护层45，因此在此例中，减薄涉及去除位于TSV的底部处的保护层45与绝缘衬里材料53来暴露在该TSV中的金属55。当该TSV延伸到低于芯片层51的厚度时，额外的硅将有必要被去除以暴露该TSV。典型地，在减薄之后，该芯片层厚度的范围将在20μ到200μ的间。硅减薄亦可在稍早的制程中实施，以形成可编程TSV。硅减薄的实施例如可使用背侧研磨和/或TMA蚀刻，如图9的箭头所示。
在晶片减薄之后，所得到的具有熔丝型可编程TSV 47的芯片可被层叠在其它芯片上，这些芯片可具有或不具有可编程熔丝型TSV。图10显示两个这种层叠的芯片。芯片1包括熔丝型可编程TSV 47及标准或不可编程TSV 49。层叠在芯片1上的芯片2包括两个不可编程TSV 77与79。典型地，该两个芯片除了用于制造该熔丝型结构的步骤之外，通常使用相同的材料和制造制程。
芯片2可使用无黏着剂的方法接合到芯片1，其中可运用室温下的共价接合。可选地，亦可使用利用黏着剂、压力和/或热的接合技术。
另外如图10所示，在BEOL层83中的金属接触81连接至FEOL层85中的编程控制电路与功能性电路。金属接触81亦连接至金属接触87，后者连同接触89可由镶嵌制程所形成，类似用于在芯片1中形成金属接触71与73的制程。如所示，金属接触87接合至可编程TSV 47。如稍早所述，在芯片1中的金属接触39同时连接至FEOL层35中的编程控制电路与功能性电路。因此，编程控制电路被连接至可编程TSV 47的相对端部。
再者，请参照图10，在芯片2中的TSV 79层叠在芯片1中的TSV 49上。因此，在该两个芯片之间可构成垂直不可编程互连。另一方面，可编程TSV 47仅在被编程这样做时，切断该两个芯片之间的连接。显而易见，其它芯片可层叠在芯片1与2上，且所有层叠的芯片具有任何数目的不同的不可编程与可编程熔丝型TSV的组合。
图11显示的方式为可编程熔丝型TSV 47在当被编程时，操作为从闭合或低阻抗状态到开放或高阻抗状态。在芯片1与2中的FEOL层35与85中的编程控制电路用于使得电流流动到芯片2中的接触81，穿过金属接触87并进入到芯片1中的TSV 47，然后通过熔丝型结构23到接触71与39，而将接触39连接至芯片1中的编程控制电路。该电流具有足够的量值而造成在该窄化的开口或颈部区域62及金属接触71中的电迁移，使得在靠近侧壁间隔物61的颈部区域处产生孔隙(如所示)。如上所述，该熔丝为双向性可编程熔丝，其代表电流可在任一方向上流动来开放熔丝。如图11所示，此孔隙产生开放电路因而切断该电流路径。虽然参照了间隔物61，但显然，该过孔具有圆形横截面，间隔物61将为环绕该圆形过孔的壁的一个连续间隔物。
图12A显示芯片叠层配置的概视图，其中至少一些芯片具有可编程与不可编程熔丝型TSV。虽然所示为五个芯片的叠层，此仅为例示性目的，如上所述，有可能具有可编程与不可编程熔丝型TSV的任何芯片组合。例如芯片1具有以88与90显示的两个熔丝型TSV。另一方面，芯片3并不具有任何熔丝型TSV，虽然典型地其可以具有。亦如上所述，横跨一对在各芯片中具有互补式电路的芯片来完成TSV的编程。因此，可见于图12A，例如在虚线区块91内的可编程TSV 89具有芯片5中的编程控制电路93与芯片4中的编程控制电路95。类似的编程控制电路的方案显示为可编程熔丝型TSV 88、90与101。很明显的，在可编程熔丝型TSV 89之上和之下的TSV 103、105、107与109为构成直接连接的常规、不可编程TSV，例如芯片1、2与3中所示。类似的直接连接被示出例如为在可编程熔丝型TSV 88之上的该直接连接的TSV的其它线路。
图12B显示在一对层叠的芯片上的该电路设置的示意图。芯片1包括可编程TSV熔丝111、感测电路113、功能性电路115与编程电路117。芯片2包括感测电路119、功能性电路121与编程电路123。开关125与127作为隔离开关，以隔离该功能性电路与该编程及感测电路。来自各芯片的编程与感测电路共同用于编程TSV熔丝111。编程电路117与123通过闭合开关118与120以产生充足的电流通过TSV熔丝111，藉此在芯片1与芯片2之间构成非易失性开放电路路径，因此用于编程TSV熔丝111。该感测电路用于判定TSV熔丝111何时被编程，由此断开开关118与120来切断该电流来源。
在图12C中，所示为用于实施横跨一对芯片的熔丝型TSV的编程的更详细的电路具体实施例。芯片1中的可编程TSV熔丝111连接于芯片2中的X节点与芯片1中的Y节点之间。TSV熔丝111可为图12A中的可编程TSV中的任何一者，例如TSV 88。互补式编程电压信号“PROA”与“PROB”，如图12D的时序波形所示，被施加到可编程区块130与132内的各互补型开关129与131。开关129可为nMOSFET，而开关131为pMOSFET。这些电压用于打开开关，并使得来自电流源133的电流通过TSV熔丝111到接地。
同时，电压信号“PROA”被施加到互补的p型开关135与n型开关137，以隔离芯片2功能性电路139与区块132中的编程电路。在区块141中提供的类似电路用于隔离芯片1中的功能性电路与区块130中的编程电路。
当TSV熔丝111接收充足的电流来产生孔隙与开放电路时，如参照图11所述，节点X处的电压电平增加，且比较器143在当控制信号CHECKB被设定为逻辑低时感测节点X处的电压增加，并在当节点X处的电压超过Vth时提供逻辑高的输出信号，其中该Vth为预先定义的阈值电压。该操作由进入到逻辑低电平脉冲的“CHECKB”电压实施，如图12D所示。该脉冲被施加于p型FET 144的栅极电极，好将其开启，并连接节点X的电压电平至比较器143的正输入。如果TSV熔丝111已经被编程，其电阻为高(例如500欧姆或更高)，且节点X处的电压高于比较器143处负输入的Vth，藉此产生指示熔丝结构111已经成功地被编程的逻辑高的比较器输出信号。如图12D所示，当“PROA”信号变低，“PROB”信号变高且CHECKB信号变高时，该编程操作完成。
应注意TSV熔丝111在当该接触结构中的金属(例如图11中的接触结构71)电迁移时变成打开以产生孔隙与开放电路。此为充分高的电流被施加横跨该结构的结果。因此，芯片1与2中的互补式编程控制电路用于施加充分高的电流来造成TSV熔丝侧壁间隔物61之间的窄化的电流路径与金属接触71之间的开放电路，如图11所示。虽然互补式编程控制电路被描述成被分开在两个芯片之间，但显然，该互补式编程控制电路的一部分连同熔丝型TSV可存在于一个芯片中，而这种互补式编程控制电路的其它部分可存在于除了芯片之外的电子装置内。
此处所使用的术语的目的仅在于说明特定具体实施例，并非要作为本发明的限制。如此处所使用者，单数形式的“一”、“一个”以及“这个”也包括复数形式，除非在文中另有明确指明。另外，应该了解，在本说明书中当用到术语“包含”和/或“包括”时指定存在有所述的特征、整数(integer)、步骤、操作、元件和/或部件，但并不排除存在或加入一个或多个其它特征、整数(integer)、步骤、操作、元件、部件和/或其群组。
在以下申请专利范围中所有手段或步骤加上功能部件的相对应结构、材料、动作及同等者，为要包括用于执行结合如特定主张的其它主张的部件的功能的任何结构、材料或动作。本发明的说明已为了例示及描述的目的而呈现，其并非为毫无遗漏或受限于本发明于所揭示的形式。本领域的技术人员将可了解到在不背离本发明的范围与精神的下可有许多修改及变化。该等具体实施例的选择及其说明，为要最佳地解释本发明的原理及其实际应用，藉此使得本领域的其它技术人员可针对多种具体实施例来了解本发明，并依照所考虑的特定用途而做出适当的多种修改。

Claims (25)

1.一种电子封装，其包含：
至少一个芯片，其具有用于到其它电子结构的芯片互连的至少一个可编程熔丝型硅通孔结构。
2.根据权利要求1的电子封装，其中所述可编程熔丝型硅通孔结构在在所述至少一个硅通孔结构的过孔的一部分内形成的过孔开口中具有横截面减小的导电材料。
3.根据权利要求2的电子封装，其中所述可编程熔丝型硅通孔结构通过控制电路从低阻抗状态被编程到高阻抗状态，所述控制电路控制通过在所述至少一个硅通孔结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料的电流流动。
4.根据权利要求3的电子封装，其中所述电流流动由形成在彼此层叠的至少两个芯片中的每一个中的控制电路所控制。
5.根据权利要求4的电子封装，其中在所述至少两个芯片中的每一个中的功能性电路在编程操作期间通过隔离电路与所述控制电路解耦。
6.根据权利要求5的电子封装，其中在编程操作期间，在所述至少两个芯片中的一者中的所述控制电路，控制进入在所述至少一个硅通孔结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料中的所述电流流动水平，并感测所述熔丝型结构何时由所述低阻抗状态成为所述高阻抗状态。
7.根据权利要求6的电子封装，其中在编程操作期间，在所述至少两个芯片中的另一者内的所述控制电路，控制从所述至少一个硅通孔结构的所述过孔的一部分内形成的所述过孔开口中的所述横截面减小的导电材料流出的所述电流流动。
8.根据权利要求4的电子封装，其包含：
多个层叠的芯片，其由硅通孔所互连，至少一部分硅通孔可由熔丝型结构编程，所述熔丝型结构响应于由跨邻近芯片设置的编程控制电路所启始的通过所述熔丝型结构的充足的电流流动，在未编程状态下提供一个阻抗值，而在编程状态下提供另一阻抗值。
9.根据权利要求8的电子封装，其中所述熔丝型结构为非易失性结构，其包括横截面减小的导电材料的过孔区域，通过一个芯片中的控制流动到所述横截面减小的导电材料的区域中的电流的控制电路以及邻近芯片中的控制流出所述横截面减小的导电材料的区域的电流的控制电路，所述非易失性结构可从低阻抗值状态被编程到高阻抗值状态。
10.根据权利要求9的电子封装，其中在所述一个芯片与所述邻近芯片中的功能性电路在编程控制操作期间与控制电路隔离。
11.根据权利要求10的电子封装，其中在所述一个芯片中的所述控制电路内的感测电路用于感测所述非易失性结构何时被编程到所述高阻抗状态，并由此切断流动到所述横截面减小的导电材料的区域中的电流。
12.一种在芯片中制造可编程硅通孔的方法，所述方法包括：
在芯片上形成器件与电路，包括用于编程所述芯片中的至少一个硅通孔的控制电路；
形成互连所述器件和电路的金属化和电介质，包括在所述电介质的表面处的用于互连用以编程所述至少一个硅通孔的所述控制电路的金属化；
在所述芯片中形成导电硅通孔，用于将所述芯片垂直互连至其它电子装置；
在所述导电硅通孔中的至少一者的过孔内形成可编程材料，其包括所述导电硅通孔的横截面减小的导电材料的区域以形成可编程硅通孔；
在所述可编程材料与用于编程所述可编程硅通孔的所述控制电路之间形成导电连接。
13.根据权利要求12的方法，其中所述形成包括横截面减小的导电材料的区域的可编程材料的步骤通过提供绝缘材料的过孔侧壁间隔物而实施。
14.根据权利要求13的方法，其中所述绝缘材料的过孔侧壁间隔物通过以下步骤形成：
去除所述至少一个导电通孔的过孔内的导电材料的一部分，以在所述芯片的活性表面处形成凹陷；
在所述凹陷中沉积绝缘材料层；以及
方向性干蚀刻所述绝缘材料以在所述绝缘材料中的其底部区域形成受限制的开口。
15.根据权利要求14的方法，其中所述干蚀刻形成向下延伸到所述受限制的开口的侧壁间隔物。
16.根据权利要求15的方法，其中所述控制电路被设置成互补于形成在另一芯片的所述器件和电路内的所述另一芯片中的额外控制电路。
17.根据权利要求16的方法，其中形成从所述另一芯片中的所述额外控制电路到在所述另一芯片的冶金层中的表面接触衬垫的电连接。
18.根据权利要求17的方法，其中在所述芯片中的所述控制电路与在所述另一芯片中的所述额外控制电路包括用于在编程期间隔离每个芯片中的功能性芯片电路与每个芯片中的所述编程控制电路的电路。
19.根据权利要求18的方法，其中至少所述芯片与所述另一芯片彼此层叠，以便所述另一芯片的所述表面接触衬垫被电连接至所述芯片的所述可编程硅通孔。
20.根据权利要求14的方法，其中所述在所述凹陷中沉积绝缘材料层的步骤包括选自Si3N4或SiO2的绝缘材料层的毯沉积的步骤，以及所述方向性干蚀刻所述绝缘材料的步骤包括溅射所述凹陷内的所述绝缘材料层以形成所述受限制的开口。
21.根据权利要求20的方法，其中用导电材料填充所述受限制的开口，以形成所述横截面缩小的导电材料的区域。
22.根据权利要求21的方法，其中所述导电材料延伸超过所述电介质的表面之上的所述开口到所述电介质的所述表面处的所述金属化，以在所述可编程材料与用于编程所述可编程硅通孔的所述控制电路之间形成所述导电连接的至少一部分。
23.一种用于编程芯片叠层中的用以互连芯片的根据权利要求12到22中任意一项的方法制造的可编程硅通孔的方法：
提供具有横截面减小的导电材料的区域的至少一个硅通孔；
将充足水平的电流提供到具有横截面缩小的导电材料的区域的所述至少一个硅晶过孔的一端以在所述导电材料中形成孔隙，从而产生高阻抗状态；
控制从具有横截面缩小的导电材料的区域的所述至少一个硅通孔的另一端流出的所述电流；以及
感测所述至少一个硅通孔何时被编程到所述高阻抗状态。
24.根据权利要求23的方法，其中所述将电流提供到所述至少一个硅通孔的一端的步骤通过所述芯片叠层中的一个芯片提供，以及所述控制从所述至少一个硅通孔的另一端流出的所述电流的步骤通过所述芯片层叠中的另一芯片来控制。
25.根据权利要求24的方法，包括将至少一个芯片和另一芯片中的功能性电路与将电流提供到所述至少一个硅通孔的一端和控制流出所述至少一个硅通孔的另一端的所述电流的所述步骤隔离的又一步骤。
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