CN102316177B - Address resolution method, system thereof and address resolution device - Google Patents
Address resolution method, system thereof and address resolution device Download PDFInfo
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- CN102316177B CN102316177B CN201110277798.0A CN201110277798A CN102316177B CN 102316177 B CN102316177 B CN 102316177B CN 201110277798 A CN201110277798 A CN 201110277798A CN 102316177 B CN102316177 B CN 102316177B
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Abstract
The invention provides an address resolution method, a system thereof and an address resolution device. The method comprises the following steps: switching an access address in an access frame sent by a management device into an address of each physical layer chip, and correspondingly sending the switched access address to each physical layer chip through a channel corresponding to each physical layer chip; resolving the access address, determining a physical layer chip corresponding to the access address, and sending a data segment in the access frame sent by the management device to the physical layer chip corresponding to the access address through the channel corresponding to the physical layer chip corresponding to the access address. The address resolution device comprises a switching module and a resolution module. The address resolution system comprises the management device, physical layer chips and the address resolution device. According to the invention, real-time access of a PHY chip by the management device is realized.
Description
Technical field
The present invention relates to technology, relate in particular to a kind of address resolution method, system and address resolver.
Background technology
In exchange board structure, medium access control (Media Access Control; Hereinafter to be referred as: MAC) chip and physical layer (Physical Layer; Hereinafter to be referred as: PHY) chip is two important component parts, and MAC mainly completes the forwarding exchange work of message, and PHY chip mainly completes the conversion of physical interface signal.At equipment, conventionally pass through serial management interface (Serial Management Interface; Hereinafter to be referred as: SMI) PHY chip is managed, SMI is for comprising a management data clock (Management Data Clock; Hereinafter to be referred as: MDC) with management data input and output (Management Data Input Output; Hereinafter to be referred as: synchronous serial interface MDIO).Conventionally the SMI interface SMI interface corresponding with PHY that adopts MAC chip to carry connects, and by MAC chip, directly accesses PHY chip.When needs are managed a plurality of PHY simultaneously, all PHY are all connected on the same SMI interface of same MAC, and because each PHY has oneself a address, MAC accesses different PHY according to different addresses.But because the address of standard protocol specifies PHY only has 5, i.e. 32 PHY of multipotency management of SMI interface, and the address of each PHY under same SMI interface can not conflict mutually, otherwise cannot access, thereby bring great design restriction.In addition, along with the function of MAC chip is progressively powerful, some MAC chip possesses the mechanism of automatic access PHY, to reduce the operation of software, but this function is the fixing PHY address of restriction conventionally, be that the PHY address that the PHY that connects under SMI interface need to meet MAC chip defined arranges, cannot freely configure the PHY address under SMI interface, thereby limit the extensibility of module and the flexibility of design.
In order to address the above problem, in prior art, common way for increasing one-level interface change-over device on SMI interface, tension management equipment is first accessed this interface change-over device, again by the lower PHY chip of hanging of interface change-over device access, be that interface change-over device first arrives this locality by data receiver, carry out again corresponding address switchover, data are sent to PHY chip.
In prior art, increased address switchover process, made tension management equipment cannot access in real time PHY chip, and tension management equipment need to be made corresponding sequential adaptation.
Summary of the invention
The invention provides a kind of address resolution method, system and address resolver, realize the real time access of management equipment to PHY chip, and management equipment is without carrying out extra sequential adaptation, improves the upgrading scalability of equipment, has higher flexibility.
The invention provides a kind of address resolution method, comprising:
Reference address in the access frame that management equipment is sent switches to respectively the address of each physical chip, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip;
Resolve described reference address, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address.
The invention provides a kind of address resolver, comprising:
Handover module, for the reference address of the access frame of management equipment transmission being switched to respectively to the address of each physical chip, and issues each physical chip by the reference address after switching by passage corresponding to each physical chip accordingly;
Parsing module, be used for resolving described reference address, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address.
The invention provides a kind of address resolution system, comprise management equipment, physical chip and address above mentioned resolver.
Address resolution method provided by the invention, system and address resolver, by the reference address in the access frame that management equipment is sent, switch to respectively the address of each PHY chip, and the reference address after switching is issued to each physical chip accordingly, according to the corresponding relation between reference address and the address of PHY chip, the data segment in the access frame that management equipment is sent sends to the PHY chip corresponding with this reference address; The present embodiment is resolved reference address wherein in real time when receiving access frame, and to corresponding PHY transmission, realized the real time access of management equipment to PHY chip, and management equipment adapts to without carrying out extra sequential, the upgrading scalability that has improved equipment, has higher flexibility.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flow chart of address resolution method embodiment mono-of the present invention;
Fig. 2 is the flow chart of address resolution method embodiment bis-of the present invention;
Fig. 3 is the circuit modular structure schematic diagram of SMI address resolver in address resolution method embodiment bis-of the present invention;
Fig. 4 is the signal intensity schematic diagram in address resolution method embodiment bis-of the present invention;
Fig. 5 is the structural representation of address resolver embodiment mono-of the present invention;
Fig. 6 is the structural representation of address resolver embodiment bis-of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the flow chart of address resolution method embodiment mono-of the present invention, and as shown in Figure 1, the present embodiment provides a kind of address resolution method, can specifically comprise the steps:
Step 101, the reference address in the access frame that management equipment is sent switches to respectively the address of each physical chip, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip.
Management equipment in the present embodiment can be specially MAC chip, the present embodiment arranges a SMI address resolver between management equipment and PHY chip, in SMI address resolver, be provided with a plurality of ports, each port connects respectively a corresponding PHY chip, and corresponding implication refers to that this PHY chip exists corresponding relation with the address of the port of the SMI address resolver being connected herein.Management equipment realizes the access to PHY chip by the address resolution of SMI address resolver, during a PHY chip of management apparatus access, to SMI address resolver, send access frame, the reference address in access frame is the address of the corresponding ports of SMI address resolver.In the access frame that SMI address resolver sends at receiving management equipment, this access frame is transmitted to PHY chip, SMI address resolver is carried out identification and analysis to each bit of access frame, when receiving the reference address of accessing in frame, this reference address is switched to respectively to the address of each PHY, and the reference address after switching is issued to each PHY chip accordingly by passage corresponding to each PHY chip.In the present embodiment, an access frame can be comprised of wherein frame head, reference address and data segment, before SMI address resolver receives the reference address in access frame, the frame head in access frame, by the passage corresponding with each PHY chip, is transferred to respectively each PHY chip.
Particularly, the above-mentioned steps in the present embodiment 101 can specifically comprise the steps: to generate output control signal according to the frame head of the access frame of management equipment transmission; According to described output control signal, the reference address in described access frame is switched to respectively to the address of physical chip.
More specifically, the step that each bit of the access frame sending according to management equipment described above generates output control signal can specifically comprise the steps: the access frame with the next synchronous receiving management equipment transmission of rising edge of management data clock, when a continuous N bit of frame head all meets the front M position in default frame structure in recognizing described access frame, output control signal is switched to the second bit value by the first bit value; When recognize after being transmitted described M bit of frame head in described access frame N position reference address time, output control signal is switched to described the first bit value by described the second bit value; Wherein, described M is the number of bits of default frame head, and described N is the number of bits of default reference address.
More specifically, the step that according to described output control signal, the reference address in described access frame is switched to respectively to the address of physical chip described above can specifically comprise the steps:, when described management data clock occurs that trailing edge changes, to generate the address switchover signal of synchronizeing with described output control signal; When described management data clock does not occur that trailing edge changes, maintain described address switchover signal constant; When described address switchover signal is described the first bit value, the frame head in the access frame that transfer management equipment sends in each passage; When described address switchover signal switches to described the second bit value by described the first bit value, the reference address of the access frame transmitting in each passage is switched to respectively to the address of the physical chip corresponding with described passage; When described address switchover signal switches to described the first bit value by described the second bit value, trigger the operation of the data segment in the access frame that transfer management equipment sends in each passage.
Step 102, resolve described reference address, determine the physical chip corresponding with described reference address, the data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address.
After SMI address resolver receives the reference address in access frame, SMI address resolver is according to the corresponding relation between default reference address and the address of PHY chip, and in conjunction with this reference address, resolve described reference address, determine the physical chip corresponding with described reference address, this corresponding relation is the address of port of SMI address resolver and the corresponding relation between the address of PHY chip.SMI address resolver, by controlling the passage corresponding with this PHY chip, sends to this PHY chip in real time by the data segment in the follow-up access frame receiving, and no longer the data segment in access frame is sent to other PHY chips, realizes the accurate transmission of data.
Particularly, reference address in the access frame that above-mentioned steps 102 in the present embodiment can specifically comprise the steps: to send according to management equipment and the corresponding relation between reference address and the address of physical chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal; According to passage corresponding to physical chip corresponding with reference address described in the lasting conducting of described address resolution gating signal, close the passage that other physical chips are corresponding, so that the data segment in described access frame is sent to the described physical chip corresponding with reference address by corresponding passage.
The present embodiment provides a kind of address resolution method, by the reference address in the access frame that management equipment is sent, switch to respectively the address of each PHY chip, and the reference address after switching is issued to each physical chip accordingly, according to the corresponding relation between reference address and the address of PHY chip, the data segment in the access frame that management equipment is sent sends to the PHY chip corresponding with this reference address; The present embodiment is resolved reference address wherein in real time when receiving access frame, and to corresponding PHY transmission, realized the real time access of management equipment to PHY chip, and management equipment adapts to without carrying out extra sequential, the upgrading scalability that has improved equipment, has higher flexibility.
Fig. 2 is the flow chart of address resolution method embodiment bis-of the present invention, and as shown in Figure 2, the present embodiment provides a kind of address resolution method, can specifically comprise the steps:
Step 201, the frame head of the access frame sending according to management equipment generates output control signal.
Fig. 3 is the circuit modular structure schematic diagram of SMI address resolver in address resolution method embodiment bis-of the present invention, and as shown in Figure 3, the SMI address resolver in the present embodiment can specifically adopt the concrete structure in figure.SMI address resolver in the present embodiment can comprise a plurality of ports, correspondingly connect a plurality of PHY chips, suppose that the SMI address resolver in the present embodiment comprises 3 ports herein, each port is connected with 1 PHY chip respectively, be PHYl, PHY2, PHY3, the address of PHY is 5 bit address.Correspondingly, this SMI address resolver can comprise frame identification module, d type flip flop, 3 gates, 35 bit shift register and 3 switches.In the present embodiment, the signal that management equipment is transmitted to SMI address resolver by the bus being connected with SMI address resolver simultaneously comprises MDC and MDIO, and MDC is for controlling the clock (～CLK) of each circuit module work.
In the present embodiment, access frame can consist of frame head, reference address and data segment successively, and this step can be specially frame identification module and generate output control signal according to the frame head of the access frame of management equipment transmission.Particularly, management equipment sends MDIO to SMI address resolver, and the MDIO that frame identification module comes synchronous receiving management equipment to send with the rising edge of～CLK, obtains access frame.Frame identification module in the present embodiment is mainly used in identifying SMI interface standard access frame, in the present embodiment referred to as access frame, the frame structure of this access frame is the structure of normalized definition, and the access of all SMI all adopts two kinds of frame structures as shown in table 1 below to read and write:
The frame structure of table 1 access frame
In upper table 1, field " 32-Bit PRE " represents 32 leading, field " 2-Bit Start of Frame " represents the frame beginning flag of 2, field " 2-Bit OpCode " represents the command code of 2, field " 5-BitPHY Addr " represents the PHY address of 5, field " 5-BitReg Addr " represents the register address of 5, field " 2-BitTA " represents the state switching mark position of 2, be used to indicate the switching of current read-write state, field " 16-BitData Field " represents the data field of 16, field " Idle " represents idle, represent in SMI bus without any communication data.Wherein, field " 32-Bit pRE ", " 2-Bit Start of Frame " and " 2-Bit OpCode " can form the frame head in access frame, field " 5-Bit PHY Addr " can be the reference address in access frame, and field " 5-Bit Reg Addr ", " 2-Bit TA ", " 16-Bit Data Field " and " Idle " can form the data segment in access frame.
In this step, when frame identification module recognizes in access frame that the continuous N bit of frame head all meets the front M position of presetting in frame structure, frame identification module switches to the second bit value by output control signal by the first bit value.Default frame structure herein can be specially the frame structure shown in table 1, and M is the number of bits of default frame head, and M is specially 36 herein, and the first bit value in the present embodiment is specially 0, the second bit value and is specially 1.When frame identification module recognizes continuous 36 while meeting first 36 of any one frame structure in table 1 of from the access frame that management equipment receives frame head, represent now to have received a standard SMI frame, and next will transmit the PHY address of 5 for accessing corresponding PHY chip, will to export control signal be 1 by 0 to frame identification module, and the OC in Fig. 3 is output as 1.
When frame identification module recognizes the N bit address section after being transmitted described M bit of frame head in described access frame, output control signal is switched to described the first bit value by described the second bit value.Wherein, N is the number of bits of default address field, and owing to supposing in the present embodiment that reference address is 5 bit address, N herein can be specially 5.When frame identification module recognizes 5 reference address after finishing receiving 36 bits of accessing frame head in frame, show that 5 PHY addresses that next MDIO transmits are transmitted, frame identification module switches to 0 by output control signal by 1, and the OC in Fig. 3 is output as 0.
Step 202, according to described output control signal calculated address switching signal.
This step can be specially d type flip flop according to output control signal calculated address switching signal, and as can be seen from Figure 3, output control signal is from the input D input of d type flip flop, and address switchover signal is from the output Q output of d type flip flop.Frame identification module outputs to output control signal in d type flip flop, inputs synchronizing clock signals～CLK in d type flip flop simultaneously.When d type flip flop input～CLK is while occurring being changed by 1 to 0 trailing edge, the output valve of the output Q of d type flip flop equals the input value of input D; When d type flip flop input～CLK is when change without trailing edge, the output valve of the output Q of d type flip flop keeps initial value constant.From above-mentioned steps, frame identification module is before recognizing address field, and the value of output control signal is 0, and when recognizing address field, the value of output control signal is 1, and after recognizing address field and having finished receiving, output control signal is 0; Correspondingly, the output valve of the output Q of d type flip flop, address switchover signal, is 1 in the time period also finishing receiving to this address field from the address field receiving access frame, all the other are 0 constantly.
Step 203, according to the access frame transmitting in described each passage of address switchover signal controlling, will access reference address in frame and switch to respectively the address of the physical chip corresponding with described passage in each passage.
As can be seen from Figure 3, the output valve of the output Q of d type flip flop is input in 3 gates and 35 bit shift register simultaneously.This step can be specially gate according to the address switchover signal of its input s input, controls the access frame transmitting in each passage, will in each passage, access reference address in frame and switch to respectively the address of the PHY chip corresponding with passage.In the present embodiment, the access frame of management equipment transmission can be transferred to respectively by 3 passages a path of 3 gates, gate is also provided with another one path, this path is connected with the output of corresponding 5 bit shift register, gate can be according to address switching signal, and the road direction in the signal receiving in different two paths of time period selection is exported outward.Particularly, when the address switchover signal of the input s of gate input is 1, the path that this gate is selected is that input b is directly connected to output c; When the address switchover signal of the input s of gate input is 0, the path that this gate is selected is that input a is directly connected to output c.
As can be seen from Figure 3, the address switchover signal of d type flip flop output is also input in the input en of 5 bit shift register simultaneously.In 5 bit shift register, preserve respectively different original preset values, this original preset value is the address of PHY chip corresponding to this 5 bit shift register.Wherein, the address of PHY1, PHY2, PHY3 chip is respectively 0x1,0x2,0x3,5 bit shift register 1,5 bit shift register 2,5 bit shift register 3 are corresponding with PHY1, PHY2, PHY3 chip respectively, and the original preset value of 5 bit shift register 1,5 bit shift register 2,5 bit shift register 3 is respectively 00001,00010,00011.In 5 bit shift register, input～trailing edge that CLK occurs by 1 to 0 changes, and now its input en's is input as at 1 o'clock, the address switchover signal that is d type flip flop output is 1 o'clock, the inside of 5 bit shift register will be carried out by gt original preset value, and the lowest order of current intrinsic value is outputed on the output out of 5 bit shift register.For example, the original preset value of supposing 5 bit shift register is 00101, and now the output valve of its output out is 1; When a trailing edge occurs for～CLK, the intrinsic value of 5 bit shift register becomes 00010, and now the output valve of its output out is 0; When a trailing edge occurs again for～CLK, intrinsic value becomes 00001, and now the output valve of its output out is 1; By that analogy, when～CLK 4 trailing edge saltus steps occurs, exports respectively 5 bit data of inner original preset value at the output out of 5 bit shift register from low to high.When the input en of 5 bit shift register be input as 0 time, its intrinsic value reverts to original preset value, and whether no matter～CLK change, intrinsic value all remains unchanged, its output out is output as the lowest order of 5 original preset values.
In the present embodiment, each gate, under the control of the address switchover signal of d type flip flop output, selects to connect a-c path or b-c path; While connecting a-c path, the original bit information comprising in access frame is transmitted the PHY chip continuing by gate to corresponding; While connecting b-c path, by the bit information of the original preset value of preserving in 5 bit shift register (being the address of corresponding PHY chip) to corresponding PHY chip transmission.In the present embodiment, from the reference address receiving access frame, starting to receive in the process finishing to each bit of reference address, the address switchover signal of d type flip flop output is 1, control each gate and connect b-c path, access the address that reference address in frame is switched to respectively the PHY chip that each gate is corresponding.
Step 204, the reference address in the access frame sending according to management equipment and the corresponding relation between reference address and the address of physical chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal.
In the present embodiment, when frame identification module recognizes the transmission that completes reference address in access frame, and by gate, the reference address of the access frame transmitting in each passage is switched to respectively behind the address of each corresponding PHY chip, frame identification module also further calculated address is resolved gating signal.Reference address in the access frame that frame identification module specifically sends according to management equipment and the corresponding relation between reference address and the address of PHY chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal.In the present embodiment, the corresponding relation between reference address and the address of PHY chip can preset, and is kept in frame identification module.Corresponding relation herein can be specially, and reference address 0x4,0x5,0x6 are corresponding one by one with address 0x1,0x2, the 0x3 of PHY chip respectively.After the reference address of frame identification module in identifying access frame, according to this reference address, just can get the address of the PHY chip corresponding with it, frame identification module just can calculated address be resolved gating signal 1,2,3 according to corresponding result, and address resolution gating signal 1,2,3 is respectively used to control the transmission of accessing the data of frame in follow-up each passage.For example, when identifying reference address and be 0x4, the address that frame identification module gets its corresponding PHY chip is 0x1, corresponding with PHY1, generating the address resolution gating signal 1 corresponding with PHY1 is 1, and the address resolution gating signal 2,3 that all the other PHY2, PHY3 are corresponding is 0.
Step 205, controls the data segment in the access frame transmitting in each passage, so that this data segment is sent to the physical chip corresponding with reference address by corresponding passage according to described address resolution gating signal.
This step is that frame identification module is according to the address resolution gating signal generating, control the data segment in the access frame transmitting in each passage, continue passage corresponding to physical chip corresponding with reference address described in conducting, close the passage that other physical chips are corresponding, so that the data segment in access frame is sent to physical chip by corresponding passage.Particularly, as shown in Figure 3, frame identification module can specifically output to the address resolution gating signal of generation in the switch on each passage, controls conducting or the disconnection of each switch by this address resolution gating signal.When address resolution gating signal is 1, keep this switch to continue conducting, when address resolution gating signal is 0, by this switching over, be off-state.For example, when the address gating signal 1,2,3 generating is respectively 1,0,0, make switch 1 continue conducting, switch 2,3 is all switched to off-state.Thus, can realize the data segment transmission in access frame is arrived to PHY1, and can not be transferred to PHY2, PHY3.In the present embodiment, when frame identification module is identifying after reference address, continue to receive after 23 MDC clocks, frame identification module calculated address is resolved gating signal 1,2,3 and is 1, make the whole conductings of switch 1,2,3, represented the process of a frame identification.
Below in conjunction with the running of whole SMI address resolver, the address 0x4 of take is example to the address resolution of 0x1, and the Operational Mechanisms of lower whole SMI address resolver is described.When MAC access PHY address 0x4, actual transmissions is arrived to the frame that the access frame real-time transform of PHY1 is access 0x1, and send to PHY1, mutual between MAC and PHY1, and, for all the other PHY chips, to not receive correct access frame, thereby MAC is not responded.
Fig. 4 is the signal intensity schematic diagram in address resolution method embodiment bis-of the present invention, as shown in Figure 4, the clock signal that MDC (MAC) sends from MAC, MDIO (MAC) represents the data-signal sending from MAC, OC represents the output control signal of frame identification module output, out1 represents the signal of 5 bit shift register 1 outputs, c1 represents the signal of gate 1 output, MDIO (PHY1) represents the signal that PHY1 receives, MDIO (PHY2) represents the signal that PHY2 receives, and MDIO (PHY3) represents the signal that PHY3 receives.As shown in Figure 4, when MAC 00100 while initiating read operation, will send MDIO (MAC) signal in Fig. 4, and frame identification module will detect at each MDC (MAC) rising edge the data of MDIO to PHY address.When frame identification module detects last bit manipulation code, by sending OC, it is 1 signal (as 0 to 1 saltus step occurs when the rising edge of the MDC of last 0 correspondence of command code the OC in Fig. 4), and when ensuing MDC trailing edge, d type flip flop locks this OC signal, and the address switchover signal in output map.Now, under the control of address switchover signal, will open the displacement output function of 5 bit shift register, and the path of gate 1 is switched in the output of 5 bit shift register 1.As Fig. 4, when address switching signal is 1, often carry out a MDC trailing edge, out1 sends default actual PHY address (00001) order, i.e., after the proper operation code that c1 output MAC sends, will switch output 00001, and this is representing address resolution procedure.Meanwhile, after PHY address is sent completely, frame identification module is resolved gating signal by OPADD, closing switch 2 and 3.Now PHY2 and PHY3 will not receive follow-up SMI frame, so it can not give a response this visit, as the MDIO in Fig. 4 (PHY1) and MDIO (PHY2), before PHY address is sent completely, correct data will be exported according to said process, and after address is sent completely, interface is closed, two MDIO signals will become high-impedance state.And after last position, PHY address is sent completely, address switchover signal also will become 0 from 1, the MDIO that the output c1 of gate 1 is connected to MAC is upper, makes MAC can continue the register read to PHY1.
The present embodiment provides a kind of address resolution method, by the reference address in the access frame that management equipment is sent, switch to respectively the address of each PHY chip, and the reference address after switching is issued to each physical chip accordingly, according to the corresponding relation between reference address and the address of PHY chip, the data segment in the access frame that management equipment is sent sends to the PHY chip corresponding with this reference address; The present embodiment is resolved reference address wherein in real time when receiving access frame, and to corresponding PHY transmission, realized the real time access of management equipment to PHY chip, and management equipment adapts to without carrying out extra sequential, the upgrading scalability that has improved equipment, has higher flexibility.The present embodiment carries out real time parsing to reference address, therefore can not cause the variation of SMI interface accessing sequential, compatible traditional SMI interface index analysis principle completely, can not destroy the SMI interface sequence index of original chip, there is extremely strong real-time, portable strong.When management equipment, send after access frame, corresponding PHY chip can receive this access frame in real time, without waiting for that SMI address resolver finishes receiving.In addition, the present embodiment is used easy hardware circuit just can realize, and cost is low, realization is easy, reliability is low, without increasing extra sequential adjustment; Can freely configure it and resolve corresponding relation, be very easy to expanded application, improve the flexibility of design.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the relevant hardware of program command, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Fig. 5 is the structural representation of address resolver embodiment mono-of the present invention, and as shown in Figure 5, the present embodiment provides a kind of address resolver, can specifically carry out each step in said method embodiment mono-, repeats no more herein.The address resolver that the present embodiment provides can be specially SMI address resolver, can specifically comprise handover module 501 and parsing module 502.Wherein, parsing module 501 switches to respectively the address of each physical chip for the reference address of access frame that management equipment is sent, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip.Sending module 502 is for resolving described reference address, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address.Wherein, the handover module 501 in the present embodiment can specifically adopt frame identification module, d type flip flop, gate and 5 bit shift register in Fig. 3 to realize, and parsing module 502 can specifically adopt frame identification module and the switch in Fig. 3 to realize.
Fig. 6 is the structural representation of address resolver embodiment bis-of the present invention, and as shown in Figure 6, the present embodiment provides a kind of address resolver, can specifically carry out each step in said method embodiment bis-, repeats no more herein.The address resolver that the present embodiment provides can be specially the SMI address resolver in Fig. 3, and on the basis shown in Fig. 5, handover module 501 can specifically comprise the first frame recognin module 511 and switching submodule 521.Wherein, the first frame recognin module 511 is for generating output control signal according to the frame head of the access frame of management equipment transmission.Switching submodule 521 is for the reference address of described access frame being switched to respectively to the address of physical chip according to described output control signal, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip.Wherein, this first frame recognin module 511 can be included in the frame identification module shown in Fig. 3, and switching submodule 521 can specifically adopt d type flip flop, gate and 5 bit shift register in Fig. 3 to realize.
Further, the first frame recognin module 511 in the present embodiment can specifically comprise the first recognition unit 5111 and the second recognition unit 5112.Wherein, the access frame that the first recognition unit 5111 comes synchronous receiving management equipment to send for the rising edge with management data clock, when a continuous N bit of frame head all meets the front M position in default frame structure in recognizing described access frame, output control signal is switched to the second bit value by the first bit value.The second recognition unit 5112 during for reference address address, N position when recognizing after being transmitted described M bit of described access frame frame head, switches to described the first bit value by output control signal by described the second bit value.Wherein, described M is the number of bits of default frame head, and described N is the number of bits of default reference address.
Further, the switching submodule in the present embodiment 521 can specifically comprise trigger element 5211 and gating unit 5212.Wherein, when trigger element 5211 changes for there is trailing edge when described management data clock, generate the address switchover signal of synchronizeing with described output control signal; When described management data clock does not occur that trailing edge changes, maintain described address switchover signal constant.Gating unit 5212 is for when described address switchover signal is described the first bit value, the frame head in the access frame that transfer management equipment sends in each passage; When described address switchover signal switches to described the second bit value by described the first bit value, the reference address of the access frame transmitting in each passage is switched to respectively to the address of the physical chip corresponding with described passage; When described address switchover signal switches to described the first bit value by described the second bit value, the operation of the data segment in the triggering access frame that transfer management equipment sends in each passage, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip.Wherein, trigger element 5211 can be specially the d type flip flop shown in above-mentioned Fig. 3, gating unit 5212 can be specially the gate shown in above-mentioned Fig. 3, and the parsing that gating unit 5212 specifically completes address under the shift register shown in Fig. 3 auxiliary is switched.
Particularly, parsing module 502 can specifically comprise the second frame recognin module 512 and passage control submodule 522.Wherein, the second frame recognin module 512 is for the reference address of the access frame that sends according to management equipment and the corresponding relation between reference address and the address of physical chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal.Passage is controlled submodule 522 for continue passage corresponding to physical chip corresponding with reference address described in conducting according to described address resolution gating signal, close the passage that other physical chips are corresponding, so that the data segment in described access frame is sent to the described physical chip corresponding with reference address by corresponding passage.Wherein, this second frame recognin module 512 also can be included in the frame identification module shown in Fig. 3, and passage is controlled submodule 522 and can specifically be adopted the switch in Fig. 3 to realize.
The present embodiment provides a kind of address resolver, by the reference address in the access frame that management equipment is sent, switch to respectively the address of each PHY chip, and the reference address after switching is issued to each physical chip accordingly, according to the corresponding relation between reference address and the address of PHY chip, the data segment in the access frame that management equipment is sent sends to the PHY chip corresponding with this reference address; The present embodiment is resolved reference address wherein in real time when receiving access frame, and to corresponding PHY transmission, realized the real time access of management equipment to PHY chip, and management equipment adapts to without carrying out extra sequential, the upgrading scalability that has improved equipment, has higher flexibility.
The present embodiment also provides a kind of address resolution system, can specifically comprise the address resolver shown in management equipment, physical chip and above-mentioned Fig. 5 or Fig. 6.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. an address resolution method, is characterized in that, comprising:
Reference address in the access frame that management equipment is sent switches to respectively the address of each physical chip, and the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip;
Resolve described reference address, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address;
Wherein, the address that the reference address in the described access frame that management equipment is sent switches to respectively each physical chip comprises:
The frame head of the access frame sending according to management equipment generates output control signal;
According to described output control signal, the reference address in described access frame is switched to respectively to the address of physical chip.
2. method according to claim 1, is characterized in that, the frame head of the described access frame sending according to management equipment generates output control signal and comprises:
With the rising edge of management data clock, carry out the access frame of synchronous receiving management equipment transmission, when a continuous N bit of frame head all meets the front M position in default frame structure in recognizing described access frame, output control signal is switched to the second bit value by the first bit value;
When recognize after being transmitted described M bit of frame head in described access frame N position reference address time, output control signal is switched to described the first bit value by described the second bit value;
Wherein, described M is the number of bits of default frame head, and described N is the number of bits of default reference address.
3. method according to claim 2, is characterized in that, the described address that reference address in described access frame is switched to respectively to physical chip according to described output control signal comprises:
When described management data clock occurs that trailing edge changes, generate the address switchover signal of synchronizeing with described output control signal;
When described management data clock does not occur that trailing edge changes, maintain described address switchover signal constant;
When described address switchover signal is described the first bit value, the frame head in the access frame that transfer management equipment sends in each passage;
When described address switchover signal switches to described the second bit value by described the first bit value, the reference address of the access frame transmitting in each passage is switched to respectively to the address of the physical chip corresponding with described passage;
When described address switchover signal switches to described the first bit value by described the second bit value, trigger the operation of the data segment in the access frame that transfer management equipment sends in each passage.
4. according to the method described in any one in claim 1-3, it is characterized in that, the described reference address of described parsing, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address to comprise:
Reference address in the access frame sending according to management equipment and the corresponding relation between reference address and the address of physical chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal;
According to passage corresponding to physical chip corresponding with reference address described in the lasting conducting of described address resolution gating signal, close the passage that other physical chips are corresponding, the data segment in described access frame is sent to the described physical chip corresponding with reference address.
5. an address resolver, is characterized in that, comprising:
Handover module, for the reference address of the access frame of management equipment transmission is switched respectively to the address of analysing as each physical chip, and issues each physical chip by the reference address after switching by passage corresponding to each physical chip accordingly;
Parsing module, be used for resolving described reference address, determine the physical chip corresponding with described reference address, data segment in the access frame that described management equipment is sent, by passage corresponding to the described physical chip corresponding with reference address, sends to the physical chip corresponding with described reference address;
Wherein, described handover module comprises:
The first frame recognin module, for generating output control signal according to the frame head of the access frame of management equipment transmission;
Switching submodule, for the reference address of described access frame being switched to respectively to the address of physical chip according to described output control signal, and issues each physical chip by the reference address after switching by passage corresponding to each physical chip accordingly.
6. address resolver according to claim 5, is characterized in that, described the first frame recognin module comprises:
The first recognition unit, the access frame that comes synchronous receiving management equipment to send for the rising edge with management data clock, when a continuous N bit of frame head all meets the front M position in default frame structure in recognizing described access frame, output control signal is switched to the second bit value by the first bit value;
The second recognition unit, during for N position reference address when recognizing after being transmitted described M bit of described access frame frame head, switches to described the first bit value by output control signal by described the second bit value;
Wherein, described M is the number of bits of default frame head, and described N is the number of bits of default reference address.
7. address resolver according to claim 6, is characterized in that, described switching submodule comprises:
Trigger element, when occurring that when described management data clock trailing edge changes, generates the address switchover signal of synchronizeing with described output control signal; When described management data clock does not occur that trailing edge changes, maintain described address switchover signal constant;
Gating unit, for when described address switchover signal is described the first bit value, the frame head in the access frame that transfer management equipment sends in each passage; When described address switchover signal switches to described the second bit value by described the first bit value, the reference address of the access frame transmitting in each passage is switched to respectively to the address of the physical chip corresponding with described passage; When described address switchover signal switches to described the first bit value by described the second bit value, data segment in the triggering access frame that transfer management equipment sends in each passage, and the operation that the reference address after switching is issued to each physical chip accordingly by passage corresponding to each physical chip.
8. according to the address resolver described in any one in claim 5-7, it is characterized in that, described parsing module comprises:
The second frame recognin module, be used for according to the reference address of the access frame of management equipment transmission and the corresponding relation between reference address and the address of physical chip, determine the physical chip corresponding with described reference address, and calculated address is resolved gating signal;
Passage is controlled submodule, be used for according to passage corresponding to physical chip corresponding with reference address described in the lasting conducting of described address resolution gating signal, close the passage that other physical chips are corresponding, so that the data segment in described access frame is sent to the described physical chip corresponding with reference address by corresponding passage.
9. an address resolution system, is characterized in that, comprises the address resolver described in any one in management equipment, physical chip and claim 5-8.
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| CN104348756B (en) * | 2013-08-08 | 2019-06-07 | 上海斐讯数据通信技术有限公司 | Switch system |
| CN105677599A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Host and method and system for managing slaves by host |
| CN106656391B (en) * | 2016-12-12 | 2018-10-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of exchanger chip multipath clock synchronization primitives clash handle circuit |
| CN109347474B (en) * | 2018-09-28 | 2022-09-23 | 深圳忆联信息系统有限公司 | Signal time sequence configuration method and device, computer equipment and storage medium |
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| US6385669B1 (en) * | 1999-05-11 | 2002-05-07 | 3Com Corporation | Method and apparatus for the detection of the presence of a device on a high speed digital data bus |
| CN101404645A (en) * | 2008-04-29 | 2009-04-08 | 华为技术有限公司 | Multiport Ethernet interface, its implementing method and physical layer interface |
| CN101692215A (en) * | 2009-08-28 | 2010-04-07 | 福建星网锐捷网络有限公司 | Method and device for controlling serial management interface |
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| US6385669B1 (en) * | 1999-05-11 | 2002-05-07 | 3Com Corporation | Method and apparatus for the detection of the presence of a device on a high speed digital data bus |
| CN101404645A (en) * | 2008-04-29 | 2009-04-08 | 华为技术有限公司 | Multiport Ethernet interface, its implementing method and physical layer interface |
| CN101692215A (en) * | 2009-08-28 | 2010-04-07 | 福建星网锐捷网络有限公司 | Method and device for controlling serial management interface |
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