CN102386166B - 包括与无源元件集成的器件晶片的晶片级封装 - Google Patents

包括与无源元件集成的器件晶片的晶片级封装 Download PDF

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CN102386166B
CN102386166B CN201110412463.5A CN201110412463A CN102386166B CN 102386166 B CN102386166 B CN 102386166B CN 201110412463 A CN201110412463 A CN 201110412463A CN 102386166 B CN102386166 B CN 102386166B
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wafer
layer
passive component
device wafer
polymeric layer
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CN102386166A (zh
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Q·甘
R·沃伦
A·洛比安科
S·梁
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Skyworks Solutions Inc
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Skyworks Solutions Inc
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Abstract

根据示例性的实施例，一种晶片级封装包括这样的器件晶片，所述器件晶片包括至少一个器件晶片接触衬垫和器件，并且其中所述至少一个器件晶片接触衬垫被电连接到所述器件。所述晶片级封装包括位于所述器件晶片之上的第一聚合物层。所述晶片级封装包括位于所述第一聚合物层之上并具有第一端子和第二端子的至少一个无源元件。所述至少一个无源元件的第一端子被电连接到所述至少一个器件晶片接触衬垫。所述晶片级封装包括位于所述至少一个无源元件之上的第二聚合物层。所述晶片级封装包括位于所述第二聚合物层之上并被电连接到所述至少一个无源元件的所述第二端子的至少一个聚合物层接触衬垫。

Description

包括与无源元件集成的器件晶片的晶片级封装
本申请是斯盖沃克斯瑟路申斯公司于2006年3月10日申请的申请号为200680008015.6、发明名称为“包括与无源元件集成的器件晶片的晶片级封装”的专利申请的分案申请
技术领域
本发明通常涉及半导体的领域，更具体而言，本发明在晶片级封装的领域中。
背景技术
电子器件例如移动电话和个人数字助理(PDA)的尺寸和价格持续减少而功能度持续增加。结果，这些电子器件需要更小、更低成本的元件，例如集成电路(IC)和微机电系统(MEMS)器件。但是，封装通常耗费IC和MEMS器件的约40.0％到约90.0％之间的总制造成本。结果，出现了晶片级封装作为提供同样具有减小的足印(footprint)的低成本IC和MEMS器件封装的挑战的主要解决方案。
在晶片级封装方法中，可以使用聚合物材料的层将帽晶片接合到包括IC或者MEMS器件的器件晶片以降低成本。然而，大多数基于聚合物的晶片级封装不提供在某些应用中需要的密闭密封。为了获得密闭密封，可以使用薄金属层例如金、基于金的合金、铜、基于铜的合金或者焊料形成接合层将帽晶片接合到器件晶片。然而，使用金属接合层不希望地增加了制造成本。
另外，在晶片级封装中通常需要用于匹配IC和MEMS器件例如射频(RF)IC和RF MEMS器件的无源元件例如电感器、电阻器和电容器。在一种常规封装方法中，将无源元件构建在多层印刷电路板(PCB)基底中并使用晶片级封装封装，这需要另一封装级的额外的成本以获得独立的器件。在另一常规封装方法中，将无源元件构建在PCB的表面，这不希望地消耗额外的封装空间。
因此，在本技术领域中需要一种包括在器件晶片上的器件的低成本、密闭地密封的晶片级封装，其中器件可以被耦合到器件晶片外的无源元件而不会不希望地增加封装足印。
发明内容
本发明旨在一种包括与无源元件集成的器件晶片的晶片级封装。本发明处理并解决了在本技术领域中对于包括在器件晶片上的器件的低成本、密闭地密封的晶片级封装的需要，其中所述器件可以被耦合到所述器件晶片外的无源元件而不会不希望地增加封装足印。
根据示例性的实施例，一种晶片级封装包括器件晶片，其中所述器件晶片包括至少一个器件晶片接触衬垫和至少一个器件，以及其中所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件。所述晶片级封装还包括位于所述器件晶片之上的第一聚合物层。所述第一聚合物层可以包括开口，例如其中所述开口形成用于所述至少一个器件的腔。所述晶片级封装还包括位于所述第一聚合物层之上的至少一个无源元件，其中所述至少一个无源元件具有第一端子和第二端子。所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫。所述晶片级封装还包括位于所述第一聚合物层中的第一导电过孔，其中所述第一导电过孔将所述至少一个无源元件的所述第一端子电连接到所述至少一个器件晶片接触衬垫。所述晶片级封装还包括位于所述至少一个无源元件之上的第二聚合物层。
根据该示例性的实施例，所述晶片级封装还包括位于所述第二聚合物层之上的至少一个聚合物层接触衬垫，其中所述至少一个聚合物接触衬垫被电连接到所述至少一个无源元件的所述第二端子。所述晶片级封装还包括位于所述第二聚合物层中的第二导电过孔，其中所述第二导电过孔被电连接到所述至少一个无源元件的所述第二端子。所述晶片级封装包括焊料凸起，其中所述焊料凸起位于所述至少一个聚合物接触衬垫上。例如，所述晶片级封装还包括位于所述第一聚合物层和所述第二聚合物层中的金属密封环。
所述器件晶片可以包括金属器件晶片环，其中所述金属器件晶片环围绕所述器件并且可以被连接到所述金属密封环。所述晶片级封装还包括位于所述第二聚合物层之上的钝化层，其中所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封。根据一个实施例，本发明为用于制造上述晶片级封装的方法。在阅读下面详细的说明和附图之后，本发明的其它特征和优点将对于本领域的普通技术人员变得更显而易见。
附图说明
图1示出了示例了实施本发明的实施例所采取的步骤的流程图；
图2A示例了对应图1中的流程图中的初始步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分；
图2B示例了对应图1中的流程图中的中间步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分；
图2C示例了对应图1中的流程图中的中间步骤的截面图，其包括根据本发明实施例处理的晶片的一部分；
图2D示例了对应图1中的流程图中的中间步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分；
图2E示例了对应图1中的流程图中的中间步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分；
图2F示例了对应图1中的流程图中的最终步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分；以及
图2G示例了对应图1中的流程图中的最终步骤的截面图，其包括根据本发明的实施例处理的晶片的一部分。
具体实施方式
本发明旨在一种包括与无源元件集成的器件晶片的晶片级封装。下列说明包含与实施本发明有关的具体信息。本领域的技术人员将认识到本发明可以以不同于在本申请中所具体讨论的方式来实施。而且，没有讨论本发明的一些具体细节以便不模糊本发明。在本发明中未被描述的具体细节在本领域的普通技术人员的知识范围内。
本申请中的附图和所附的详细的说明仅仅针对本发明的示例性的实施例。为了维持简明，使用本发明的原理的本发明的其它实施例在本申请中没有被详细描述，也没有通过本发明的附图具体说明。
本发明提供一种有效地集成无源元件和器件晶片的晶片级封装而不会不希望地增加封装足印。本发明的晶片级封装包括在器件晶片之上形成的聚合物层之间的无源元件，这将在以下详细讨论。虽然在此描述了具有仅仅两个聚合物层和两个无源元件的晶片级封装以示例本发明，但是可以应用本发明的创新的方法以提供具有位于器件晶片之上的多于两个聚合物层和无源元件的晶片级封装。
图1示出了示例了根据本发明的实施例的示例性方法的流程图。从流程图100省略了对于本领域技术人员显而易见的某些细节和特征。例如，如本领域所公知的，一个步骤可以由一个或多个步骤组成或者可以涉及特定的设备或材料。在流程图100中示出的步骤170至182足以描述本发明的一个实施例；本发明的其它实施例可以利用与在流程图100中所示的那些步骤不同的步骤。
此外，从图2A到2G中的结构270到282分别地示例了执行流程图100的步骤170到182的结果。例如，结构270示出了在处理步骤170之后的半导体结构，结构272示出了在处理步骤172之后的结构270，结构274示出了在处理步骤174之后的结构272，等等。
现在参考图1中的步骤170和图2A中的结构270，在流程图100的步骤170处，在处理晶片(handle wafer)204上形成牺牲涂层202，在牺牲涂层202上形成金属种子层206，在金属种子层206上形成聚合物层208。利用处理晶片204作为在其上制造本发明的晶片级封装的一部分的平台。处理晶片204可以包括硅或玻璃并且在随后的工艺步骤中被去除。牺牲涂层202位于处理晶片上并且包括可以通过施加热来分解的聚合物。在其它的实施例中，牺牲涂层202可以包括可以通过紫外(UV)光分解的聚合物或者可以在化学溶液中溶解的聚合物。在一个实施例中，牺牲涂层可以包括可以用光致抗蚀剂剥离物(stripper)去除的光致抗蚀剂。作为实例，牺牲涂层202可以具有约2.0微米与约50.0微米之间的厚度。可以通过使用旋涂方法或其它适宜的方法在处理晶片204上形成牺牲涂层202。在一个实施例中，牺牲涂层202包括可以层压在处理晶片上的干膜带。
金属种子层206位于牺牲涂层202上并且可以包括钛、钛钨、铜、金、铬、氮化钛或其它适宜的金属或者金属合金。作为实例，金属种子层206可以具有约0.1微米与约2.0微米之间的厚度。可以通过使用溅射方法、化学气相淀积(CVD)方法、物理气相淀积(PVD)方法或其它适宜的方法在牺牲涂层202上形成金属种子层206。聚合物层208位于金属种子层206上并且可以包括光成像的(photoimageable)聚合物，例如苯并环丁烯(BCB)，SU-8(环氧基的负抗蚀剂)或者聚酰亚胺族的化学结构中的一种。在一个实施例中，聚合物层208可以包括光成像的环氧树脂。作为实例，聚合物层208可以具有在约30.0微米与约70.0微米之间的厚度。可以通过使用旋涂方法、喷涂方法、丝网印刷方法或者其它适宜的方法在金属种子层206上形成聚合物层208。通过在图2A中的结构270示例了流程图100的步骤170的结果。
参考图1中的步骤172和图2B中的结构272，在流程图100的步骤172处，在聚合物层208中形成导电过孔210和212以及金属带214并且在聚合物层208上形成无源元件216和218。导电过孔210和212位于聚合物层208中并且延伸通过聚合物层208，并且可以包括导电材料例如铜、金、镍、焊料材料例如基于锡的焊料材料，或者其它适宜的金属或金属合金。可以通过在聚合物层208上构图过孔开口并且通过利用反应离子蚀刻(RIE)方法、湿法蚀刻方法或其它适宜的蚀刻方法延伸该过孔开口通过聚合物层208，形成导电过孔210和212。然后可以使用无电镀敷方法、电镀敷方法、丝网印刷方法或其它适宜的淀积方法使用导电材料填充过孔开口，以形成导电过孔210与212。
金属带214位于并且延伸通过聚合物层208并形成沿聚合物层208周边延伸的连续的金属环路(loop)。金属带214可以包括铜、金、镍、焊料材料例如基于锡的焊料材料或者其它适宜的金属或金属合金。可以通过在聚合物层208中构图并且蚀刻沟槽形成金属带214。然后可以使用无电镀敷方法、电镀敷方法或其它适宜的淀积方法使用适宜的金属或金属合金填充该沟槽，以形成金属带214。
无源元件216位于聚合物208上并且具有位于过孔210之上并与其电接触的端子220和端子222。无源元件216可以是电阻器、电感器、或电容器，并且可以包括金属例如钨或其它适宜的金属材料。无源元件218位于聚合物208上并且具有位于过孔212之上并与其电接触的端子224和端子226。无源元件218可以是电阻器、电感器、或电容器，并且可以包括金属例如钨或其它适宜的金属材料。可以通过在聚合物层208之上淀积包括钨或其它适宜的金属材料的再分布(redistribution)层和适宜地构图和蚀刻再分布层来形成无源元件216与218。通过在图2B中的结构272示例了流程图100的步骤172的结果。
参考图1中的步骤174和图2C中的结构274，在流程图100的步骤174处，在聚合物层208与无源元件216和218之上形成聚合物层228，并且在聚合物层228中形成导电过孔230和232、开口234以及金属带236。聚合物层228位于聚合物层208层与无源元件216和218之上并且可以包括光成像的聚合物例如BCB、SU-8、或聚酰亚胺族的化学结构中的一种。在一个实施例中，聚合物层208可以包括光成像的环氧树脂。在一个实施例中，聚合物层228和聚合物层208可以包括不同的材料。作为实例，聚合物层228可以具有在约5.0微米与约70.0微米之间的厚度。可以通过使用旋涂方法、喷涂方法、丝网印刷方法或者其它适宜的方法在聚合物层208和无源元件216和218之上形成聚合物层228。
导电过孔230和232位于聚合物层228中并且位于各自的无源元件216和218之上。导电过孔230位于无源元件216的端子222之上并与其电接触，并且导电过孔232位于无源元件218的端子226之上并与其电接触。导电过孔230和232在组成和形成方面基本上与导电过孔210和214相似。开口234位于聚合物层228中在导电过孔230与232之间并且可以通过适宜地构图和蚀刻聚合物层228形成。金属带236位于聚合物层228中并延伸通过聚合物层228并且还位于金属带214上。金属带236形成沿聚合物层228的周边延伸的连续的金属环路，并且在组成、厚度和形成方面基本上与聚合物层208中的金属带214相似。金属带236和金属带214形成金属密封环238，其形成位于聚合物层208和聚合物层228中延伸并且围绕导电过孔210、212、230和232以及无源元件216和218的连续的金属环路。通过在图2C中的结构274示例了流程图100的步骤174的结果。
参考图1中的步骤176和图2D中的结构276，在流程图100的步骤176处，在各自的导电过孔230和232上形成焊料衬垫240和242，在金属密封环238上形成焊料环244，并且将器件晶片246接合到聚合物层228。焊料衬垫240和242位于聚合物层28中各自的导电过孔230与232上，并且可以包括焊料材料例如锡-银-铜、锡-银、铟或者具有低温熔点的其它适宜的焊料材料。可以通过使用镀敷方法或其它适宜的淀积方法在各自的导电过孔230和232上形成焊料衬垫240和242。焊料环244位于金属密封环238上，并且在组成、厚度和形成方面基本上与焊料衬垫240和242相似。
可以包括硅和/或硅-锗、GaAs、InP、InGaP、和或其它材料的器件晶片246位于聚合物层228之上，并且包括器件248、器件晶片接触衬垫250和252和金属器件晶片环254。可以包括IC例如RF IC的器件248位于器件晶片246上，并且位于开口234之上，其形成用于器件248的腔。在一个实施例中，器件248可以包括MEMS器件，例如RF MEMS器件。器件晶片接触衬垫250和252位于器件晶片246上并被电连接到器件248，并且还分别被电连接到无源元件216和218的端子222和226。金属器件晶片环254位于器件晶片246上，并且形成沿器件晶片246的周边延伸并围绕器件晶片接触衬垫250和252以及器件248的连续的金属环路。金属器件晶片环254可以被连接到器件晶片246中的地。在一个实施例中，金属器件晶片环254可以不被连接到器件晶片246中的地。
器件晶片接触衬垫250和252以及金属器件晶片环254可以包括铜、铝、或者其它适宜的金属或金属合金，并且可以以本技术领域中公知的方法被形成在器件晶片246上。注意到虽然为了保持简明在此具体地讨论的器件晶片包括仅仅一个器件和两个器件接触衬垫，但是器件晶片可以包括大量的器件接触衬垫和多个器件。可以通过使用焊料衬垫240和242分别将焊料导电过孔230和232接合到器件晶片接触衬垫250和252并且通过使用焊料环244将焊料金属密封环238接合到器件晶片金属环254，将器件晶片246接合到聚合物层228。通过在图2D中的结构276示例了流程图100的步骤176的结果。
参考图1中的步骤178和图2E中的结构278，在流程图100的步骤178处，进行减薄工艺以获得器件晶片246的目标厚度256，并且从金属种子层206去除处理晶片204。作为实例，器件晶片246的目标厚度可以在约50.0微米与约300.0微米之间。在减薄工艺中，可以通过从器件晶片246去除足够量的材料获得器件晶片246的目标厚度256。减薄方法可以包括研磨方法、研磨方法、化学机械抛光(CMP)方法、蚀刻方法或者其它适宜的材料去除方法。可以通过以适宜的方法分解(在图2A和2D中示出的)牺牲涂层202从金属种子层206去除(在图2A到2D中示出的)处理晶片204，以便从金属种子层206释放处理晶片204。在本实施例中，可以用加热方法分解牺牲涂层202，以从金属种子层206释放处理晶片204。在其它实施中，可以通过使用UV光或化学溶液分解牺牲涂层202。在去除处理晶片204之后，可以通过使用湿法或干法蚀刻方法去除在金属种子层206上剩余的牺牲涂层202的任何部分。通过图2E中的结构278示例了流程图100的步骤178的结果。
参考图1中的步骤180和图2F中的结构280，在流程图100的步骤180处，从聚合物层208去除金属种子层206，在聚合物208的暴露的表面260上形成钝化层258，以及在钝化层258中形成开口262和264以暴露各自的导电过孔210和212。可以通过使用湿法或干法蚀刻工艺去除(在图2A到2E中示出的)金属种子层206以暴露聚合物208的表面260。钝化层258位于聚合物208的表面260上，并且可以包括二氧化硅、氮化硅或者其它适宜的介质材料。可以通过使用CVD方法、等离子增强化学气相淀积(PECVD)方法或者其它适宜的低温淀积方法在聚合物层208上形成钝化层258。钝化层258可以具有小于约1.0微米的厚度。在一个实施例中，钝化层258可以具有在几十纳米与几百纳米之间的厚度。开口262和264位于各自的导电过孔210和212之上并暴露了导电过孔210和212，并且可以通过适宜地构图和蚀刻钝化层258形成。钝化层258和金属密封环238提供了用于本发明的晶片级封装的密闭密封。在不需要密闭密封的晶片级封装的本发明的实施例中，可以不使用钝化层258和/或金属密封环238。通过在图2F中的结构280示例了流程图100的步骤180的结果。
参考图1中的步骤182和图2G中的结构282，在流程图100的步骤182处，在各自的导电过孔210和212之上形成聚合物层接触衬垫265和266，并且在各自的聚合物层接触衬垫265和266上形成焊料凸起267和268。聚合物层接触衬垫265和266位于各自的导电过孔210和212上，并且可以包括凸起下金属化(UBM)层的一部分，其可以包括镍、铜、钒或者其它适宜的金属或金属合金。可以通过使用PVD方法或者其它适宜的淀积方法在导电过孔210和212以及钝化层258之上淀积UBM层并且适宜地构图和蚀刻UBM层，形成聚合物层接触衬垫265和266。通过导电过孔210将聚合物层接触衬垫265电连接到无源元件216的端子220，通过导电过孔212将聚合物层接触衬垫266电连接到无源元件218的端子224。
焊料凸起267和268位于各自的聚合物层接触衬垫265和266上，并且包括适宜的焊料材料。焊料凸起267和268可以提供在聚合物层接触衬垫265和266与容纳器件248和无源元件216和218的本发明的晶片级封装外部的器件和元件之间的电连接性。在一个实施例中，可以使用线接合代替焊料凸起267和268以提供在聚合物层接触衬垫265和266与本发明的晶片级封装外的器件和元件之间的电连接性。通过在图2G中的结构282示例了流程图100的步骤182的结果。
因此，如上所述，本发明有利地实现了一种包括位于在器件晶片之上的聚合物层之间的无源元件的晶片级封装，其中可以将无源元件连接到器件晶片接触衬垫并且通过聚合物层接触衬垫还可将其连接到外部的元件和器件。通过在器件晶片之上形成的聚合物层之间形成无源元件，本发明在晶片级封装中有效地将无源元件与器件晶片集成而不会不希望地增加封装足印。
另外，通过在聚合物层中形成金属密封环和在聚合物层之上形成钝化层，本发明有利的获得了密闭密封的晶片级封装，其具有与通过使用金属接合材料将帽晶片接合到器件晶片获得密闭密封的常规密闭密封的晶片级封装相比的减少的成本。从本发明的上述说明可知，可以使用各种技术用于实现本发明的构思而不偏离其范围。此外，虽然参照特定实施例描述了本发明，但本领域的技术人员将理解，可以在形式和细节方面做出各种改变而不背离本发明的精神和范围。因此，所述实施例在所有方面被考虑为示例性的而非限制性的。同样应该理解，本发明不局限于这里的具体实施例，而能够具有许多重新组合、修改和替代而不背离本发明的范围。
因此，已描述了一种包括与无源元件集成的器件晶片的晶片级封装。

Claims (16)

1.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层包括开口，所述开口形成用于所述至少一个器件的腔，以及所述至少一个器件晶片接触衬垫被焊接到在所述第一聚合物层中的至少一个导电过孔；
第二聚合物层，其位于所述至少一个无源元件之上；
金属密封环，其位于所述第一聚合物层和所述第二聚合物层中；以及
钝化层，其位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封。
2.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子；
第二聚合物层，位于所述至少一个无源元件之上，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层包括开口，所述开口形成用于所述至少一个器件的腔，以及所述腔不包括来自所述第一聚合物层或来自所述第二聚合物层的聚合物材料；
金属密封环，其位于所述第一聚合物层和所述第二聚合物层中；以及
钝化层，其位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封。
3.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子；
第二聚合物层，位于所述至少一个无源元件之上，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层包括开口，所述开口形成用于所述至少一个器件的腔，以及所述第一聚合物层具有与所述第二聚合物层不同的材料；
金属密封环，其位于所述第一聚合物层和所述第二聚合物层中；以及
钝化层，其位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封。
4.根据权利要求3的晶片级封装，其中所述至少一个无源元件位于所述第一聚合物层与所述第二聚合物层之间的界面处。
5.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子；
第二聚合物层，位于所述至少一个无源元件之上，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层具有开口，所述开口形成用于所述至少一个器件的腔，以及所述腔由所述器件晶片与所述第一聚合物层之间的空间以及所述器件晶片与所述第二聚合物层之间的空间限定，以及没有中间层存在于所述器件晶片与所述第一聚合物层之间的所述空间或所述器件晶片与所述第二聚合物层之间的所述空间中；
金属密封环，其位于所述第一聚合物层和所述第二聚合物层中；以及
钝化层，其位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封。
6.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子；
第二聚合物层，位于所述至少一个无源元件之上；
金属密封环，位于所述第一聚合物层和所述第二聚合物层中；
钝化层，位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封；以及
金属器件晶片环，形成连续的金属环，该连续的金属环围绕所述至少一个器件并被连接到所述金属密封环，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层具有开口，所述开口形成用于所述至少一个器件的腔，以及所述金属器件晶片环被连接到所述器件晶片中的地。
7.一种晶片级封装，包括：
器件晶片，包括至少一个器件晶片接触衬垫和至少一个器件，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
第一聚合物层，其位于所述器件晶片之上；
至少一个无源元件，其位于所述第一聚合物层之上，所述至少一个无源元件具有第一端子和第二端子；
第二聚合物层，位于所述至少一个无源元件之上；
金属密封环，位于所述第一聚合物层和所述第二聚合物层中；
钝化层，其位于所述第二聚合物层之上，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封；以及
金属器件晶片环，形成连续的金属环，该连续的金属环围绕所述至少一个器件并被连接到所述金属密封环，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫，所述第一聚合物层包括开口，所述开口形成用于所述至少一个器件的腔，以及所述金属器件晶片环被焊接到所述金属密封环。
8.一种用于制造晶片级封装的方法，包括：
在处理晶片之上形成第一聚合物层；
在所述第一聚合物层的第一表面上形成至少一个无源元件，所述至少一个无源元件具有第一端子和第二端子；
在所述至少一个无源元件之上形成第二聚合物层；
将器件晶片接合到所述第二聚合物层，所述器件晶片包括至少一个器件和至少一个器件晶片接触衬垫，所述至少一个器件晶片接触衬垫被电连接到所述至少一个器件；
在所述第一聚合物层的相对于所述第一表面的第二表面之上形成至少一个聚合物层接触衬垫；所述至少一个无源元件的所述第一端子被电连接到所述至少一个聚合物层接触衬垫以及所述至少一个无源元件的所述第二端子被电连接到所述至少一个器件晶片接触衬垫；
在所述第一聚合物层和所述第二聚合物层中形成金属密封环；
在所述第一聚合物层的所述第二表面之上形成钝化层，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封；以及
在所述第二聚合物层中形成开口，所述接合包括在所述开口之上定位所述至少一个器件，所述开口形成用于所述至少一个器件的腔。
9.一种用于制造晶片级封装的方法，包括：
在处理晶片之上形成第一聚合物层；
在所述第一聚合物层的第一表面上形成至少一个无源元件，所述至少一个无源元件具有第一端子和第二端子；
在所述至少一个无源元件之上形成第二聚合物层；
在所述第一聚合物层和所述第二聚合物层中形成金属密封环；
在所述第一聚合物层的相对于所述第一表面的第二表面之上形成钝化层，所述钝化层和所述金属密封环提供用于所述晶片级封装的密闭密封；
将器件晶片接合到所述第二聚合物层，所述器件晶片包括被电连接到至少一个器件晶片接触衬垫的至少一个器件，所述至少一个无源元件的所述第一端子被电连接到所述至少一个器件晶片接触衬垫；以及
在形成所述第一聚合物层之后在所述第一聚合物层中形成第一导电过孔和第一金属带，所述第一导电过孔被连接到所述至少一个无源元件的所述第二端子。
10.根据权利要求9的方法，还包括在所述第一聚合物层的所述第二表面之上形成至少一个聚合物层接触衬垫，所述至少一个聚合物层接触衬垫被电连接到所述至少一个无源元件的所述第二端子。
11.根据权利要求10的方法，还包括在所述第二聚合物层中形成第二导电过孔和第二金属带，所述第二导电过孔被连接到所述至少一个无源元件的所述第一端子，以及所述第一金属带和所述第二金属带形成所述金属密封环。
12.根据权利要求9的方法，还包括在形成所述第一聚合物层之前在所述处理晶片之上形成牺牲涂层。
13.根据权利要求9的方法，其中所述第一聚合物层包括光成像聚合物。
14.根据权利要求10的方法，还包括在所述至少一个聚合物接触衬垫上形成焊料凸起。
15.根据权利要求10的方法，还包括在形成所述至少一个聚合物层接触衬垫之前进行减薄工艺以获得所述器件晶片的目标厚度。
16.根据权利要求9的方法，还包括在所述第二聚合物层中形成开口，所述接合包括在所述开口之上定位所述至少一个器件，所述开口形成用于所述至少一个器件的腔。
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