CN102403455A - Method for manufacturing phase-change memory component - Google Patents
Method for manufacturing phase-change memory component Download PDFInfo
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- CN102403455A CN102403455A CN2010102880953A CN201010288095A CN102403455A CN 102403455 A CN102403455 A CN 102403455A CN 2010102880953 A CN2010102880953 A CN 2010102880953A CN 201010288095 A CN201010288095 A CN 201010288095A CN 102403455 A CN102403455 A CN 102403455A
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- organic antireflection
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Abstract
The invention provides a method for manufacturing a phase-change memory component, which comprises the following steps of: providing a front-end device structure, wherein the front-end device structure comprises a bottom electrode, and the bottom electrode exposes on the surface of the front-end device structure; forming an organic antireflection layer and a photoresist pattern on the front-end device structure, wherein the photoresist pattern is positioned above the bottom electrode; etching the photoresist pattern and the organic antireflection layer to shorten the line widths of the photoresist pattern and the organic antireflection layer; forming an insulating layer in an area uncovered by the remaining photoresist pattern and the remaining organic antireflection layer on the surface of the front-end device structure; removing the remaining photoresist pattern and the remaining organic antireflection layer to form an opening; forming a second dielectric layer and a phase-change layer on the insulating layer, positioning the phase-change layer above the bottom electrode and filling the opening; and forming a third dielectric layer and a top electrode on the second dielectric layer and the phase-change layer, and positioning the top electrode at the position aligned with the bottom electrode on the phase-change layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making phase change memory component.
Background technology
The local pyrexia that phase-change material (for example Ge-Sb-Te phase-change material) causes through electric pulse and change its phase into crystalline state and amorphous state, phase transition storage is exactly the semiconductor device that utilizes this characteristic storage binary message.Phase transition storage is based on the memory of resistance, reaches the purpose of storage binary message through conversion and the corresponding resistance characteristic that presents low-resistance and high resistant of phase-change material between crystalline state and amorphous state.In phase transition storage, the memory cell of storage binary message comprises phase change layer and electrode.
Fig. 1 is the sectional view of the phase change memory component of prior art.As shown in Figure 1, phase change memory component 100 comprises bottom electrode 101, phase change layer 102 and top electrodes 103.The electric current of the varying strength phase change layer 102 of flowing through flows through the thermal effect that phase change layer 102 produced through electric current and changes phase-change material into amorphous state (RESET attitude) by crystalline state (SET attitude), and (RESET) operation promptly can reset to phase-change material.The operation of crystalline state is corresponding to be called set (SET) and phase-change material changed into by amorphous state.When carrying out the SET operation; Need apply a voltage or a current impulse long and intensity is medium; The temperature of phase-change material is elevated to more than the crystallization temperature, below the fusion temperature; And keep the regular hour (generally greater than 50ns), make phase-change material be converted into crystalline state by amorphous state, become low-resistance by high resistant.When carrying out the RESET operation; Need apply a weak point and strong current impulse; Electric energy is transformed into heat energy, the temperature of phase-change material is elevated to more than the fusion temperature, through quick cooling just can realize phase-change material by crystalline state to amorphous conversion; Promptly become high resistant, thereby realize memory function based on resistance by low-resistance.
In phase change memory component, phase change layer needs higher temperature from crystalline state to amorphous transition process.Generally speaking, through bottom electrode phase change layer is heated, top electrodes only plays the effect of interconnection, and therefore, bottom electrode directly has influence on the read-write speed of phase change memory component to the quality of the heats of phase change layer.In order to obtain good heats; The bigger drive current of the general employing of phase change memory component; Its write-operation current will reach about 1mA, but drive current can not unrestrictedly rise, and big drive current can cause the small-sized difficulty of peripheral drive circuit and logical device.Also have a kind of method that improves heats to be, dwindle the contact area of bottom electrode and phase change layer, improve contact resistance.Yet in the existing technology, the forming process of bottom electrode mainly is in interlayer dielectric layer, to form the hole earlier, fills metal then.Usually the top width in etching formation hole causes formed bottom electrode to be horn-like all greater than bottom width, therefore is difficult to further dwindle the contact area between bottom electrode and the phase change layer.In addition, because the restriction of the photo-etching machine exposal limit only can't define the bottom electrode that satisfies technological requirement by photoetching.
Therefore, need a kind of method,, improve the efficiency of heating surface of bottom electrode, thereby improve the read or write speed of phase change memory component phase change layer through reducing the contact area between bottom electrode and the phase change layer.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
The invention provides a kind of method of making phase change memory component, comprising: the front end device architecture a) is provided, and said front end device architecture comprises bottom electrode, and said bottom electrode is exposed to the surface of said front end device architecture; B) on said front end device architecture, form organic antireflection layer, photoresist pattern successively, wherein, said photoresist pattern be positioned at said bottom electrode directly over; C) said photoresist pattern and said organic antireflection layer are carried out etching, to dwindle the live width of said photoresist pattern and said organic antireflection layer; D) on the surface of said front end device architecture, do not formed insulating barrier by remaining said photoresist pattern and said organic antireflection layer region covered; E) remove remaining said photoresist pattern and said organic antireflection layer, to form opening; F) on said insulating barrier, form second dielectric layer and phase change layer, wherein, said second dielectric layer surround said phase change layer around, said phase change layer be positioned at said bottom electrode directly over, and fill said opening; And g) on said second dielectric layer and said phase change layer, form the 3rd dielectric layer and top electrodes, wherein, said the 3rd dielectric layer surround said top electrodes around, said top electrodes is positioned at the position of aiming at said bottom electrode on the said phase change layer.
Preferably, c) in the step, said etching comprises anisotropic etching and isotropic etching.
Preferably, feed Cl in the said anisotropic etching process
2, HBr, CF
4, O
2In at least two kinds of gases, perhaps N
2And H
2Mist, and substrate bias power is 100-500W.
Preferably, feed O in the said isotropic etching process
2Or Cl
2, and substrate bias power is 0-50W.
Preferably, also feed HBr and CH in the said isotropic etching process
2F
2
Preferably, the live width of remaining said photoresist pattern and said organic antireflection layer is 5-40nm.
Preferably, said insulating barrier forms through the selective deposition method.
Preferably, said selective deposition method is a chemical liquid deposition.
Preferably, the material of said insulating barrier is a silica.
Preferably, the thickness of said organic antireflection layer is 30-100nm.
Preferably, the thickness of said insulating barrier is less than or equal to the thickness of said organic antireflection layer.
Preferably, at e) step and f) between the step, also comprise the step that the front end device architecture that is formed with said insulating barrier is cleaned.
Preferably, remaining said photoresist pattern and said organic antireflection layer adopt the mode of ashing to remove.
Method according to invention can effectively reduce the contact area between bottom electrode and the phase change layer, improves the efficiency of heating surface of bottom electrode to phase change layer, thereby improves the read or write speed of phase change memory component.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the sectional view of the phase change memory component of prior art;
Fig. 2 A-2F is the sectional view according to each step in the method flow of one embodiment of the invention making phase change memory component;
Fig. 3 is a process chart of making phase change memory component according to one embodiment of the invention.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes phase change memory component.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Fig. 2 A-2F is the sectional view according to each step in the method flow of one embodiment of the invention making phase change memory component.
Shown in Fig. 2 A, front end device architecture 200 is provided.At first, provide to be formed with the isostructural substrate 201 of grid, source electrode, drain electrode and interlayer dielectric layer, for for simplicity, said structure is all not shown in the drawings.Wherein, the material of interlayer dielectric layer can be chosen as low k (dielectric constant) material.Has the conduction latch of making by electric conducting material that at least one exposes upper surface in the interlayer dielectric layer, for example the tungsten latch.Then, on the surface of substrate 201, form first dielectric layer 202 and bottom electrode 202a, wherein bottom electrode 202a is exposed to the surface of front end device architecture 200, and be positioned at the conduction latch directly over.The material of first dielectric layer 202 can be an oxide, silica for example, and generation type can be a chemical vapour deposition technique (CVD) etc.The material of bottom electrode 202a can be DOPOS doped polycrystalline silicon, W, TiN or TiAlN; It can also be other silicide material; This silicide material can be at least a silicide that comprises among Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, Zn and the Mg, is preferably WSi.The method that forms bottom electrode 202a can be filled into bottom electrode material in the said opening in first dielectric layer 202, defining earlier the opening of bottom electrode pattern then.Substrate 201, bottom electrode 202a and first dielectric layer, 202 common formation front end device architectures 200.
Shown in Fig. 2 B, on front end device architecture 200, forming thickness is the organic antireflection layer 203 of 30-100nm.On organic antireflection layer 203, form photoresist layer, form photoresist pattern 204 through technologies such as exposure, developments then.Wherein, photoresist pattern 204 be positioned at bottom electrode 202a directly over.The live width (D) of the photoresist pattern 204 of technology definition such as warp exposure, development is generally 50-100nm.
Shown in Fig. 2 C, photoresist pattern 204 and organic antireflection layer 203 are carried out etching, to dwindle the live width of photoresist pattern 204 and organic antireflection layer 203.Said etching comprises anisotropic etching and isotropic etching, and particularly, said etching comprises the anisotropic etching of organic antireflection layer 203 and isotropic etching, and to the isotropic etching of photoresist pattern 204.To specifically describe the step of said etching below.
According to one embodiment of the present invention, said etching process comprises: with photoresist pattern 204 is mask, and organic antireflection layer 203 is carried out anisotropic etching, so that photoresist pattern 204 is transferred to organic antireflection layer 203; Photoresist pattern 204 and organic antireflection layer 203 are carried out isotropic etching, with the live width of dwindling photoresist pattern 204 and organic antireflection layer 203 to d.
Another execution mode according to the present invention, said etching process comprises: photoresist pattern 204 is carried out isotropic etching, with the live width of dwindling photoresist pattern 204 to d; The photoresist pattern 204 that with the live width is d is a mask, and organic antireflection layer 203 is carried out anisotropic etching, being that the photoresist pattern 204 of d is transferred to organic antireflection layer 203 with live width.
Above-mentioned etching all can adopt dry etching.
For the anisotropic etching of organic antireflection layer 203, can feed Cl
2, HBr, CF
4, O
2In at least two kinds of gases, perhaps N
2And H
2Mist, substrate bias power is 100-500W.According to one embodiment of the present invention, the gas of anisotropic etching comprises HBr and CF
4, the flow velocity of HBr is 50-100sccm, the flow velocity of CF4 is 20-80sccm.Wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow.
Isotropic etching for photoresist pattern 204 and/or organic antireflection layer 203 can adopt O
2Or Cl
2In addition, the gas of isotropic etching can also comprise HBr and CH
2F
2Substrate bias power is 0-50W, is preferably 0W.According to one embodiment of the present invention, the gas of isotropic etching comprises O
2, CH
2F
2And HBr.Wherein, O
2Flow velocity be 10-100sccm, the flow velocity of HBr is 0-80sccm, CH
2F
2Flow velocity be 10-20sccm.
In addition, can also comprise inert gas in the gas of isotropic etching and anisotropic etching, to play effects such as holding chamber internal pressure and dilution.Through after the above-mentioned PROCESS FOR TREATMENT, the live width (d) of remaining photoresist pattern 204 and organic antireflection layer 203 is 5-40nm.
Shown in Fig. 2 D, on the surface of front end device architecture 200, do not formed insulating barrier 205 by remaining photoresist pattern 204 and organic antireflection layer 203 region covered.The method that forms insulating barrier 205 is the selective deposition method; Promptly for front end device architecture 200; Only do not formed insulating barrier 205, and on remaining photoresist pattern 204, do not forming insulating barrier by remaining photoresist pattern 204 and organic antireflection layer 203 region covered.Said selective deposition rule is chemical liquid deposition etc. in this way.The material of insulating barrier 205 can be a silica.The thickness of insulating barrier 205 need be less than or equal to the thickness of organic antireflection layer 203.
Shown in Fig. 2 E, remove remaining photoresist pattern 204 and organic antireflection layer 203, to form opening 210.Remaining photoresist pattern 204 can adopt mode such as ashing to remove with organic antireflection layer 203.Then, alternatively, the front end device architecture 200 that is formed with insulating barrier 205 is cleaned, to remove in the opening 210 and insulating barrier 205 lip-deep residues.
Shown in Fig. 2 F, on the surface of insulating barrier 205, form second dielectric layer 206 and phase change layer 206a.Around second dielectric layer, the 206 encirclement phase change layer 206a.Phase change layer 206a be positioned at bottom electrode 202a directly over, and phase change layer 206a filling opening 210.Then, on second dielectric layer 206 and phase change layer 206a, form the 3rd dielectric layer 207 and top electrodes 207a.Around the 3rd dielectric layer 207 encirclement top electrodes 207a.Top electrodes 207a is positioned at phase change layer 206a and goes up the position of aiming at bottom electrode 202a, thereby accomplishes the making of phase change memory component.
The phase change memory component of making according to the embodiment of the present invention through between phase change layer and bottom electrode, forming the insulating barrier with opening, has dwindled the contact area of phase change layer and bottom electrode, thereby has improved both contact resistances.When phase change layer being heated through bottom electrode, obtain good heats, therefore, improved the read or write speed of phase transition storage, and both contacts area can adjust through technology, simple and convenient, be easy to manufacture.
As shown in Figure 3, be process chart according to the making phase change memory component of the embodiment of the invention.In step 301, the front end device architecture is provided, said front end device architecture comprises first dielectric layer and bottom electrode, bottom electrode is exposed to the surface of front end device architecture.In step 302, on the front end device architecture, form organic antireflection layer and photoresist pattern successively, wherein, the photoresist pattern be positioned at bottom electrode directly over.In step 303, photoresist pattern and organic antireflection layer are carried out etching, to dwindle the live width of photoresist pattern and organic antireflection layer.Said etching comprises the anisotropic etching of organic antireflection layer and isotropic etching.In step 304, on front end device architecture surface, do not formed insulating barrier by remaining photoresist pattern and organic antireflection layer region covered.In step 305, remove remaining photoresist pattern and organic antireflection layer, to form opening.In step 306, on insulating barrier, form second dielectric layer and phase change layer.Second dielectric layer surround phase change layer around, phase change layer be positioned at bottom electrode directly over, and phase change layer filling opening.On second dielectric layer and phase change layer, form the 3rd dielectric layer and top electrodes.Around the 3rd dielectric layer encirclement top electrodes, top electrodes is positioned at the position of aiming at bottom electrode on the phase change layer.Accomplish the making of phase change memory component.
Phase change memory component according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type dynamic random access memory), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (13)
1. method of making phase change memory component comprises:
A) the front end device architecture is provided, said front end device architecture comprises bottom electrode, and said bottom electrode is exposed to the surface of said front end device architecture;
B) on said front end device architecture, form organic antireflection layer, photoresist pattern successively, wherein, said photoresist pattern be positioned at said bottom electrode directly over;
C) said photoresist pattern and said organic antireflection layer are carried out etching, to dwindle the live width of said photoresist pattern and said organic antireflection layer;
D) on the surface of said front end device architecture, do not formed insulating barrier by remaining said photoresist pattern and said organic antireflection layer region covered;
E) remove remaining said photoresist pattern and said organic antireflection layer, to form opening;
F) on said insulating barrier, form second dielectric layer and phase change layer, wherein, said second dielectric layer surround said phase change layer around, said phase change layer be positioned at said bottom electrode directly over, and fill said opening; And
G) on said second dielectric layer and said phase change layer, form the 3rd dielectric layer and top electrodes, wherein, said the 3rd dielectric layer surround said top electrodes around, said top electrodes is positioned at the position of aiming at said bottom electrode on the said phase change layer.
2. the method for claim 1 is characterized in that, c) in the step, said etching comprises anisotropic etching and isotropic etching.
3. method as claimed in claim 2 is characterized in that, feeds Cl in the said anisotropic etching process
2, HBr, CF
4, O
2In at least two kinds of gases, perhaps N
2And H
2Mist, and substrate bias power is 100-500W.
4. method as claimed in claim 2 is characterized in that, feeds O in the said isotropic etching process
2Or Cl
2, and substrate bias power is 0-50W.
5. method as claimed in claim 4 is characterized in that, also feeds HBr and CH in the said isotropic etching process
2F
2
6. the method for claim 1 is characterized in that, the live width of remaining said photoresist pattern and said organic antireflection layer is 5-40nm.
7. the method for claim 1 is characterized in that, said insulating barrier forms through the selective deposition method.
8. method as claimed in claim 7 is characterized in that, said selective deposition method is a chemical liquid deposition.
9. the method for claim 1 is characterized in that, the material of said insulating barrier is a silica.
10. the method for claim 1 is characterized in that, the thickness of said organic antireflection layer is 30-100nm.
11. the method for claim 1 is characterized in that, the thickness of said insulating barrier is less than or equal to the thickness of said organic antireflection layer.
12. the method for claim 1 is characterized in that, at e) step and f) between the step, also comprise the step that the front end device architecture that is formed with said insulating barrier is cleaned.
13. the method for claim 1 is characterized in that, remaining said photoresist pattern and said organic antireflection layer adopt the mode of ashing to remove.
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|---|---|---|---|---|
| CN1728340A (en) * | 2004-07-29 | 2006-02-01 | 应用材料有限公司 | Cluster tool and method for process integration in manufacture of a gate structure of a field effect transistor |
| US20080131994A1 (en) * | 2006-12-01 | 2008-06-05 | Heon Yong Chang | Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer |
| US20090261313A1 (en) * | 2008-04-22 | 2009-10-22 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
| CN101572290A (en) * | 2009-06-02 | 2009-11-04 | 中国科学院上海微系统与信息技术研究所 | Method for preparing columnar nanometer heating electrode |
-
2010
- 2010-09-17 CN CN2010102880953A patent/CN102403455A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728340A (en) * | 2004-07-29 | 2006-02-01 | 应用材料有限公司 | Cluster tool and method for process integration in manufacture of a gate structure of a field effect transistor |
| US20080131994A1 (en) * | 2006-12-01 | 2008-06-05 | Heon Yong Chang | Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer |
| US20090261313A1 (en) * | 2008-04-22 | 2009-10-22 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
| CN101572290A (en) * | 2009-06-02 | 2009-11-04 | 中国科学院上海微系统与信息技术研究所 | Method for preparing columnar nanometer heating electrode |
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