CN102420108A - Process for manufacturing metal-insulator-metal capacitor by adopting copper damascene process, and structure - Google Patents
Process for manufacturing metal-insulator-metal capacitor by adopting copper damascene process, and structure Download PDFInfo
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- CN102420108A CN102420108A CN2011101603093A CN201110160309A CN102420108A CN 102420108 A CN102420108 A CN 102420108A CN 2011101603093 A CN2011101603093 A CN 2011101603093A CN 201110160309 A CN201110160309 A CN 201110160309A CN 102420108 A CN102420108 A CN 102420108A
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Abstract
The invention relates to a copper damascene process and a structure, in particular to a process for manufacturing a metal-insulator-metal capacitor by adopting a copper damascene process, and a structure. According to the structure of the metal-insulator-metal capacitor structure and the process for manufacturing the metal-insulator-metal capacitor structure by adopting the copper damascene process, the metal-insulator-metal capacitor and an inductor are simultaneously manufactured by adopting the copper damascene process; a third electrode and other structures are simultaneously manufactured; a dielectric barrier layer is removed in the manufacturing process of a second electrode and the third electrode; and a dielectric layer made of a high-dielectric-constant material is re-deposited as an intermetallic insulating layer, so that the structure of the metal-insulator-metal double-layer capacitor produced by adopting the technical scheme provided by the invention can be completely compatible with the copper damascene process of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) logic circuit and the inductor; and the density of the metal-insulator-metal capacitor is increased.
Description
Technical field
The present invention relates to a kind of copper Damascus technics and structure, relate in particular to copper Damascus technics metal-insulating layer-metal capacitor manufacturing process and structure.
Background technology
Along with reducing of feature sizes of semiconductor devices, the semiconductor rear section copper wiring replaces aluminum manufacturing procedure becomes main flow technology.In mixed signal and radio circuit, exploitation (Metal-Insulator-Metal the is called for short MIM) capacitance structure and the manufacturing process of the copper Damascus technics of CMOS compatible logical circuit and inductance fully necessitates.This has not only improved the complexity of technology; And use low resistance copper can improve the MIM capacitive property as battery lead plate.
Patent US6329234, the structure and the technological process of process for copper CMOS compatible metal-insulating layer-metal capacitor, the technical scheme that it adopted is in double damask structure, to make individual layer Damascus MIM electric capacity.
Patent US6670237, the structure and the technological process of process for copper CMOS compatible metal-insulating layer-metal capacitor, the technical scheme that it adopted is in the through-hole structure of single Damascus, to make individual layer Damascus MIM electric capacity.
And, must reduce the MIM capacity area along with the reducing of semiconductor dimensions.This just requires to increase capacitance density.
Double-deck mim capacitor structure and copper Damascus manufacturing process that the present invention proposes, the MIM of the copper Damascus technics of CMOS compatible logical circuit and inductance, and increase fully capacitance density.
Summary of the invention
The invention discloses a kind of copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, Make double-level-metal-insulating barrier-metal capacitor structure and copper Damascus manufacturing process thereof; CMOS compatible logical circuit and inductance fully, and increase the capacitance density of metal-insulating layer-metal capacitor, its process comprises the steps:
Adopt Damascus technics, etching forms first electrode trenches and matrix interconnection line groove on a matrix dielectric layer, in said first electrode trenches and said matrix interconnection line groove, forms first electrode and matrix interconnection line;
Deposit first dielectric barrier layer and first dielectric layer form via dielectric layer successively; The said via dielectric layer of etching to said first electrode forms second electrode trenches, is formed with the dislocation zone between wherein said second electrode trenches and said first electrode;
Deposit first metal barrier, first insulating barrier, second metal barrier and copper seed layer successively again, and electroplate and fill after metallic copper is full of second electrode trenches, carry out planarization to remove excess metal, form second electrode;
Deposit second dielectric barrier layer and second dielectric layer form trench dielectric layer successively afterwards; The said trench dielectric layer of etching forms the third electrode groove to said second electrode, and said third electrode groove be positioned at said first electrode and said second electrode overlap part directly over;
Deposit the 3rd metal barrier and second insulating barrier successively again;
Make through hole, be connected the second electrode interconnection line trenches and connecting through hole interconnection line groove with etching through via process photoetching behind groove or the first groove behind the dual damascene elder generation through hole, make said through hole pass said via dielectric layer, connect said metal interconnecting wires; Make the said connection second electrode interconnection line trenches pass said second insulating barrier, said the 3rd metal barrier and said trench dielectric layer, connect said second electrode; Make said connecting through hole interconnection line groove pass said second insulating barrier, said the 3rd metal barrier and said trench dielectric layer, connect said through hole;
Deposit the 4th metal barrier and copper seed layer are successively again electroplated and are filled metallic copper and be full of the third electrode groove, connect the second electrode interconnection line trenches, through hole and connecting through hole interconnection line groove; Cmp carries out planarization, removes excess metal, forms third electrode, through hole, the connection second electrode interconnection line and connecting through hole interconnection line.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, In said first electrode trenches and said matrix interconnection line groove; Deposit parent metal barrier layer and copper seed layer successively, said parent metal barrier layer cover bottom and the sidewall of said first electrode trenches, bottom and the sidewall and the remaining matrix dielectric layer of said matrix interconnection line groove, fill metallic copper and make it to be full of first electrode trenches and matrix interconnection line groove; Carry out planarization afterwards to remove excess metal, form first electrode and matrix interconnection line.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, the material of said matrix dielectric layer, said first dielectric layer and said second dielectric layer adopts in the silex glass of silicon dioxide, hydrocarbon silica or doped with fluorine any one.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, the material that adopts of said parent metal barrier layer, said first metal barrier, said second metal barrier, said the 3rd metal barrier and said the 4th metal barrier be in tantalum nitride, tantalum, titanium nitride, the titanium any one or multiple.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, above-mentioned cement copper inculating crystal layer adopts physical vapor deposition process; Filling metallic copper all adopts the electrochemistry copper-plating technique to fill.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, said planarization all adopts chemical mechanical milling tech to carry out planarization.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, Said etching forms first electrode trenches and matrix interconnection line groove, promptly forms first photoresistance of said first electrode trenches and said matrix interconnection line groove shape through photoetching process, is that mask carries out etching with said first photoresistance afterwards; Form said first electrode trenches and said matrix interconnection line groove, and remove said first photoresistance.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, said via dielectric layer and said trench dielectric layer all adopt chemical vapor deposition method to form.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, the material of said first dielectric barrier layer and said second dielectric barrier layer is silicon nitride or carbonitride of silicium.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, The said via dielectric layer of said etching is said first electrode extremely, promptly forms second photoresistance of the said second electrode trenches shape through photoetching process, is that mask carries out etching with said second photoresistance afterwards; Form said second electrode trenches, and remove said second photoresistance.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, said first metal barrier of deposit, said first insulating barrier, said the 3rd metal barrier and said second insulating barrier all adopt atomic layer deposition or guarantor's type film deposition art to prepare.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, said first insulating barrier and the said second insulating barrier material are silicon nitride, silicon dioxide or high dielectric constant material.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process, wherein, said high dielectric constant material is hafnium oxide, Zirconium oxide, aluminum oxide or lanthanum-oxides etc.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, The said trench dielectric layer of said etching is said second electrode extremely, promptly forms the 3rd photoresistance of said third electrode groove shape through photoetching process, is that mask carries out etching with said the 3rd photoresistance afterwards; Form said third electrode groove, and remove said the 3rd photoresistance.
The present invention also provides a kind of copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, comprising:
One matrix dielectric layer is disposed with first dielectric barrier layer, first dielectric layer, second dielectric barrier layer and second dielectric layer from bottom to up in proper order on the said matrix dielectric layer; Said first dielectric barrier layer and said first dielectric layer constitute via dielectric layer, and said second dielectric barrier layer and said second dielectric layer constitute trench dielectric layer;
First electrode and at least one matrix interconnection line embed fully and are arranged among the said matrix dielectric layer; And its upper surface all part contacts with said first dielectric barrier layer, between said first electrode and the said matrix dielectric layer, be provided with the parent metal barrier layer between said interconnection line and the said matrix dielectric layer;
Second electrode embeds fully and is arranged among the said via dielectric layer; And its upper surface portion contacts with said second dielectric barrier layer, is disposed with first metal barrier, first insulating barrier and second metal barrier between said second electrode and the said via dielectric layer from outside to inside in proper order; The said first metal barrier lower surface contacts with the part upper surface of said first electrode and said matrix dielectric layer respectively; Be formed with the dislocation zone between said second electrode and said first electrode;
Third electrode be connected the second electrode interconnection line and embed fully and be arranged among the said trench dielectric layer; Be disposed with the 3rd metal barrier, second insulating barrier and the 4th metal barrier in proper order from outside to inside between said third electrode and the said trench dielectric layer, the lower surface of said the 3rd metal barrier contacts with the part upper surface of said second electrode; Be provided with the 4th metal barrier equally between said connection second electrode interconnection line and the said trench dielectric layer, and the part upper surface of second electrode in its lower surface and the said dislocation zone contacts;
The connecting through hole interconnection line embeds fully and is set in place among the said trench dielectric layer of said matrix interconnection line top; The corresponding matrix interconnection line of through hole position embeds fully and is set in place among the said via dielectric layer in said matrix interconnection line top; The upper surface of said through hole contacts with the part lower surface of said connecting through hole interconnection line and forms an overall structure; Between said connecting through hole interconnection line and said trench dielectric layer and the via dielectric layer; And be provided with the 4th metal barrier equally between said through hole and the via dielectric layer; The lower surface of its through hole is connected with the upper surface of said interconnection line, and the part lower surface of connecting through hole interconnection line contacts with the upper surface of said first dielectric layer.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure; Wherein, the material that adopts of said parent metal barrier layer, first metal barrier, said second metal barrier, said the 3rd metal barrier and said the 4th metal barrier be in tantalum nitride, tantalum, titanium nitride, the titanium any one or multiple.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, the material of said matrix dielectric layer, said first dielectric layer and said second dielectric layer adopts in the silex glass of silicon dioxide, hydrocarbon silica or doped with fluorine any one.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure; Wherein, Said first electrode, said second electrode, said third electrode, said through hole, the said connection second electrode interconnection line and said connecting through hole interconnection line metallic copper are all through the cement copper inculating crystal layer and adopt the electrochemistry copper-plating technique to form.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, said via dielectric layer and said trench dielectric layer all adopt chemical vapor deposition method to form.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, the material of said first dielectric barrier layer and said second dielectric barrier layer is silicon nitride or carbonitride of silicium.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure; Wherein, said first metal barrier, said first insulating barrier, said the 3rd metal barrier and said second insulating barrier all adopt atomic layer deposition or guarantor's type film deposition art to prepare.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, said first insulating barrier and the said second insulating barrier material are silicon nitride, silicon dioxide or high dielectric constant material.
Above-mentioned copper Damascus technics metal-insulating layer-metal capacitor structure, wherein, said high dielectric constant material is hafnium oxide, Zirconium oxide, aluminum oxide or lanthanum-oxides etc.
In sum; Owing to adopted technique scheme; The structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; Make metal-insulating layer-metal capacitor and inductance simultaneously through using Damascus technics; Third electrode and other structures are made simultaneously, and in second electrode and third electrode manufacturing process, remove dielectric barrier layer, and the dielectric layer of depositing high dielectric constant material is as internallic insulating layers again; Make the metal-insulator-metal double layer capacity structure produced through technical scheme of the present invention copper Damascus technics of CMOS compatible logical circuit and inductance fully and increase metal-insulating layer-metal capacitor density.
Description of drawings
Fig. 1 a-l is the schematic flow sheet of copper Damascus technics metal-insulating layer-metal capacitor manufacturing process of the present invention;
Fig. 2 is the sketch map of copper Damascus technics metal-insulating layer-metal capacitor structure of the present invention.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Shown in Fig. 1 a-l; The invention provides a kind of copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; Wherein, make double-level-metal-insulating barrier-metal capacitor structure and copper Damascus manufacturing process thereof, fully CMOS compatible logical circuit and inductance; And the capacitance density of increase metal-insulating layer-metal capacitor, its process comprises the steps:
Adopting Damascus technics, is silicon dioxide (SiO in material
2), silex glass (the Fluorinated Silicate Glass of hydrocarbon silica (SiOCH) or doped with fluorine; Be called for short FSG) on any one the matrix dielectric layer 102; Form first electrode trenches be positioned on the matrix dielectric layer and first photoresistance of matrix interconnection line groove shape through photoetching process; Be that mask carries out etching matrix dielectric layer with first photoresistance afterwards, form first electrode trenches 14 and matrix interconnection line groove 131,132, and remove first photoresistance; Deposit parent metal barrier layer 103 and copper seed layer cover bottom and the sidewall of first electrode trenches 14, bottom and the sidewall and the remaining matrix dielectric layer 102 of matrix interconnection line groove 131,132 successively
1Adopt electrochemistry copper-plating technique (Electrochemical plating copper process; Abbreviation ECP) carries out electro-coppering 104 and make it to be full of first electrode trenches 14 and matrix interconnection line groove 131,132; Adopt chemical mechanical milling tech (Chemical mechanical Polishing is called for short CMP) to carry out planarization, form first electrode 104 to remove excess metal
1, first electrode 104
1With remaining matrix dielectric layer 102
1Between remaining parent metal barrier layer 103
1, matrix interconnection line 105
1, matrix interconnection line 105
1With remaining matrix dielectric layer 102
1Between remaining parent metal barrier layer 103
2, matrix interconnection line 105
2, matrix interconnection line 105
2With remaining matrix dielectric layer 102
1Between remaining parent metal barrier layer 103
3Wherein, because the electric capacity of producing through technical scheme provided by the invention can have independently circuit structure,, also can in die cavity (tool), make separately so matrix dielectric layer 102 can be deposited on the matrix.
Adopt chemical vapor deposition method (Chemical Vapor Deposition; Be called for short CVD) deposit first dielectric barrier layer 106 and first dielectric layer 107 successively; The material of first dielectric barrier layer 106 is silicon nitride (SiN) or carbonitride of silicium (SiCN), and it covers first electrode 104
1, matrix interconnection line 105
1, matrix interconnection line 105
2With remaining matrix dielectric layer 102
1, first dielectric layer 107 covers first dielectric barrier layer, 106, the first dielectric layers 107 and first dielectric barrier layer 106 constitutes via dielectric layer 120.
Forming second photoresistance of the second electrode trenches shape through photoetching process, is that mask carries out etching through hole dielectric layer 120 to first electrodes 104 with second photoresistance afterwards
1With matrix dielectric layer 102
1, form said second electrode trenches 133 and remaining via dielectric layer 120
1, and remove above-mentioned second photoresistance; Wherein, second electrode trenches 133 and first electrode 104
1Between form dislocation zone 134.
Adopt atomic layer deposition technology (Atomic Layer Deposition is called for short ALD) deposit first metal barrier 108 and first insulating barrier, 109, the first metal barriers, 108 covering residue via dielectric layer 107 successively
1, remaining second electrode trenches 133
1First electrode and sidewall thereof on the bottom, first insulating barrier 109 covers first metal barrier 108, and wherein, the material of first insulating barrier 109 is silicon nitride (SiN), silicon dioxide (SiO
2) or hafnium oxide (HfO), Zirconium oxide (ZrO), aluminum oxide (AlO), lanthanum-oxides high dielectric constant materials such as (LaO).
Deposit second metal barrier 110 and the copper seed layer successively again; Second metal barrier 110 covers first insulating barrier 109; Copper seed layer covers second metal barrier 110, adopts the electrochemistry copper-plating technique to electroplate filling metallic copper 111 equally and is full of second electrode trenches 133
1, adopt chemical mechanical milling tech to carry out planarization to remove excess metal, form second electrode 111
1And second electrode 111
1With remaining first dielectric layer 107
1Between remaining first metal barrier 108
1, first insulating barrier 109
1, second metal barrier 110
1
Adopt chemical vapor deposition method successively deposit second dielectric barrier layer 112 and second dielectric layer, 113, the second dielectric barrier layers, 112 materials be silicon nitride (SiN) or carbonitride of silicium (SiCN), it covers second electrode 111
1And remaining first dielectric layer 107
1, second dielectric layer 113 covers second dielectric barrier layer, 112, the second dielectric barrier layers 112 and second dielectric layer 113 forms trench dielectric layer 121.
Continuing to form through photoetching process the 3rd photoresistance of third electrode groove shape, is that mask carries out etching groove dielectric layer 121 to second electrodes 111 with the 3rd photoresistance afterwards
1, form said third electrode groove 135 and remaining trench dielectric layer 121
1, and remove above-mentioned the 3rd photoresistance; Wherein, third electrode groove 135 is positioned at second electrode 111
1With first electrode 114
1Overlapping part on.
Adopt atomic layer deposition technology, deposit the 3rd metal barrier 114 and second insulating barrier, 115, the three metal barriers 114 cover remaining trench dielectric layer 121 successively
1, third electrode groove 135 bottoms second electrode and sidewall thereof, second insulating barrier 115 covers the 3rd metal barrier 114; Wherein, the material that the 3rd metal barrier 114 adopts be in tantalum nitride, tantalum, titanium nitride, the titanium any one or multiple, the material of second insulating barrier 115 is silicon nitride (SiN), silicon dioxide (SiO
2) or hafnium oxide (HfO), Zirconium oxide (ZrO), aluminum oxide (AlO), lanthanum-oxides high dielectric constant materials such as (LaO).
Make through hole 138,139 and be connected the second electrode interconnection line trenches 136 and connecting through hole interconnection line groove 137 with etching through via process photoetching behind the dual damascene elder generation groove: photoetching forms and connects the second electrode interconnection line trenches and connecting through hole interconnection line groove figure, etching second insulating barrier, the 3rd metal barrier and trench dielectric layer 121
1, form the connection second electrode interconnection line trenches 136 and connecting through hole interconnection line groove 137; Then, photoetching forms via hole image, etching through hole dielectric layer 120
1Form through hole 138,139; Make said through hole 138,139 pass said via dielectric layer 121
1, connect said metal interconnecting wires 105
1, 105
2Make said connection second electrode interconnection line trenches 136 and connecting through hole interconnection line groove 137 pass said second insulating barrier 115, said the 3rd metal barrier 114 and said trench dielectric layer 121
1, connect said second electrode 111 respectively
1With said through hole 138,139; For fear of the damage of said dual damascene photoetching and etching technics to second insulating barrier; But can be on second insulating barrier 115 conducting metal protective layer such as physical vapor deposition or chemical vapor deposition one deck TiN, Ti, TaN, Ta; But said conducting metal protective layer can form through hole 138,139 and be connected the second electrode interconnection line trenches 136 and the 137 back wet methods removals of connecting through hole interconnection line groove in said dual damascene process etching, removes unnecessary conducting metal protective layer in the excess metal process but also can remove at follow-up said cmp;
Deposit the 4th metal barrier 116 and copper seed layer successively, the 4th metal barrier 116 covers residue second insulating barrier 115
1, connect the trench dielectric layer of the second electrode interconnection line trenches, 136 sidewalls and second electrode of bottom thereof, trench dielectric layer and the via dielectric layer of bottom, the via dielectric layer of through hole 138,139 sidewalls and the matrix interconnection line of bottom thereof of connecting through hole interconnection line groove 137 sidewalls; Copper seed layer covers the 4th metal barrier 116, adopts the electrochemistry copper-plating technique to electroplate filling metallic copper 117 and is full of residue third electrode groove 135
1, connect the second electrode interconnection line trenches 136, through hole 138,139 and connecting through hole interconnection line groove 137.
Adopt chemical mechanical milling tech to carry out planarization at last, form third electrode 117 to remove excess metal
1, connect the second electrode interconnection line 117
2, connecting through hole interconnection line 117
3And through hole 118,119.
Wherein, the material of matrix dielectric layer 102, first dielectric layer 107 and second dielectric layer 113 adopts silicon dioxide (SiO
2), in the silex glass (FSG) of hydrocarbon silica (SiOCH) or doped with fluorine any one.
Further, the material that adopts of parent metal barrier layer 103, first metal barrier 108, second metal barrier 110, the 3rd metal barrier 114 and the 4th metal barrier 116 be in tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), the titanium (Ti) any one or multiple.
As shown in Figure 2; The present invention also provides a kind of copper Damascus technics metal-insulating layer-metal capacitor structure; Wherein, comprising: on the matrix dielectric layer 202 from bottom to up order be disposed with first dielectric barrier layer 206, first dielectric layer 207, second dielectric barrier layer 212 and second dielectric layer 213; First dielectric barrier layer 206 and first dielectric layer 207 constitute via dielectric layer 220, the second dielectric barrier layers 212 and second dielectric layer 213 constitutes trench dielectric layer 221.
Connecting through hole interconnection line 217
3Embed fully and be set in place in matrix interconnection line 205,205
1Among the trench dielectric layer of top, through hole 218,219 corresponding matrix interconnection lines 205,205
1The position embeds fully and is set in place in matrix interconnection line 205,205
1Among the via dielectric layer 220 of top, the upper surface of through hole 218,219 and connecting through hole interconnection line 217
3Part lower surface contact form an overall structure, connecting through hole interconnection line 217
3And between trench dielectric layer 221 and the via dielectric layer 220, and be provided with the 4th metal barrier 216 equally between through hole 218,219 and the via dielectric layer 220
3, the lower surface of its through hole 218,219 respectively with interconnection line 205,205
1Part upper surface contact, connecting through hole interconnection line 217
3The part lower surface contact with the upper surface of first dielectric layer 207.
Wherein, parent metal barrier layer 203, first metal barrier 208, second metal barrier 210, the 3rd metal barrier 214 and the 4th metal barrier 216
1, 216
2, 216
3The material that adopts be in tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), the titanium (Ti) etc. any one or multiple.
Further, the material of matrix dielectric layer 202, first dielectric layer 207 and second dielectric layer 213 adopts silicon dioxide (SiO
2), in the silex glass (Fluorinated Silicate Glass is called for short FSG) of hydrocarbon silica (SiOCH) or doped with fluorine any one.
Further, first electrode 204, second electrode 211, third electrode 217, connect the second electrode interconnection line 217
2, connecting through hole interconnection line 217
3And through hole 218,219 metallic coppers, all through the cement copper inculating crystal layer and adopt electrochemistry copper-plating technique (Electrochemical plating copper process, be called for short ECP) to form.
Further, via dielectric layer 220 all adopts chemical vapor deposition method (Chemical Vapor Deposition is called for short CVD) to form with trench dielectric layer 221.
Further, the material of first dielectric barrier layer 206 and second dielectric barrier layer 212 is silicon nitride (SiN) or carbonitride of silicium (SiCN).
Further; First metal barrier 208, first insulating barrier 209, the 3rd metal barrier 214 and second insulating barrier 215 all adopt atomic layer deposition technology (Atomic Layer Deposition; Be called for short ALD) or guarantor's type thin film deposition (Conformal Film Deposition is called for short CFD) technology prepare.
Further, first insulating barrier 209 and second insulating barrier, 215 materials are silicon nitride (SiN), silicon dioxide (SiO
2) or hafnium oxide (HfO), Zirconium oxide (ZrO), aluminum oxide (AlO), lanthanum-oxides high dielectric constant materials such as (LaO).
Disclosed processing step of the present invention and structure are in the single-layer metal layer, to make multiple layer metal-insulating barrier-metal capacitance; Certainly the present invention is not limited only to single-layer metal, and the disclosed method and structure of the present invention is applicable to too makes the more metal-insulating layer-metal capacitor of multilayer in the multiple layer metal.
In sum; Owing to adopted technique scheme; Copper Damascus technics metal-insulating layer-metal capacitor manufacturing process of the present invention and structure; Make metal-insulating layer-metal capacitor and inductance simultaneously through using Damascus technics; Third electrode and other structures are made simultaneously, and in second electrode and third electrode manufacturing process, remove dielectric barrier layer, and the dielectric layer of depositing high dielectric constant material is as internallic insulating layers again; Make the metal-insulator-metal double layer capacity structure produced through technical scheme of the present invention copper Damascus technics of CMOS compatible logical circuit and inductance fully and increase metal-insulating layer-metal capacitor density.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (23)
1. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process; It is characterized in that; Make double-level-metal-insulating barrier-metal capacitor structure and copper Damascus manufacturing process thereof; CMOS compatible logical circuit and inductance fully, and increase the capacitance density of metal-insulating layer-metal capacitor, its process comprises the steps:
Adopt Damascus technics, etching forms first electrode trenches and matrix interconnection line groove on a matrix dielectric layer, in said first electrode trenches and said matrix interconnection line groove, forms first electrode and matrix interconnection line;
Deposit first dielectric barrier layer and first dielectric layer form via dielectric layer successively; The said via dielectric layer of etching to said first electrode forms second electrode trenches, is formed with the dislocation zone between wherein said second electrode trenches and said first electrode;
Deposit first metal barrier, first insulating barrier, second metal barrier and first copper seed layer successively again, and fill after metallic copper is full of second electrode trenches, carry out planarization to remove excess metal, form second electrode;
Deposit second dielectric barrier layer and second dielectric layer form trench dielectric layer successively afterwards; The said trench dielectric layer of etching forms the third electrode groove to said second electrode, and said third electrode groove be positioned at said first electrode and said second electrode overlap part directly over;
Deposit the 3rd metal barrier and second insulating barrier successively again;
Make through hole, be connected the second electrode interconnection line trenches and connecting through hole interconnection line groove with etching through via process photoetching behind groove or the first groove behind the dual damascene elder generation through hole, make said through hole pass said via dielectric layer, connect said metal interconnecting wires; Make the said connection second electrode interconnection line trenches pass said second insulating barrier, said the 3rd metal barrier and said trench dielectric layer, connect said second electrode; Make said connecting through hole interconnection line groove pass said second insulating barrier, said the 3rd metal barrier and said trench dielectric layer, connect said through hole;
Deposit the 4th metal barrier and copper seed layer are successively again electroplated and are filled metallic copper and be full of the third electrode groove, connect the second electrode interconnection line trenches, through hole and connecting through hole interconnection line groove; Cmp carries out planarization, removes excess metal, forms third electrode, through hole, the connection second electrode interconnection line and connecting through hole interconnection line.
2. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that; In said first electrode trenches and said matrix interconnection line groove; Deposit parent metal barrier layer and copper seed layer successively, said parent metal barrier layer cover bottom and the sidewall of said first electrode trenches, bottom and the sidewall and the remaining matrix dielectric layer of said matrix interconnection line groove, fill metallic copper and make it to be full of first electrode trenches and matrix interconnection line groove; Carry out planarization afterwards to remove excess metal, form first electrode and matrix interconnection line.
3. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that the material of said matrix dielectric layer, said first dielectric layer and said second dielectric layer adopts in the silex glass of silicon dioxide, hydrocarbon silica or doped with fluorine any one.
4. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that, the material that said parent metal barrier layer, said first metal barrier, said second metal barrier, said the 3rd metal barrier and said the 4th metal barrier adopt be in tantalum nitride, tantalum, titanium nitride, the titanium any one or multiple.
5. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1 is characterized in that, above-mentioned cement copper inculating crystal layer adopts physical vapor deposition process; Filling metallic copper all adopts the electrochemistry copper-plating technique to fill.
6. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1 is characterized in that said planarization all adopts chemical mechanical milling tech to carry out planarization.
7. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that; Said etching forms first electrode trenches and matrix interconnection line groove, promptly forms first photoresistance of said first electrode trenches and said matrix interconnection line groove shape through photoetching process, is that mask carries out etching with said first photoresistance afterwards; Form said first electrode trenches and said matrix interconnection line groove, and remove said first photoresistance.
8. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1 is characterized in that, said via dielectric layer and said trench dielectric layer all adopt chemical vapor deposition method to form.
9. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1 is characterized in that the material of said first dielectric barrier layer and said second dielectric barrier layer is silicon nitride or carbonitride of silicium.
10. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that; The said via dielectric layer of said etching is said first electrode extremely, promptly forms second photoresistance of the said second electrode trenches shape through photoetching process, is that mask carries out etching with said second photoresistance afterwards; Form said second electrode trenches, and remove said second photoresistance.
11. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that said first metal barrier of deposit, said first insulating barrier, said the 3rd metal barrier and said second insulating barrier all adopt atomic layer deposition or guarantor's type film deposition art to prepare.
12. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1 is characterized in that, said first insulating barrier and the said second insulating barrier material are silicon nitride, silicon dioxide or high dielectric constant material.
13. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 12 is characterized in that said high dielectric constant material is hafnium oxide, Zirconium oxide, aluminum oxide or lanthanum-oxides etc.
14. copper Damascus technics metal-insulating layer-metal capacitor manufacturing process according to claim 1; It is characterized in that; The said trench dielectric layer of said etching is said second electrode extremely, promptly forms the 3rd photoresistance of said third electrode groove shape through photoetching process, is that mask carries out etching with said the 3rd photoresistance afterwards; After forming said third electrode groove, remove said the 3rd photoresistance.
15. a copper Damascus technics metal-insulating layer-metal capacitor structure is characterized in that, comprising:
One matrix dielectric layer is disposed with first dielectric barrier layer, first dielectric layer, second dielectric barrier layer and second dielectric layer from bottom to up in proper order on the said matrix dielectric layer; Said first dielectric barrier layer and said first dielectric layer constitute via dielectric layer, and said second dielectric barrier layer and said second dielectric layer constitute trench dielectric layer;
First electrode and at least one matrix interconnection line embed fully and are arranged among the said matrix dielectric layer; And its upper surface all part contacts with said first dielectric barrier layer, between said first electrode and the said matrix dielectric layer, be provided with the parent metal barrier layer between said interconnection line and the said matrix dielectric layer;
Second electrode embeds fully and is arranged among the said via dielectric layer; And its upper surface portion contacts with said second dielectric barrier layer, is disposed with first metal barrier, first insulating barrier and second metal barrier between said second electrode and the said via dielectric layer from outside to inside in proper order; The said first metal barrier lower surface contacts with the part upper surface of said first electrode and said matrix dielectric layer respectively; Be formed with the dislocation zone between said second electrode and said first electrode;
Third electrode be connected the second electrode interconnection line and embed fully and be arranged among the said trench dielectric layer; Be disposed with the 3rd metal barrier, second insulating barrier and the 4th metal barrier in proper order from outside to inside between said third electrode and the said trench dielectric layer, the lower surface of said the 3rd metal barrier contacts with the part upper surface of said second electrode; Be provided with the 4th metal barrier equally between said connection second electrode interconnection line and the said trench dielectric layer, and the part upper surface of second electrode in its lower surface and the said dislocation zone contacts;
The connecting through hole interconnection line embeds fully and is set in place among the said trench dielectric layer of said matrix interconnection line top; The corresponding matrix interconnection line of through hole position embeds fully and is set in place among the said via dielectric layer in said matrix interconnection line top; The upper surface of said through hole contacts with the part lower surface of said connecting through hole interconnection line and forms an overall structure; Between said connecting through hole interconnection line and said trench dielectric layer and the via dielectric layer; And be provided with the 4th metal barrier equally between said through hole and the via dielectric layer; The part lower surface of its through hole is connected with the upper surface of said interconnection line, and the part lower surface of connecting through hole interconnection line contacts with the upper surface of said first dielectric layer.
16. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15; It is characterized in that, the material that said parent metal barrier layer, first metal barrier, said second metal barrier, said the 3rd metal barrier and said the 4th metal barrier adopt be in tantalum nitride, tantalum, titanium nitride, the titanium any one or multiple.
17. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15; It is characterized in that the material of said matrix dielectric layer, said first dielectric layer and said second dielectric layer adopts in the silex glass of silicon dioxide, hydrocarbon silica or doped with fluorine any one.
18. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15; It is characterized in that; Said first electrode, said second electrode, said third electrode, said through hole, the said connection second electrode interconnection line and said connecting through hole interconnection line metallic copper are all through the cement copper inculating crystal layer and adopt the electrochemistry copper-plating technique to form.
19. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15 is characterized in that, said via dielectric layer and said trench dielectric layer all adopt chemical vapor deposition method to form.
20. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15 is characterized in that the material of said first dielectric barrier layer and said second dielectric barrier layer is silicon nitride or carbonitride of silicium.
21. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15; It is characterized in that said first metal barrier, said first insulating barrier, said the 3rd metal barrier and said second insulating barrier all adopt atomic layer deposition or guarantor's type film deposition art to prepare.
22. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 15 is characterized in that, said first insulating barrier and the said second insulating barrier material are silicon nitride, silicon dioxide or high dielectric constant material.
23. copper Damascus technics metal-insulating layer-metal capacitor structure according to claim 22 is characterized in that said high dielectric constant material is hafnium oxide, Zirconium oxide, aluminum oxide or lanthanum-oxides.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| CN108962873A (en) * | 2018-09-04 | 2018-12-07 | 长鑫存储技术有限公司 | Compound double damask structure and preparation method thereof |
| CN113130442A (en) * | 2020-01-15 | 2021-07-16 | 广东汉岂工业技术研发有限公司 | MIM capacitor and method for manufacturing the same |
| US20210343829A1 (en) * | 2014-04-30 | 2021-11-04 | Stmicroelectronics, Inc. | Dram interconnect structure having ferroelectric capacitors exhibiting negative capacitance |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329234B1 (en) * | 2000-07-24 | 2001-12-11 | Taiwan Semiconductor Manufactuirng Company | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
| US6638830B1 (en) * | 2002-09-18 | 2003-10-28 | United Microelectronics Corp. | Method for fabricating a high-density capacitor |
| US20060234443A1 (en) * | 2005-04-15 | 2006-10-19 | Chih-Chao Yang | MIM capacitor and method of fabricating same |
| US20070037405A1 (en) * | 2005-08-10 | 2007-02-15 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers and devices so formed |
| CN101174585A (en) * | 2006-11-03 | 2008-05-07 | 东部高科股份有限公司 | Method for manufacturing semiconductor device having damascene MIM type capacitor |
| CN102420105A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Process for manufacturing metal-insulator-metal capacitor by using copper damascene process, and structure |
| CN102420107A (en) * | 2011-06-15 | 2012-04-18 | 上海华力微电子有限公司 | Copper Damascus process MIM (metal-insulator-metal) capacitor manufacturing process and structure |
-
2011
- 2011-06-15 CN CN 201110160309 patent/CN102420108B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329234B1 (en) * | 2000-07-24 | 2001-12-11 | Taiwan Semiconductor Manufactuirng Company | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
| US6638830B1 (en) * | 2002-09-18 | 2003-10-28 | United Microelectronics Corp. | Method for fabricating a high-density capacitor |
| US20060234443A1 (en) * | 2005-04-15 | 2006-10-19 | Chih-Chao Yang | MIM capacitor and method of fabricating same |
| US20070037405A1 (en) * | 2005-08-10 | 2007-02-15 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers and devices so formed |
| CN101174585A (en) * | 2006-11-03 | 2008-05-07 | 东部高科股份有限公司 | Method for manufacturing semiconductor device having damascene MIM type capacitor |
| CN102420105A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Process for manufacturing metal-insulator-metal capacitor by using copper damascene process, and structure |
| CN102420107A (en) * | 2011-06-15 | 2012-04-18 | 上海华力微电子有限公司 | Copper Damascus process MIM (metal-insulator-metal) capacitor manufacturing process and structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| US20210343829A1 (en) * | 2014-04-30 | 2021-11-04 | Stmicroelectronics, Inc. | Dram interconnect structure having ferroelectric capacitors exhibiting negative capacitance |
| US11664415B2 (en) * | 2014-04-30 | 2023-05-30 | Stmicroelectronics, Inc. | Method of making interconnect structure having ferroelectric capacitors exhibiting negative capacitance |
| CN108962873A (en) * | 2018-09-04 | 2018-12-07 | 长鑫存储技术有限公司 | Compound double damask structure and preparation method thereof |
| CN108962873B (en) * | 2018-09-04 | 2023-07-04 | 长鑫存储技术有限公司 | Composite dual damascene structure and preparation method thereof |
| CN113130442A (en) * | 2020-01-15 | 2021-07-16 | 广东汉岂工业技术研发有限公司 | MIM capacitor and method for manufacturing the same |
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Inventor after: Li Lei Inventor after: Hu Youcun Inventor after: Chen Yuwen Inventor after: Ji Feng Inventor after: Zhang Liang Inventor before: Li Lei Inventor before: Hu Youcun Inventor before: Chen Yuwen Inventor before: Ji Feng Inventor before: Zhang Liang |