CN102457274A - Digital frequency synthesizer having phase-locking loop - Google Patents
Digital frequency synthesizer having phase-locking loop Download PDFInfo
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- CN102457274A CN102457274A CN2010105146745A CN201010514674A CN102457274A CN 102457274 A CN102457274 A CN 102457274A CN 2010105146745 A CN2010105146745 A CN 2010105146745A CN 201010514674 A CN201010514674 A CN 201010514674A CN 102457274 A CN102457274 A CN 102457274A
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Abstract
The invention discloses a digital frequency synthesizer having a phase-locking loop. The digital frequency synthesizer has a clock tracking unit, a first phase-locking circuit which is connected with the clock tracking unit, a digital frequency-eliminating unit which is connected with the clock tracking unit and the first phase-locking circuit, and a second phase-locking circuit which is arranged behind the digital frequency-eliminating unit and connected with the digital frequency-eliminating unit, wherein the digital frequency-eliminating unit controls the number of clocks in a unit clock group; the clock tracking unit tracks the clocks of incident signals to increase or decrease the number of the clocks in the digital frequency-eliminating unit so as to achieve an effect of accelerating or decelerating the clocks; the first phase-locking circuit and the second phase-locking circuit are used together with the digital frequency-eliminating unit for multiplying clock frequency; and the second phase-locking circuit is used for absorbing clock disturbance after the digital frequency-eliminating unit increases or decreases the number of the clocks.
Description
Technical field
The present invention relates to a kind of frequency synthesizer, relate in particular to a kind of digital frequency synthesizer with phase-locked loop.
Background technology
Along with the progress in epoch, the technology development of constantly bringing forth new ideas, the density of high speed processing speed and integrated circuit all constantly increases.Therefore, the Synchronous Processing between each module be important problem.No matter on communication apparatus, apparatus measures, system are linked up, clock that must be through correspondence between each instrument is to link up and to measure.For instance, if oscillographic clock can't be synchronous with measuring instrument, just can't show precisely clear and definite waveform on that oscilloscope, waveform can be run along with the time, even can't see the waveform result.Like the music instrument, if the clock frequency of the voice data of media player output is can't be synchronous with the clock frequency of receiving terminal, just cause the distortion and the destruction of music quality easily in addition.
(Direct Digital Synthesizer DDS), produces the time-varying signal of digital form through DDS, carries out digital analogue conversion again and produces analog waveform and the solution of generally using at present is to use Direct Digital Frequency Synthesizers.Because the DDS device is to utilize digital form to reach, thereby can between output frequency, switches apace and have fine frequency resolution, can also use on frequency spectrum widely.But use the cost of DDS higher, be its major defect.
And the device and method of many control frequencys has appearred in industry; " frequency synthesizer with a plurality of frequency locking circuits " that existing as TaiWan, China patent announcement is I316793 number, its technology contents comprises a plurality of frequency locking circuits, selection circuit and control circuit.Frequency locking circuits is in order to lock a plurality of clock signals and to export those clock signals according to a plurality of reference clock signals respectively.It reaches the purpose of adjustable frequency through a plurality of frequency locking circuits, but a plurality of frequency locking circuits obviously can increase the area and the circuit cost of circuit design.
Announce the 7th for another United States Patent (USP); 560; No. 960 " Frequency synthesizerusing two phase locked loops "; It is mainly invented to using an Integer N phase-locked loop and mark N phase-locked loop, and it is through making up this Integer N phase-locked loop and this mark N phase-locked loop produces an output frequency signal.Cooperation through Integer N phase-locked loop and mark N phase-locked loop; Can reach the totalling of FREQUENCY CONTROL; And Integer N phase-locked loop and this mark N phase-locked loop are respectively by the signal controlling of high frequency and low frequency; Can reach the advantage of low phase noise and narrow channel separation, but frequency adds the frequency precision that always has influence on integral body.
Summary of the invention
Main purpose of the present invention is to solve existing designed circuit cost problem, and the accurate problem of the frequency of frequency synthesizer.
For realizing above-mentioned purpose; The present invention provides a kind of digital frequency synthesizer with phase-locked loop; It utilizes phase-locked loop (Phase Lock Loop; PLL) mode is carried out the adjustment of frequency, and the digital frequency synthesizer with phase-locked loop of the present invention comprises: the clock number purpose numeral frequency elimination unit in one first phase lock circuitry, a plurality of unit clock groups of a control reaches one second phase lock circuitry that is oppositely arranged with this first phase lock circuitry.This first phase lock circuitry is in order to receive an incoming signal.The input of this numeral frequency elimination unit is connected with this first phase lock circuitry.This second phase lock circuitry and this first phase lock circuitry are oppositely arranged, and this second phase lock circuitry is connected with the output of this numeral frequency elimination unit, and this first phase lock circuitry and this second phase lock circuitry cooperate this numeral frequency elimination unit to carry out the multiplication and division of frequency.
According to further improved plan of the present invention, first phase lock circuitry has one first multiplier parameter, and this first multiplier parameter is in order to the frequency of conversion incoming signal.
According to further improved plan of the present invention, second phase lock circuitry has one second multiplier parameter, and this second multiplier parameter is in order to change the frequency through the incoming signal behind the digital frequency elimination unit frequency elimination.
According to further improved plan of the present invention, this second phase lock circuitry is also in order to absorb through the clock disturbance behind this numeral frequency elimination unit increase and decrease clock.
Illustrate further, a plurality of these unit clock groups in this numeral frequency elimination unit have all been lacked a clock, and through can the clock in single or a plurality of unit clock groups being added and subtracted this numeral frequency elimination unit, to carry out the increase and decrease of clock frequency.
According to further improved plan of the present invention, have a clock tracing unit, first phase locking unit is connected with incoming signal through the clock tracing unit, and the clock tracing unit provides a clock control signal to digital frequency elimination unit.
Can know that by above-mentioned explanation compared to prior art, the present invention has following characteristics:
One, utilizes the cooperation of this first phase lock circuitry and this second phase lock circuitry, realize the multiplication and division of optional frequency.
Two,, reach the effect of clock increase and decrease speed through the clock number in a plurality of unit clock groups of this numeral frequency elimination unit controls.
Three, through the setting of this second phase lock circuitry, the clock disturbance (Clock Jitter) that is caused when absorbing this numeral frequency elimination unit because of plus-minus clock number.
Description of drawings
Fig. 1 is the square configuration schematic diagram of one embodiment of the present invention;
Fig. 2 A is the unit clock group sketch map of one embodiment of the present invention;
Fig. 2 B is that the unit clock group of one embodiment of the present invention increases sketch map; And
Fig. 2 C is that the unit clock group of one embodiment of the present invention reduces sketch map.
Embodiment
Relevant detailed description of the present invention and technology contents, as follows with regard to the conjunction with figs. explanation at present:
See also shown in Figure 1; It is the square configuration schematic diagram of one embodiment of the present invention; As shown in the figure: the present invention is a kind of digital frequency synthesizer with phase-locked loop; It comprises: one first phase lock circuitry 10, is controlled the clock number purpose numeral frequency elimination unit 20 in a plurality of unit clock groups, reaches one second phase lock circuitry 30 that is oppositely arranged with this first phase lock circuitry 10.This first phase lock circuitry 10 is in order to receive an incoming signal 1.The input of this numeral frequency elimination unit 20 is connected with this first phase lock circuitry 10.This second phase lock circuitry 30 is oppositely arranged with this first phase lock circuitry 10; This second phase lock circuitry 30 is connected with the output of this numeral frequency elimination unit 20; This first phase lock circuitry 10 and this second phase lock circuitry 30 cooperate this numeral frequency elimination unit 20 to carry out the multiplication and division of frequency, and this second phase lock circuitry 30 is more in order to absorb through the clock disturbance behind this numeral frequency elimination unit 20 increase and decrease clocks.
In addition, the present invention also has a clock tracing unit 40, and this first phase lock circuitry 10 is connected with this incoming signal 1 through this clock tracing unit 40, and this clock tracing unit 40 provides a clock control signal to this numeral frequency elimination unit 20.And be to utilize the design of phase-locked loop (Phase Lock Loop) to accomplish about this first phase lock circuitry 10 and this second phase lock circuitry 30; The phase-locked loop is to utilize two dividers, phase detector (PhaseDetector), charge pump (Charge Pump) and voltage control oscillator (VoltageControl Oscillator); These two dividers are done M and N frequency division doubly respectively; Loop through these two dividers cooperates; Can reach M/N frequency inverted doubly, its detailed principle is non-to be emphasis of the present invention, just is not elaborated at this.
Please cooperate in addition and consult shown in Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 A is a unit clock group sketch map of the present invention, and Fig. 2 B is that unit clock group of the present invention increases sketch map, and Fig. 2 C is that unit clock group of the present invention reduces sketch map.In present embodiment; It is as a unit clock group 50a, 50b, 50c with 10 clocks; And clock signal is made up of a plurality of unit clock group 50a, 50b, 50c; And, at first set and all lacked the 5th clock signal among the per unit clock group 50a, so just reduced by 100,000 clocks in each 1,000,000 clock signal by shown in Fig. 2 A.When if this clock tracing unit 40 finds that frequency need be accelerated; Just inform that through this clock control signal digital frequency elimination unit 20 quickens; By finding out among Fig. 2 B; This numeral frequency elimination unit 20 (being shown in Fig. 1) just will be wherein the 5th clock signal among one group of unit clock group 50b refill, produced and quickened millionth effect.And by knowing among Fig. 2 C; And when if this clock tracing unit 40 finds that frequencies need slow down; Just can a clock among one group of unit clock group 50c wherein be destroyed again,, destroy the 8th clock signal exactly according to present embodiment; Let and wherein only be left eight clock signals among one group of clock signal group 50c, produce the millionth effect of slowing down.Except using the clock number of 10 clocks as a unit clock group 50a, 50b, 50c, also can use 25 clocks or 50 clocks etc. to be used as the clock number of unit clock group 50a, 50b, 50c, it depends on the demand of system fully and decides.
And this first phase lock circuitry 10 and this second phase lock circuitry 30 are separately positioned on the both sides of this numeral frequency elimination unit 20, respectively utilize the frequency of this incoming signal 1 of one first multiplier parameter and one second multiplier parameter conversion.This first multiplier parameter and this second multiplier parameter to should first phase lock circuitry 10 and this second phase lock circuitry 30 in two frequency eliminators and have the effect of N/M and A/B respectively; Therefore can carry out the multiple adjustment of frequency through four parameters, meticulousr fine-tuning capability is provided.
And carry out the increase and decrease of clock because of the clock among 20 couples of a plurality of this unit clock group 50a in this numeral frequency elimination unit, 50b, the 50c; It can cause the clock disturbance; And the setting through this second phase lock circuitry 30 just can absorb the clock perturbed problem that this numeral frequency elimination unit 20 is caused.
In sum, because the present invention utilizes the cooperation of this first phase lock circuitry 10 and this second phase lock circuitry 30, realize the multiplication and division of optional frequency.In addition, through the clock number among a plurality of unit clock group 50a of these numeral frequency elimination unit 20 controls, 50b, the 50c, reach the effect of clock increase and decrease speed.Moreover, utilize the setting of this second phase lock circuitry 30, the clock perturbed problem that is caused when absorbing this numeral frequency elimination unit 20 because of plus-minus clock number.
Below the present invention is done a detailed description, but the above is merely a preferred embodiment of the present invention, when not limiting the scope that the present invention implements.Be that all equalizations of doing according to application range of the present invention change and modify etc., all should still belong in the patent covering scope of the present invention.
Claims (5)
1. the digital frequency synthesizer with phase-locked loop is characterized in that, comprising: one first phase lock circuitry (10), and it receives an incoming signal (1);
Clock number purpose numeral frequency elimination unit (20) in the one a plurality of unit clock groups of control (50a, 50b, 50c), the input of said digital frequency elimination unit (20) is connected with said first phase lock circuitry (10); And
One second phase lock circuitry (30) that is oppositely arranged with said first phase lock circuitry (10); Said second phase lock circuitry (30) is connected with the output of said digital frequency elimination unit (20), and said first phase lock circuitry (10) and said second phase lock circuitry (30) cooperate said digital frequency elimination unit (20) to carry out the multiplication and division of frequency.
2. the digital frequency synthesizer with phase-locked loop according to claim 1 is characterized in that, said first phase lock circuitry (10) has one first multiplier parameter, and said first multiplier parameter is in order to change the frequency of said incoming signal (1).
3. the digital frequency synthesizer with phase-locked loop according to claim 2; It is characterized in that; Said second phase lock circuitry (30) has one second multiplier parameter, and said second multiplier parameter is in order to change the frequency through the incoming signal (1) behind said digital frequency elimination unit (20) frequency elimination.
4. the digital frequency synthesizer with phase-locked loop according to claim 1 is characterized in that, said second phase lock circuitry (30) absorbs through the clock disturbance behind said digital frequency elimination unit (20) increase and decrease clock.
5. the digital frequency synthesizer with phase-locked loop according to claim 1; It is characterized in that; Has a clock tracing unit (40); Said first phase locking unit is connected with said incoming signal (1) through said clock tracing unit (40), and said clock tracing unit (40) provides a clock control signal to said digital frequency elimination unit (20).
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010105146745A CN102457274A (en) | 2010-10-21 | 2010-10-21 | Digital frequency synthesizer having phase-locking loop |
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| CN2010105146745A CN102457274A (en) | 2010-10-21 | 2010-10-21 | Digital frequency synthesizer having phase-locking loop |
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| CN102457274A true CN102457274A (en) | 2012-05-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951149A (en) * | 2019-12-10 | 2021-06-11 | 瑞鼎科技股份有限公司 | LED display driving circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2299423Y (en) * | 1997-05-12 | 1998-12-02 | 中国科学院陕西天文台 | VHF frequency synthesizer |
| US7102690B2 (en) * | 2002-03-12 | 2006-09-05 | Via Technologies Inc. | Clock signal synthesizer with multiple frequency outputs and method for synthesizing clock signal |
| JP3957311B2 (en) * | 2005-12-05 | 2007-08-15 | ローム株式会社 | FM transmitter |
| CN101183871A (en) * | 2007-12-17 | 2008-05-21 | 华为技术有限公司 | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus |
| CN101409803A (en) * | 2007-10-10 | 2009-04-15 | 安国国际科技股份有限公司 | Frequency synthesizer applied for digital TV tuner |
| US20100020730A1 (en) * | 2008-07-25 | 2010-01-28 | Analog Devices, Inc. | Frequency synthesizers for wireless communication systems |
-
2010
- 2010-10-21 CN CN2010105146745A patent/CN102457274A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2299423Y (en) * | 1997-05-12 | 1998-12-02 | 中国科学院陕西天文台 | VHF frequency synthesizer |
| US7102690B2 (en) * | 2002-03-12 | 2006-09-05 | Via Technologies Inc. | Clock signal synthesizer with multiple frequency outputs and method for synthesizing clock signal |
| JP3957311B2 (en) * | 2005-12-05 | 2007-08-15 | ローム株式会社 | FM transmitter |
| CN101409803A (en) * | 2007-10-10 | 2009-04-15 | 安国国际科技股份有限公司 | Frequency synthesizer applied for digital TV tuner |
| CN101183871A (en) * | 2007-12-17 | 2008-05-21 | 华为技术有限公司 | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus |
| US20100020730A1 (en) * | 2008-07-25 | 2010-01-28 | Analog Devices, Inc. | Frequency synthesizers for wireless communication systems |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951149A (en) * | 2019-12-10 | 2021-06-11 | 瑞鼎科技股份有限公司 | LED display driving circuit |
| CN112951149B (en) * | 2019-12-10 | 2024-03-15 | 瑞鼎科技股份有限公司 | Light emitting diode display driving circuit |
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Application publication date: 20120516 |