CN102543878A - Manufacturing method of storage - Google Patents
Manufacturing method of storage Download PDFInfo
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- CN102543878A CN102543878A CN2010106210170A CN201010621017A CN102543878A CN 102543878 A CN102543878 A CN 102543878A CN 2010106210170 A CN2010106210170 A CN 2010106210170A CN 201010621017 A CN201010621017 A CN 201010621017A CN 102543878 A CN102543878 A CN 102543878A
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Abstract
The invention discloses a manufacturing method of a storage. The manufacturing method comprises the following steps of: providing a substrate comprising a storage unit region and a peripheral region, wherein a plurality of grids with clearance walls are formed on the substrate, and a plurality of openings are formed among the grids of the storage unit region; forming a first material layer in the storage unit region to cover the grids and fill the openings; forming a barrier layer on the substrate to cover the grids of the peripheral region and the first material layer of the storage unit region; forming a second material layer on the substrate of the peripheral region to cover the barrier layer on the grids of the peripheral region; removing the barrier layer covering the first material layer; removing a part of the first material layer to form a plurality of second openings, wherein the second openings are positioned on the tops of the grids of the storage unit region; forming patterns in the second openings; removing the first material layer to form a plurality of contact window openings; and forming a contact window plug in each contact window opening. According to the method, a process can be simplified, and the storage has good properties.
Description
Technical field
The present invention relates to a kind of manufacturing approach of memory.
Background technology
In general, along with the size of memory is dwindled gradually, aim at contact hole (self-aligned contact, SAC) technology voluntarily in order to overcome more and more little live width and to prevent contact hole generation aligning mistake (misalignment), can adopting.
In aiming at contact hole technology voluntarily, the clearance wall thickness of gate lateral wall can influence the size that is formed at the contact hole between the grid.Yet, because memory component comprises memory cell areas and external zones, and the element of memory cell areas and external zones for clearance wall thickness require differently, so increased the complexity of technology.In general, can on the gate lateral wall of memory cell areas and external zones, form the ground floor clearance wall simultaneously, then, for source electrode and the drain region that forms external zones, meeting forms second layer clearance wall again on the ground floor clearance wall of the grid of external zones usually.Wherein, For technology easy; Can second layer spacer material be inserted the opening between the grid of memory cell areas simultaneously; And in the substrate of external zones, form after source electrode and the drain region, remove the second layer spacer material between the grid of second layer clearance wall and memory cell areas of external zones more in the lump.
Yet because the opening between the grid of memory cell areas has bigger depth-to-width ratio, it totally is very difficult therefore will the second layer spacer material between the grid being removed, and in removing process, may hurt the ground floor clearance wall of memory cell areas.Thus, cause the ground floor clearance wall excellent electrical property insulation to be provided for grid, and the size that influences the formed contact hole of later use ground floor clearance wall.In addition, the not good condition that removes can cause damage to the substrate of external zones, causes element characteristic to be degenerated.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing approach of memory, to simplify step and to make memory have good element characteristic.
The present invention proposes a kind of manufacturing approach of memory.At first, a substrate is provided, substrate comprises a memory cell areas and an external zones, has been formed with a plurality of grids in the substrate, and has one first clearance wall on the sidewall of each grid, wherein has a plurality of first openings between the grid of memory cell areas.Then, in the substrate of memory cell areas, form one first material layer, the grid of the first layer of material covers memory cell areas and fill up first opening.Then, in substrate, form a barrier layer, with the grid of covering external zones and first material layer of memory cell areas.Then, in the substrate of external zones, form one second material layer, with the barrier layer on the grid that covers external zones.Then, remove the barrier layer that covers first material layer.Then, remove part first material layer, forming a plurality of second openings, each second opening is positioned on the top of each grid of memory cell areas.Then, in each second opening, form one first pattern.Then, remove remaining first material layer, to form a plurality of contact windows in memory cell areas.Then, in each contact window, form a contact hole connector, wherein first pattern arrangement is between the contact hole connector.
Beneficial effect of the present invention is; Based on above-mentioned; The manufacturing approach of memory of the present invention is protected the element of memory cell areas and external zones respectively with first material layer and second material layer; Therefore when one of them deposits with processing such as etching to external zones and memory cell areas, in external zones and the memory cell areas wherein another can not come to harm, the structure that the gap wall energy on the gate lateral wall is remained intact.Thus, the gap wall energy is that grid provides the excellent electrical property insulation, and can between two adjacent segment walls, form the self-aligned contact hole, makes memory have good element characteristic.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Fig. 1 to Fig. 9 is the manufacturing approach flow process generalized section according to a kind of memory of one embodiment of the invention.
Wherein, description of reference numerals is following:
100: substrate
102: memory cell areas
104: external zones
110,120: grid
110a: top
112,122,124: clearance wall
114,132: opening
126: source electrode and drain region
130,150: material layer
134,135: contact window
136,137: the contact hole connector
140: barrier layer
150a: end face
160: pattern
Embodiment
Fig. 1 to Fig. 9 is the flow process generalized section according to the manufacturing approach of a kind of memory of one embodiment of the invention.
Please with reference to Fig. 1; At first; Substrate 100 is provided, and substrate 100 comprises memory cell areas 102 and external zones 104, has been formed with a plurality of grids 110,120 in the substrate 100; And have first clearance wall 112,122 on the sidewall of grid 110,120, wherein have a plurality of first openings 114 between the grid 110 of memory cell areas 102.Substrate 100 for example is the semiconductor-based end, like the silicon base of N type or P type, three or five families semiconductor-based end etc.The material of grid 110,120 for example is a DOPOS doped polycrystalline silicon, and the material of first clearance wall 112,122 for example is a silicon nitride.
Please, then, in substrate 100, form first material layer, 130, the first material layers 130 and cover memory cell areas 102 and external zones 104, and first material layer 130 fills up opening 114 with reference to Fig. 2.First material layer 130 for example is a polysilicon layer, and its formation method for example is a chemical vapour deposition technique.In the present embodiment, this step also comprises and first material layer 130 is carried out (chemical mechanical polishing CMP) waits flatening process such as chemical mechanical milling tech.
Please, then, remove first material layer 130 that covers external zones 104, to expose external zones 104 with reference to Fig. 3.The method that removes first material layer 130 for example be reactive ion-etching (reactive ion etch, RIE).
Please with reference to Fig. 4, then, on first clearance wall 122 of the grid 120 of external zones 104, form second clearance wall 124.The formation method of second clearance wall 124 for example is in substrate 100, to form spacer material layer (not shown) with methods such as chemical vapour deposition techniques earlier; Carry out anisotropic etching process afterwards again and remove part spacer material layer, on first clearance wall 122, to form the clearance wall structure.Wherein, the material of second clearance wall 124 for example is a silicon nitride, and removing part spacer material layer for example is reactive ion-etching with the method that forms second clearance wall 124.
Then, for example be to be mask with second clearance wall 124, carry out one and implant technology, form source electrode and drain region 126 with grid 120 both sides in external zones 104.Special one carry be, after grid 120 both sides of external zones 104 form source electrode and drain region 126, can remove or not remove second clearance wall 124, be to be example in the present embodiment not remove second clearance wall 124.In other words, the step that removes second clearance wall 124 is actually optional step.
Special one carry be; When forming second clearance wall, can simultaneously spacer material be inserted the opening between the grid of memory cell areas compared to known technology; Or when removing second clearance wall, remove the spacer material layer in the opening together with time shift; In the present embodiment; Since first material layer 130 can covering protection memory cell areas 102 grid 110 and first clearance wall 112, the therefore formation of second clearance wall 124 or remove technology (comprise and depositing or technology such as etching) and can the grid 110 or first clearance wall 112 of memory cell areas 102 do not damaged, the structure that first clearance wall 112 of memory cell areas 102 can be remained intact.In other words, first material layer 130 is applicable to that protection memory cell areas 102 avoids receiving the destruction that any treatment process that external zones 104 carried out possibly cause.
Please, then, in substrate 100, form a barrier layer 140, with first material layer 130 of covering memory cell areas 102 and the grid 120 of external zones 104 with reference to Fig. 5.In the present embodiment, barrier layer 140 for example is surface and first material layer 130 of memory cell areas 102 that covers grid 120, first clearance wall 122 and second clearance wall 124 of external zones 104.
Then, in the substrate 100 of external zones 104, form one second material layer 150, with the barrier layer 140 on the grid 120 that covers external zones 104.In the present embodiment, second material layer 150 for example is to comprise boric acid silex glass or silica, and its formation method for example is a chemical vapour deposition technique.In the present embodiment; This step for example is prior to form one second material layer that covers external zones 104 and memory cell areas 102 on the substrate 100 comprehensively; Follow with the barrier layer 140 on first material layer 130 as etch stop layer; Second material layer is carried out flatening process, make end face 150a and the end face of barrier layer 140 of second material layer 150 rough equate and essence at grade upper.Wherein, flatening process for example is to comprise a chemical mechanical milling tech.
In general, if on first material layer 130 of memory cell areas 102, form barrier layer 140, then when second material layer 150 is carried out flatening process, can be with the top of first material layer 130 as etch stop layer.Thus, overetched problem may take place in second material layer 150, and possibly cause first material layer 130 that surperficial depressed phenomenon is arranged.Yet; In the present embodiment; Because be coated with barrier layer 140 on first material layer 130 of memory cell areas 102, so when second material layer 150 is carried out flatening process, can be with the barrier layer 140 on first material layer 130 as etch stop layer; And, therefore can avoid second material layer 150 and first material layer 130 that the problems referred to above take place because barrier layer 140 has higher density usually.
Please, then, remove the barrier layer 140 of first material layer 130 that covers memory cell areas 102 with reference to Fig. 6.The method that removes part barrier layer 140 for example is a dry etch process.
Then, remove part first material layer 130, to form a plurality of second openings 132.In the present embodiment, the method that removes part first material layer 130 comprises reactive ion-etching.Special one carry be; In the present embodiment; In the step that forms second opening 132, because the zone of external zones 104 entirely by second material layer, 150 covering protections, therefore need not to take into account whether can hurt external zones 104 on selecting in order to the etching condition that removes part first material layer 130; And can use preferable etching condition to remove part first material layer 130, with obtain having vertically profiling second opening 132 of (vertical profile).For instance, in the selection of etchant, need not consider whether employed etchant has the high etching ratio of selecting for first material layer 130 and grid 120, and can be only select with regard to the viewpoint of the opening that can obtain to have preferred profile.
Please, then, in each second opening 132, form one first pattern 160 with reference to Fig. 7.The material of first pattern 160 for example is to comprise boron-phosphorosilicate glass or silica, with and forming method thereof for example be chemical vapor deposition method.
Please, then, remove remaining first material layer 130, to form a plurality of contact windows 134 in memory cell areas 102 with reference to Fig. 8.The method that removes first material layer 130 for example is dry-etching method or wet etching.Then, remove the part of second material layer 150 that is positioned at external zones 104, to form contact window 135 in external zones 104, wherein contact window 135 exposes source electrode and drain region 126.The method that removes second material layer 150 for example is dry-etching method or wet etching.
Please, then, in contact window 134,135, insert conductor material layer with reference to Fig. 9, with formation contact hole connector 136 between adjacent two first clearance walls 112, and in external zones 104 formation contact hole connectors 137.The material of contact hole connector 136,137 for example is tungsten, copper, aluminium or other suitable metals.
In the present embodiment; Be earlier with first material layer, 130 protection memory cell areas 102; Be beneficial to external zones 104 is handled (such as forming and remove second clearance wall 124); With the etch stop layer of the barrier layer 140 on first material layer 130, there are the overetched problem and first material layer 130 that the phenomenon of surface depression is arranged again to avoid second material layer 150 as formation second material layer 150.Then, remove first material layer 130 with the technology that forms first pattern 160 in because second material layer 150 can protect external zones 104, make the pattern 160 of winning have preferable vertically profiling.In addition; Because first clearance wall 112 of memory cell areas 102 can be covered by first material layer 130; Therefore first clearance wall 112 can not receive external zones 104 treatment process (such as the formation of second clearance wall with remove) influence; And can the excellent electrical property insulation be provided, and can between intact first clearance wall, 112 structures, form contact hole connector 136 for grid 110.
In sum; In the manufacturing approach of memory of the present invention; Protect the element of memory cell areas and external zones respectively with first material layer and second material layer; Therefore when one of them deposits with processing such as etching to external zones and memory cell areas, in external zones and the memory cell areas wherein another can not come to harm, the structure that the gap wall energy on the gate lateral wall is remained intact.In addition; When forming second material layer; Owing to be formed with barrier layer on first material layer, therefore can protect first material layer that problems such as depression can not take place because of the flatening process of second material layer, help the follow-up pattern that defines the contact hole connector that in first material layer, forms.Particularly; In the step that forms in order to the pattern that defines the contact hole connector; Because the grid of external zones is protected by second layer of material covers; Therefore need not to take into account under the condition of the grid that whether can hurt external zones and clearance wall and select preferable etching mode, the pattern that has preferred profile with acquisition.Thus, the clearance wall of memory cell areas and external zones all has complete structure, therefore can between two adjacent segment walls, form the self-aligned contact hole, makes memory have good element characteristic.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, and any affiliated person skilled is not breaking away from the spirit and scope of the present invention; When doing a little change and retouching,, protection scope of the present invention is as the criterion so working as the claim person of defining who looks.
Claims (8)
1. the manufacturing approach of a memory comprises step:
One substrate is provided, and this substrate comprises a memory cell areas and an external zones, has been formed with a plurality of grids in this substrate, and respectively has one first clearance wall on the sidewall of this grid, wherein has a plurality of first openings between said a plurality of grids of this memory cell areas;
In this substrate of this memory cell areas, form one first material layer, said a plurality of grids of this this memory cell areas of first layer of material covers and fill up said a plurality of first opening;
In this substrate, form a barrier layer, with said a plurality of grids of covering this external zones and this first material layer of this memory cell areas;
In this substrate of this external zones, form one second material layer, with this barrier layer on the said a plurality of grids that cover this external zones;
Remove this barrier layer that covers this first material layer;
Remove this first material layer of part, to form a plurality of second openings, respectively this second opening is positioned on the top of respectively this grid of this memory cell areas;
In respectively forming one first pattern in this second opening;
Remove remaining this first material layer, to form a plurality of contact windows in this memory cell areas; And
In respectively forming a contact hole connector in this contact window, wherein said a plurality of first pattern arrangement are between said a plurality of contact hole connectors.
2. the manufacturing approach of memory as claimed in claim 1 is characterized in that, this manufacturing approach also comprises step:
On this first clearance wall of respectively this grid of this external zones, form one second clearance wall; And
With said a plurality of second clearance walls is mask, forms one source pole and drain region in respectively these grid both sides of this external zones.
3. the manufacturing approach of memory as claimed in claim 2 is characterized in that, this barrier layer more covers said a plurality of second clearance wall.
4. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of this barrier layer comprises silicon nitride.
5. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the step that forms this second material layer comprises:
In this substrate, form one second material layer that comprehensively covers; And
With this barrier layer on this first material layer is an etch stop layer, and this second material layer is carried out a flatening process.
6. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of this second material layer comprises boric acid silex glass or silica.
7. the manufacturing approach of memory as claimed in claim 1 is characterized in that, this first material layer comprises polysilicon.
8. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of said first pattern comprises boron-phosphorosilicate glass or silica.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010621017.0A CN102543878B (en) | 2010-12-24 | 2010-12-24 | Manufacturing method of storage |
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| CN201010621017.0A CN102543878B (en) | 2010-12-24 | 2010-12-24 | Manufacturing method of storage |
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| CN102543878B CN102543878B (en) | 2014-02-12 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716084A (en) * | 2013-12-12 | 2015-06-17 | 华邦电子股份有限公司 | Method for manufacturing semiconductor element |
| DE102017120886A1 (en) * | 2017-08-01 | 2019-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method |
| US10263004B2 (en) | 2017-08-01 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455362B1 (en) * | 2000-08-22 | 2002-09-24 | Micron Technology, Inc. | Double LDD devices for improved dram refresh |
| TW511249B (en) * | 2000-09-18 | 2002-11-21 | Samsung Electronics Co Ltd | Semiconductor memory device and method for manufacturing the same |
| US20040185671A1 (en) * | 2003-03-21 | 2004-09-23 | Seong-Wook Lee | Method for fabricating semiconductor device |
| CN1855433A (en) * | 2005-04-21 | 2006-11-01 | 旺宏电子股份有限公司 | Production of memory |
-
2010
- 2010-12-24 CN CN201010621017.0A patent/CN102543878B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455362B1 (en) * | 2000-08-22 | 2002-09-24 | Micron Technology, Inc. | Double LDD devices for improved dram refresh |
| TW511249B (en) * | 2000-09-18 | 2002-11-21 | Samsung Electronics Co Ltd | Semiconductor memory device and method for manufacturing the same |
| US20040185671A1 (en) * | 2003-03-21 | 2004-09-23 | Seong-Wook Lee | Method for fabricating semiconductor device |
| CN1855433A (en) * | 2005-04-21 | 2006-11-01 | 旺宏电子股份有限公司 | Production of memory |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716084A (en) * | 2013-12-12 | 2015-06-17 | 华邦电子股份有限公司 | Method for manufacturing semiconductor element |
| CN104716084B (en) * | 2013-12-12 | 2017-10-27 | 华邦电子股份有限公司 | The manufacture method of semiconductor element |
| DE102017120886A1 (en) * | 2017-08-01 | 2019-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method |
| US10263004B2 (en) | 2017-08-01 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
| US10629605B2 (en) | 2017-08-01 | 2020-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
| US11075212B2 (en) | 2017-08-01 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing |
| DE102017120886B4 (en) | 2017-08-01 | 2022-03-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated chip comprising gate structures with sidewall spacers and manufacturing method |
| US11903192B2 (en) | 2017-08-01 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing |
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| CN102543878B (en) | 2014-02-12 |
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