CN102543879B - Method for manufacturing gate-last one-transistor dynamic random access memory - Google Patents
Method for manufacturing gate-last one-transistor dynamic random access memory Download PDFInfo
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- CN102543879B CN102543879B CN201110265306.6A CN201110265306A CN102543879B CN 102543879 B CN102543879 B CN 102543879B CN 201110265306 A CN201110265306 A CN 201110265306A CN 102543879 B CN102543879 B CN 102543879B
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Abstract
The invention discloses a method for manufacturing a gate-last one-transistor dynamic random access memory to solve the problem in the prior art that processes lack manufacturability. The method for manufacturing the silicon on insulator gate-last one-transistor dynamic random access memory (SOI Gate-last 1T DRAM) with design for manufacturability (DFM) is suitable for preparing integrated circuit of a 45nm or less high-k metal gate (HKMG) (high dielectric constant oxide layer+ metal gate) gate-last processes. By using the method for manufacturing the gate-last one-transistor dynamic random access memory and through achievement of gate sources different from conventional complementary metal oxide semiconductor (CMOS) processes, gate induced drain leakage (GIDL) effect or band-to-band tunneling (BTBT) effect is effectively eliminated, and accordingly electric leakage is restrained, charging speed rate is fastened, and retention time is prolonged.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor memory, relate in particular to a kind of manufacture method of rear grid single-transistor dynamic random access memory.
Background technology
Along with constantly dwindling of semiconductor device characteristic size, tradition 1T/1C DRAM unit is in order to obtain enough amount of storage capacity (General Requirements 30fF/cell), its electric capacity preparation technology (stack capacitor or deep-trench capacitor) will become increasingly complex, and with logical device processing compatibility worse and worse.Therefore, compatible good in electric capacity DRAM(Capacitorless DRAM with logical device) will in VLSI, there is good development prospect in high-performance embedded DRAM field.1T-DRAM(one transistor dynamic random access memory wherein) because its cell size only has 4F
2and become the study hotspot of current Capacitorless DRAM.
1T-DRAM is generally a SOI buoyancy aid (floating body) transistor, and when being charged in its tagma, i.e. the accumulation in hole, tagma completes one writing, at this moment, because the accumulation of hole, tagma causes body effect, causes transistorized threshold voltage to reduce.When being discharged in its tagma, the hole by its tagma accumulation of the positive assistant general of body drain PN junction has bled off to write " 0 ", and at this moment body effect disappears, and threshold voltage recovering is normal.And read operation is the source-drain current while reading this transistor opening, different with the threshold voltage of " 0 " state due to " 1 ", both source-drain currents are also different, and what when larger, represent to read is " 1 ", and what hour represent to read is " 0 ".
According to the difference of one writing method of operation, 1T-DRAM can be divided into two classes, when a class adopts transistor to work in saturation region, passes through ionization by collision (impact-ionization) in accumulation hole, tagma, and a class adopts GIDL effect making accumulation hole, tagma.Adopting the 1T-DRAM of impact ionization is the study hotspot of current 1T-DRAM.But adopt the 1T-DRAM of impact ionization to there are the following factors of instability:
1, when certain cell is during at Hold state, its WL is low-voltage, this is due to grid leak overlap, easily be subject to the electric disturbance (same BL is listed as the read-write operation of other cell) of BL end and produce GIDL effect or band-band penetration tunnel (BTBT, Band-to-Band Tunneling) effect, thereby cause the floater area charge conversion of this cell, especially Hold " 0 " time GIDL effect or BTBT effect can cause the accumulation of floater area hole, cause charge conversion, cause the retention time (retention time) to shorten.
2, when grid length diminishes, short-channel effect (SCE, Short Channel Effect) becomes more and more serious, and effective stored charge when serious, causes DRAM inefficacy.
For this reason, the people such as Ki-Whan Song are at paper (55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure, Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 15-17 Dec. 2008, a kind of elimination grid leak overlap is proposed to eliminate GIDL or BTBT effect page:1 – 4), increase the method in charge storage space, increase grid curb wall thickness, injection condition and follow-up thermal budget are leaked in adjustment source, to reach grid source, grid leak is without the object of overlap.
The method take that to change stand CMOS be cost, can affect cmos device correlated performance, and follow-up Contact technology difficulty is increased.With stand CMOS poor compatibility.
Summary of the invention
The invention discloses a kind of manufacture method of rear grid single-transistor dynamic random access memory, so that a kind of grid source, grid leak underlap characteristic of stand CMOS to be provided, to eliminate the penetration tunnel between GIDL (grid induction drain leakage) effect or BTBT(band and band) effect, reach the object that suppresses electric leakage, accelerates charge rate, and solved the problem of technique shortage manufacturability in prior art.
To achieve these goals, the technical scheme that the present invention takes is:
A kind of manufacture method of rear grid single-transistor dynamic random access memory, at a silicon-on-insulator (Silicon on Insulator, SOI) in substrate, be formed with the transistorized rear grid high-k MOS structure that comprises of making by rear grid technology, there is overlap-add region with transistor gate groove respectively in transistorized drain electrode and source electrode, wherein, comprise the following steps:
Step a: carry out wet etching, the sample grid in the transistor gate groove of above-mentioned transistor device are removed, wherein, high dielectric layer and metal oxide dielectric materials layer both can be previously prepared when preparing sample grid also can prepare after removing sample grid;
Step b: the tilted certain angle of transistor gate groove is carried out angle-tilt ion injection, and auto-alignment flows into metal oxide dielectric materials layer, increase the work function at grid groove place, so that the diffusion zone transoid of transistor gate groove below is the doping type identical with this transistorized well region.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, transistor is set to: source electrode is N+ type, drains as N+ type, and well region is P type.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, step b Implantation direction be near transistor drain one side angle angle-tilt ion inject.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, described work function is larger ion, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, the angle bi-directional symmetrical angle-tilt ion injection of step b Implantation for tilting certain, direction be close transistor source one side in transistor gate groove angle angle-tilt ion inject, other direction be close transistor drain one side in transistor gate groove angle angle-tilt ion inject, to increase the work function at grid groove place, it is P type that injection ion makes the source of transistorized grid lower end leak diffusion zone transoid.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, transistor is set to: source electrode is N+ type, drains as N+ type, and well region is P type.
The manufacture method of above-mentioned rear grid single-transistor dynamic random access memory, wherein, described work function is larger example, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.
The present invention is owing to having adopted above-mentioned technology, and the good effect that makes it to have is:
The grid source that is different from stand CMOS by realization, effectively eliminate GIDL(grid induction drain leakage) effect or BTBT(band be with between penetration tunnel) effect, thereby suppress electric leakage, accelerate charge rate, increase the retention time (retention time).
Accompanying drawing explanation
Fig. 1 is the monolateral flow chart of drain terminal of the manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention.
Fig. 2 is the bilateral flow chart of drain terminal of the manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment, the invention will be further described.
First adopt drain terminal monolateral:
Fig. 1 is the monolateral flow chart of drain terminal of the manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention, shown in Figure 1.The manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention wherein, forms a rear grid high-k MOS structure that comprises single-transistor 1 by rear grid technology on a P type silicon-on-insulator substrate; Transistor 1 is set to source electrode 11 for N+ type, and drain electrode 12 is N+ type, and well region 13 is P type.
The first step: carry out wet etching, sample grid in the transistor gate groove 14 of transistor 1 device are removed, should be noted that a bit, wherein, high dielectric layer and metal oxide dielectric materials layer both can be previously prepared when preparing sample grid, also can after removing sample grid, prepare.
Second step: the angle angle-tilt ion that tilts certain is injected, this ion can inject metal oxide dielectric materials layer 2 by auto-alignment, and 14 places carry out the adjusting of work function for grid groove, this work function is larger ion, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.Carrying out the angle angle-tilt ion of close transistor 1 drain electrode 12 1 sides in transistor gate groove 14 injects, making the channel region transoid near drain terminal under the grid of transistor 1 is P type, making horizontal proliferation to the diffusion zone transoid of transistor gate groove 14 belows in the drain region of transistor 11 is the identical doping type of well region 13 with transistor 1, that is to say that transoid is P type, thus the drain electrode 12 that makes transistor 1 with transistor gate groove 14 without overlap-add region.
The 3rd step: the MOS structural manufacturing process of carrying out the silicon-on-insulator of follow-up routine.
Employing drain terminal is bilateral:
Fig. 2 is the bilateral flow chart of drain terminal of the manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention, shown in Figure 2.The manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention wherein, forms a rear grid high-k MOS structure that comprises single-transistor 1 by rear grid technology on a P type silicon-on-insulator substrate; Transistor 1 is set to source electrode 11 for N+ type, and drain electrode 12 is N+ type, and well region 13 is P type.
The first step: carry out wet etching, sample grid in the transistor gate groove 14 of transistor 1 device are removed, should be noted that a bit, wherein, high dielectric layer and metal oxide dielectric materials layer both can be previously prepared when preparing sample grid, also can after removing sample grid, prepare.
Second step: the angle bi-directional symmetrical angle-tilt ion that tilts certain is injected, an angle angle-tilt ion injection that direction is close transistor 1 source electrode 11 1 sides in transistor gate groove 14, other direction is that the angle angle-tilt ion of close transistor 1 drain electrode 12 1 sides in transistor gate groove 14 is injected.This ion can inject metal oxide dielectric materials layer 2 by auto-alignment, and 14 places carry out the adjusting of work function for grid groove, this work function is larger ion, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.Carrying out the angle angle-tilt ion of close transistor 1 drain electrode 12 1 sides in transistor gate groove 14 injects, making the channel region transoid near source and drain terminal under the grid of transistor 1 is P type, making the source region of transistor 11 and the horizontal proliferation in drain region to the diffusion zone transoid of transistor gate groove 14 belows is the identical doping type of well region 13 with transistor 1, that is to say that transoid is P type, thus the drain electrode 12 that makes transistor 1 with transistor gate groove 14 without overlap-add region.
The 3rd step: the MOS structural manufacturing process of carrying out the silicon-on-insulator of follow-up routine.
In sum, use the manufacture method of a kind of rear grid single-transistor dynamic random access memory of the present invention, the grid source that is different from stand CMOS by realization, effectively eliminate GIDL(grid induction drain leakage) effect or BTBT(band be with between penetration tunnel) effect, thereby suppress electric leakage, accelerate charge rate, increase the retention time (retention time).
Above specific embodiments of the invention are described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the method for wherein not describing in detail to the greatest extent and processing procedure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not affect flesh and blood of the present invention.All any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. the manufacture method of grid single-transistor dynamic random access memory after a kind, in a silicon-on-insulator substrate, be formed with the transistorized rear grid high-k MOS structure that comprises of making by rear grid technology, there is overlap-add region with transistor gate groove respectively in transistorized drain electrode and source electrode, it is characterized in that, comprise the following steps:
Step a: carry out wet etching, sample grid in the transistor gate groove of above-mentioned transistor device are removed, wherein, high dielectric layer and metal oxide dielectric materials layer are both previously prepared when preparing sample grid or prepare after removing sample grid;
Step b: the certain angle of inclination in transistor gate groove is carried out angle-tilt ion injection near transistor drain one side, and auto-alignment flows into metal oxide dielectric materials layer, increase the work function at grid groove place, so that the diffusion zone transoid of transistor gate groove below is the doping type identical with this transistorized well region.
2. the manufacture method of rear grid single-transistor dynamic random access memory as claimed in claim 1, is characterized in that, transistor is set to: source electrode is N+ type, drains as N+ type, and well region is P type.
3. the manufacture method of rear grid single-transistor dynamic random access memory as claimed in claim 2, is characterized in that, it is P type that injection ion makes the drain diffusion region transoid of transistorized grid lower end.
4. the manufacture method of the rear grid single-transistor dynamic random access memory as described in claim as arbitrary in claims 1 to 3, it is characterized in that, described work function is larger ion, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.
5. the manufacture method of rear grid single-transistor dynamic random access memory as claimed in claim 1, it is characterized in that, the angle bi-directional symmetrical angle-tilt ion injection of step b Implantation for tilting certain, an angle angle-tilt ion injection that direction is close transistor source one side in transistor gate groove, other direction is that the angle angle-tilt ion of close transistor drain one side in transistor gate groove is injected, to increase the work function at grid groove place, it is P type that injection ion makes the source of transistorized grid lower end leak diffusion zone transoid.
6. the manufacture method of rear grid single-transistor dynamic random access memory as claimed in claim 5, is characterized in that, transistor is set to: source electrode is N+ type, drains as N+ type, and well region is P type.
7. the manufacture method of rear grid single-transistor dynamic random access memory as claimed in claim 5, it is characterized in that, described work function is larger ion, adopts the ion that B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po element are base.
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| US6087231A (en) * | 1999-08-05 | 2000-07-11 | Advanced Micro Devices, Inc. | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| CN1527398A (en) * | 2003-03-06 | 2004-09-08 | 北京大学 | Combined-grid FET |
| CN1815742A (en) * | 2004-12-15 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Storage unit and method for forming a storage unit |
| US20080286928A1 (en) * | 2007-05-15 | 2008-11-20 | Masataka Minami | method of manufacturing a semiconductor integrated circuit device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087231A (en) * | 1999-08-05 | 2000-07-11 | Advanced Micro Devices, Inc. | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| CN1527398A (en) * | 2003-03-06 | 2004-09-08 | 北京大学 | Combined-grid FET |
| CN1815742A (en) * | 2004-12-15 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Storage unit and method for forming a storage unit |
| US20080286928A1 (en) * | 2007-05-15 | 2008-11-20 | Masataka Minami | method of manufacturing a semiconductor integrated circuit device |
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