CN102569426B - PN junction voltage-controlled varactor and preparation method thereof - Google Patents
PN junction voltage-controlled varactor and preparation method thereof Download PDFInfo
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- CN102569426B CN102569426B CN201010598359.5A CN201010598359A CN102569426B CN 102569426 B CN102569426 B CN 102569426B CN 201010598359 A CN201010598359 A CN 201010598359A CN 102569426 B CN102569426 B CN 102569426B
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- epitaxial loayer
- variodenser
- ion implanted
- implanted layer
- groove
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Abstract
The invention discloses a PN junction voltage-controlled varactor, a first epitaxial layer with the same conductivity type is arranged on a substrate, the first epitaxial layer contains at least one trench, a heavily doped ion implantation layer with the conductivity type opposite to that of the epitaxial layer is covered on the inner wall of the trench and the upper surface of the first epitaxial layer, a second epitaxial layer is filled in the trench, and the second epitaxial layer has the same conductivity type with the first epitaxial layer. The heavily doped ion implantation layer is connected through a front metal to form one electrode of the voltage-controlled varactor, the second epitaxial layer is also connected through the front metal to form the other electrode of the voltage-controlled varactor, and the two electrodes are separated by photoetching and etching. The back surface of the substrate is connected with a back metal, and when a chip is packaged, the back metal is connected with the electrode connected with the second epitaxial layer. The result of the invention shows that the junction area of a PN junction is enlarged, and the regulation range of capacitance value is widened. The invention further discloses a preparation method of the PN junction voltage-controlled varactor.
Description
Technical field
The present invention relates to a kind of PN junction voltage control variodenser.
Background technology
Phase-locked loop has application extremely widely in analog circuit and radio circuit, and voltage control variodenser is a Primary Component in phase-locked loop.The capacitance adjustable extent of voltage control variodenser plays vital impact to the performance of phase-locked loop.
Existing voltage control variodenser mainly contains two kinds of structures: a kind of is to adopt mos capacitance, wherein Semiconductor substrate S (for example silicon) is through light dope, between metal or polysilicon gate and substrate, add bias voltage, substrate forms depletion layer, thereby voltage-regulation depletion widths regulates the capacitance of variodenser; Another kind is PN junction structure, by its reverse biased, regulates the width of knot depletion region to regulate the capacitance of variodenser.The capacity valve regulating range of these two kinds of variodensers can improve by change structure.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of PN junction voltage control variodenser, and it has larger capacity valve regulating range.
For solving the problems of the technologies described above, PN junction voltage control variodenser of the present invention, for there is the first epitaxial loayer of identical conduction type on substrate, in described the first epitaxial loayer, comprise at least one groove, the inwall of described groove and described the first epitaxial loayer upper surface are coated with the ion implanted layer that conduction type is contrary with epitaxial loayer, the second epitaxial loayer is filled in described groove, described ion implanted layer is connected to form an electrode of voltage control variodenser by metal, described the second epitaxial loayer is also connected to form another electrode of voltage control variodenser by metal, described the second epitaxial loayer is connected by metal with described substrate simultaneously.
The preparation method who the invention still further relates to a kind of PN junction voltage control variodenser, comprises the steps:
(1) at Grown and substrate, there is the first epitaxial loayer of identical conduction type;
(2) adopt ion implantation technology, in described the first epi-layer surface, form ion implanted layer, the conduction type of described ion implanted layer is contrary with described the first epitaxial loayer;
(3) deposit etching barrier layer on described the first epitaxial loayer;
(4) adopt photoetching process to define groove, then etching barrier layer and described the first epitaxial loayer described in etching, form groove;
(5) utilize described etching barrier layer, adopt ion implantation technology to inject ion at described trench wall, identical with step (2) of its Implantation Energy and implantation concentration, the inclination angle of ion beam is made as 7-80 degree, at described trench wall, forms ion implanted layer;
(6) epitaxial growth for the second time, makes the second epitaxial loayer fill described groove, removes afterwards etching barrier layer;
(7) described ion implanted layer is connected to form to an electrode of voltage control variodenser by metal, the second epitaxial loayer is also connected to form another electrode of voltage control variodenser by metal, the second epitaxial loayer and substrate are electrically connected to.
PN junction voltage control variodenser of the present invention, has wherein designed serpentine configuration, makes the junction area of PN junction become large, and while adding reverse biased, depletion region broadens, and makes capacity valve regulating range become large.The design of the second epitaxial loayer, makes the depletion region of PN junction become large, further strengthens the adjustable range of capacitance.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the structural representation of PN junction voltage control variodenser of the present invention;
Fig. 2 is the schematic diagram of Implantation for the first time;
Fig. 3 is the structural representation after Implantation for the first time;
Fig. 4 is that etching forms the structural representation after groove;
Fig. 5 is the schematic diagram of Implantation for the second time;
Fig. 6 is the structural representation after Implantation for the second time;
Fig. 7 is the structural representation after epitaxial growth for the second time;
Fig. 8 is the structural representation of PN junction voltage control variodenser of the present invention;
Fig. 9 is preparation flow schematic diagram of the present invention.
Embodiment
PN junction voltage control variodenser of the present invention, concrete structure is (seeing Fig. 1): first epitaxial loayer on substrate with identical conduction type, in the first epitaxial loayer, comprise at least one groove, the inwall of groove and the first epitaxial loayer upper surface are coated with the ion implanted layer that conduction type is contrary with epitaxial loayer, the second epitaxial loayer is filled in groove, and the second epitaxial loayer is identical with the conduction type of the first epitaxial loayer.Heavy doping ion implanted layer is connected to form an electrode of voltage control variodenser by front metal, the second epitaxial loayer is also connected to form another electrode of voltage control variodenser by front metal, and above-mentioned two electrodes by photoetching, etching separately.At substrate back deposit back metal, when chip package, back metal is connected with the electrode that is connected second layer extension.The doping content of ion implanted layer is greater than the doping content of the first epitaxial loayer and the second epitaxial loayer conventionally.
In said structure, the doping content of substrate can be 10
14-10
16individual atom/cm
2, the doping content of the first epitaxial loayer is 10
12-10
14individual atom/cm
2, the doping content of the second epitaxial loayer is 10
12-10
14individual atom/cm
2, the thickness of ion implanted layer is 0.1-1 micron, the doping content of ion implanted layer is: 10
14-10
16individual atom/cm
2.The concentration of the first epitaxial loayer and the second epitaxial loayer can be set to identical.The width of the groove in epitaxial loayer is 0.1-100 micron, and the degree of depth is 0.1-50 micron.The number of groove can arrange according to concrete capacity valve regulating range, and groove is more, and effectively PN junction junction area is larger, and capacitance adjustment scope is larger.
The preparation method of PN junction voltage control variodenser of the present invention, comprises the steps (seeing Fig. 9):
(1) at Grown and substrate, there is the first epitaxial loayer of identical conduction type;
(2) adopt ion implantation technology, in the first epi-layer surface, form ion implanted layer, the conduction type of ion implanted layer and the first epitaxial loayer contrary (seeing Fig. 2 and Fig. 3);
(3) deposit etching barrier layer (can be silicon oxide layer) on described the first epitaxial loayer;
(4) adopt photoetching process to define groove, then this etching barrier layer of etching and the first epitaxial loayer, form groove (seeing Fig. 4);
(5) utilize described etching barrier layer, adopt ion implantation technology to inject ion at described trench wall, identical with step (2) of its Implantation Energy and concentration, at described trench wall formation ion implanted layer.In this injection process, implant angle can be made as the inclination of 7-80 degree and inject (seeing Fig. 5 and Fig. 6).
(6) epitaxial growth for the second time, makes the second epitaxial loayer filling groove, removes afterwards etching barrier layer; Because the existence of etching barrier layer, epitaxial growth is only carried out at channel bottom and inwall, realizes selective epitaxial growth (seeing Fig. 7).
(7) ion implanted layer is connected to form to an electrode of voltage control variodenser by front metal, the second epitaxial loayer is also connected to form another electrode of voltage control variodenser by front metal, the second epitaxial loayer and substrate are electrically connected to.Above-mentioned two electrodes separate (seeing Fig. 8 and Fig. 1) by photoetching, etching.
Wherein the formation of electrode specifically can be:
1) deposit interlayer film on the first epitaxial loayer, then described in etching, interlayer film forms contact hole respectively on ion implanted layer and the second epitaxial loayer;
2) depositing metal filling contact hole forms contacting metal, by dry quarter or cmp removing the metal on interlayer film surface;
3) deposit front metal, forms respectively the metal wire of the second epitaxial loayer and the metal wire of ion implanted layer by photoetching and etching technics, as two electrodes.These two electrodes can form by the front metal figure separating;
4) by substrate back attenuate, deposit back metal afterwards;
5), when chip package, back metal is electrically connected to the electrode of the second epitaxial loayer.
In said method, the doping content of substrate can be 10
14-10
16individual atom/cm
2, the doping content of the first epitaxial loayer can be 10
12-10
14individual atom/cm
2, the doping content of the second epitaxial loayer can be 10
12-10
14individual atom/cm
2, the doping content of ion implanted layer can be: 10
14-10
16individual atom/cm
2.The width of groove can be 0.1-100 micron, and the degree of depth can be 0.1-50 micron, and the thickness of ion implanted layer can be 0.1-1 micron.
Claims (6)
1. a PN junction voltage control variodenser, it is characterized in that: first epitaxial loayer on substrate with identical conduction type, in described the first epitaxial loayer, comprise at least one groove, the inwall of described groove and described the first epitaxial loayer upper surface are coated with the ion implanted layer that conduction type is contrary with epitaxial loayer, the second epitaxial loayer is filled in described groove, described ion implanted layer is connected to form first electrode of voltage control variodenser by metal, described the second epitaxial loayer is also connected to form second electrode of voltage control variodenser by metal, described the second epitaxial loayer is connected by metal with described substrate simultaneously, the doping content of described ion implanted layer is greater than the doping content of described the first epitaxial loayer and the second epitaxial loayer,
Before the described ion implanted layer that is positioned at described the first epitaxial loayer upper surface is formed by described groove, in described the first epi-layer surface, inject and forms, after the described ion implanted layer that is positioned at described trench wall surface is formed by described groove, described the second epitaxial loayer fills the front Implantation that is 7-80 degree by inclination angle and form;
Interlayer film covers described the second epitaxial loayer and the described ion implanted layer surface between groove described in each, described ion implanted layer is connected with described first electrode by the contact hole through described interlayer film, and described the second epitaxial loayer is connected with second electrode by the contact hole through described interlayer film;
Described ion implanted layer exhausts from He Ge side, top, described first epitaxial loayer of channel bottom described in each is exhausted from top and forms the first variodenser described the first epitaxial loayer between groove described in each; Described ion implanted layer exhausts from bottom and each side described the second epitaxial loayer in groove described in each and forms the second variodenser; By described the first variodenser and described the second variodenser PN junction voltage control variodenser that forms in parallel; The maximum capacitor value of described the first variodenser is the capacitance of described the first epitaxial loayer while all exhausting, and the maximum capacitor value of described the second variodenser is the capacitance of described the second epitaxial loayer while all exhausting.
2. PN junction voltage control variodenser as claimed in claim 1, is characterized in that: the doping content of described substrate is 10
14-10
16individual atom/cm
2, the doping content of described the first epitaxial loayer is 10
12-10
14individual atom/cm
2, the doping content of described the second epitaxial loayer is 10
12-10
14individual atom/cm
2, the thickness of described ion implanted layer is 0.1-1 micron, the doping content of ion implanted layer is: 10
14-10
16individual atom/cm
2.
3. PN junction voltage control variodenser as claimed in claim 1, is characterized in that: the width of described groove is 0.1-100 micron, and the degree of depth is 0.1-50 micron.
4. a preparation method for PN junction voltage control variodenser, is characterized in that, comprises the steps:
(1) at Grown and substrate, there is the first epitaxial loayer of identical conduction type;
(2) adopt ion implantation technology, in described the first epi-layer surface, form ion implanted layer, the conduction type of described ion implanted layer is contrary with described the first epitaxial loayer;
(3) deposit etching barrier layer on described the first epitaxial loayer;
(4) adopt photoetching process to define groove, then etching barrier layer and described the first epitaxial loayer described in etching, form groove;
(5) utilize described etching barrier layer, adopt ion implantation technology to inject ion at described trench wall, identical with step (2) of its Implantation Energy and implantation concentration, the inclination angle of ion beam is made as 7-80 degree, at described trench wall, forms ion implanted layer;
(6) epitaxial growth for the second time, makes the second epitaxial loayer fill described groove, removes afterwards etching barrier layer;
(7) described ion implanted layer is connected to form to first electrode of voltage control variodenser by metal, the second epitaxial loayer is also connected to form second electrode of voltage control variodenser by metal, the second epitaxial loayer and substrate are electrically connected to;
Described ion implanted layer exhausts from He Ge side, top, described first epitaxial loayer of channel bottom described in each is exhausted from top and forms the first variodenser described the first epitaxial loayer between groove described in each; Described ion implanted layer exhausts from bottom and each side described the second epitaxial loayer in groove described in each and forms the second variodenser; By described the first variodenser and described the second variodenser PN junction voltage control variodenser that forms in parallel; The maximum capacitor value of described the first variodenser is the capacitance of described the first epitaxial loayer while all exhausting, and the maximum capacitor value of described the second variodenser is the capacitance of described the second epitaxial loayer while all exhausting; Described step (7) specifically can be:
1) deposit interlayer film on described the first epitaxial loayer, then described in etching, interlayer film forms contact hole respectively on ion implanted layer and the second epitaxial loayer;
2) depositing metal is filled described contact hole and is formed contacting metal;
3) deposit front metal, forms respectively the electrode of the second epitaxial loayer and the electrode of ion implanted layer by photoetching and etching technics;
4) by substrate back attenuate, deposit back metal afterwards;
5), when chip package, back metal is electrically connected to second electrode of described the second epitaxial loayer.
5. preparation method as claimed in claim 4, is characterized in that: the doping content of described substrate is 10
14-10
16individual atom/cm
2, the doping content of described the first epitaxial loayer is 10
12-10
14individual atom/cm
2, the doping content of described the second epitaxial loayer is 10
12-10
14individual atom/cm
2, the doping content of described ion implanted layer is: 10
14-10
16individual atom/cm
2.
6. preparation method as claimed in claim 4, is characterized in that: the width of described groove is 0.1-100 micron, and the degree of depth is 0.1-50 micron, and the thickness of described ion implanted layer is 0.1-1 micron.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010598359.5A CN102569426B (en) | 2010-12-21 | 2010-12-21 | PN junction voltage-controlled varactor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010598359.5A CN102569426B (en) | 2010-12-21 | 2010-12-21 | PN junction voltage-controlled varactor and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN102569426A CN102569426A (en) | 2012-07-11 |
| CN102569426B true CN102569426B (en) | 2014-10-08 |
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| CN104299902B (en) * | 2014-08-20 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | The structure and preparation method of the variable MIS electric capacity of capacitance |
| CN112864097B (en) * | 2021-01-14 | 2022-06-24 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112993083A (en) * | 2021-02-04 | 2021-06-18 | 华虹半导体(无锡)有限公司 | Method for manufacturing ultra-deep photodiode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153921A (en) * | 1998-11-05 | 2000-11-28 | Toko Kabushiki Kaisha | Diode device |
| CN1707809A (en) * | 2004-06-08 | 2005-12-14 | Nec化合物半导体器件株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350111A (en) * | 1993-06-10 | 1994-12-22 | Nec Corp | Varactor diode |
| JP2001102599A (en) * | 1999-09-29 | 2001-04-13 | Sanyo Electric Co Ltd | Variable capacitance semiconductor device |
| TWI246154B (en) * | 2004-08-04 | 2005-12-21 | Realtek Semiconductor Corp | Method for forming junction varactor by triple-well process |
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2010
- 2010-12-21 CN CN201010598359.5A patent/CN102569426B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153921A (en) * | 1998-11-05 | 2000-11-28 | Toko Kabushiki Kaisha | Diode device |
| CN1707809A (en) * | 2004-06-08 | 2005-12-14 | Nec化合物半导体器件株式会社 | Semiconductor device |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2001-102599A 2001.04.13 |
| JP特开平6-350111A 1994.12.22 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
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Effective date of registration: 20140103 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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